b3c74e6dd0
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p instructions to loose any special insn->architecture mask. * config/tc-sparc.c (v9a_asr_table): Add v9b ASRs. (sparc_md_end, sparc_arch_types, sparc_arch, sparc_elf_final_processing): Handle v8plusb and v9b architectures. (sparc_ip): Handle siam mode operands. Support v9b ASRs (and request v9b architecture if they are used). bfd/ * elf32-sparc.c (elf32_sparc_merge_private_bfd_data, elf32_sparc_object_p, elf32_sparc_final_write_processing): Support v8plusb. * elf64-sparc.c (sparc64_elf_merge_private_bfd_data, sparc64_elf_object_p): Support v9b. * archures.c: Declare v8plusb and v9b machines. * bfd-in2.h: Ditto. * cpu-sparc.c: Ditto. include/opcode/ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. Note that '3' is used for siam operand. opcodes/ * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. (compute_arch_mask): Add v8plusb and v9b machines. (print_insn_sparc): siam mode decoding, accept ASRs up to 25. * opcodes/sparc-opc.c: Support for Cheetah instruction set. (prefetch_table): Add #invalidate. |
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a29k.h | ||
alpha.h | ||
arc.h | ||
arm.h | ||
avr.h | ||
cgen.h | ||
ChangeLog | ||
convex.h | ||
cris.h | ||
d10v.h | ||
d30v.h | ||
h8300.h | ||
hppa.h | ||
i370.h | ||
i386.h | ||
i860.h | ||
i960.h | ||
ia64.h | ||
m68hc11.h | ||
m68k.h | ||
m88k.h | ||
mips.h | ||
mn10200.h | ||
mn10300.h | ||
np1.h | ||
ns32k.h | ||
pj.h | ||
pn.h | ||
ppc.h | ||
pyr.h | ||
sparc.h | ||
tahoe.h | ||
tic30.h | ||
tic54x.h | ||
tic80.h | ||
v850.h | ||
vax.h |