Add support for the MIPS32
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Nick Clifton
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4f46dbc790
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@ -1,3 +1,7 @@
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2000-09-13 Anders Norlander <anorland@acc.umu.se>
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* mips.h (E_MIPS_MACH_4K): New define.
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2000-09-05 Alan Modra <alan@linuxcare.com.au>
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* hppa.h: Fix a comment.
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@ -153,7 +153,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
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#define E_MIPS_MACH_4100 0x00830000
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#define E_MIPS_MACH_4650 0x00850000
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#define E_MIPS_MACH_4111 0x00880000
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/* -mips32 code.
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It is easier to treat MIPS32 as a machine rather than an architecture. */
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#define E_MIPS_MACH_MIPS32 0x00890000
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/* Processor specific section indices. These sections do not actually
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exist. Symbols with a st_shndx field corresponding to one of these
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@ -1,3 +1,20 @@
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2000-09-13 Anders Norlander <anorland@acc.umu.se>
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* mips.h: Use defines instead of hard-coded processor numbers.
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(CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
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CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
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CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
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CPU_4KC, CPU_4KM, CPU_4KP): Define..
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(OPCODE_IS_MEMBER): Use new defines.
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(OP_MASK_SEL, OP_SH_SEL): Define.
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(OP_MASK_CODE20, OP_SH_CODE20): Define.
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Add 'P' to used characters.
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Use 'H' for coprocessor select field.
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Use 'm' for 20 bit breakpoint code.
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Document new arg characters and add to used characters.
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(INSN_MIPS32): New define for MIPS32 extensions.
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(OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
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2000-09-05 Alan Modra <alan@linuxcare.com.au>
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* hppa.h: Mention cz completer.
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@ -126,6 +126,10 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_MASK_MMISUB 0x1f
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
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#define OP_SH_PERFREG 1
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#define OP_SH_SEL 0 /* Coprocessor select field */
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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#define OP_SH_CODE20 6 /* 20 bit breakpoint code */
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#define OP_MASK_CODE20 0xfffff
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/* This structure holds information for a particular instruction. */
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@ -172,6 +176,7 @@ struct mips_opcode
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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"j" 16 bit signed immediate (OP_*_DELTA)
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"k" 5 bit cache opcode in target register position (OP_*_CACHE)
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"m" 20 bit breakpoint code (OP_*_CODE20)
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"o" 16 bit signed offset (OP_*_DELTA)
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"p" 16 bit PC relative branch target address (OP_*_DELTA)
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"q" 10 bit extra breakpoint code (OP_*_CODE2)
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@ -200,6 +205,7 @@ struct mips_opcode
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"E" 5 bit target register (OP_*_RT)
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"G" 5 bit destination register (OP_*_RD)
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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"H" 3 bit sel field (OP_*_SEL)
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Macro instructions:
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"A" General 32 bit expression
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@ -215,8 +221,8 @@ struct mips_opcode
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Characters used so far, for quick reference when adding more:
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"<>(),"
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"ABCDEFGILMNSTRVW"
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"abcdfhijklopqrstuvwxz"
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"ABCDEFGHILMNPSTRVW"
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"abcdfhijklmopqrstuvwxz"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -319,10 +325,32 @@ struct mips_opcode
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#define INSN_4100 0x00000040
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/* Toshiba R3900 instruction. */
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#define INSN_3900 0x00000080
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/* MIPS32 instruction (4Kc, 4Km, 4Kp). */
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#define INSN_MIPS32 0x00000100
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/* 32-bit code running on a ISA3+ CPU. */
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#define INSN_GP32 0x00001000
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/* CPU defines, use instead of hardcoding processor number. Keep this
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in sync with bfd/archures.c in order for machine selection to work. */
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#define CPU_R2000 2000
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#define CPU_R3000 3000
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#define CPU_R3900 3900
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#define CPU_R4000 4000
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#define CPU_R4010 4010
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#define CPU_VR4100 4100
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#define CPU_R4111 4111
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#define CPU_R4300 4300
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#define CPU_R4400 4400
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#define CPU_R4600 4600
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#define CPU_R4650 4650
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#define CPU_R5000 5000
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#define CPU_R6000 6000
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#define CPU_R8000 8000
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#define CPU_R10000 10000
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#define CPU_MIPS16 16
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#define CPU_MIPS32 32
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#define CPU_4K CPU_MIPS32
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/* Test for membership in an ISA including chip specific ISAs.
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INSN is pointer to an element of the opcode table; ISA is the
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specified ISA to test against; and CPU is the CPU specific ISA
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@ -331,20 +359,16 @@ struct mips_opcode
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a machine with 64-bit registers; see the documentation under -mgp32
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in the MIPS gas docs. */
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#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \
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((((insn)->membership & INSN_ISA) != 0 \
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&& ((insn)->membership & INSN_ISA) <= isa \
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&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
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|| (cpu == 4650 \
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&& ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == 4010 \
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&& ((insn)->membership & INSN_4010) != 0) \
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|| ((cpu == 4100 \
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|| cpu == 4111 \
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) \
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&& ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == 3900 \
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&& ((insn)->membership & INSN_3900) != 0))
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#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
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((((insn)->membership & INSN_ISA) != 0 \
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&& ((insn)->membership & INSN_ISA) <= (unsigned) isa \
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&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
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|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
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&& ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
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/* This is a list of macro expanded instructions.
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*
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