Support for tic54x target.
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Tim Wall
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2000-05-04 Timothy Wall <twall@cygnus.com>
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* tic54x.h: New.
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2000-05-03 J.T. Conklin <jtc@redback.com>
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* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
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167
include/opcode/tic54x.h
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167
include/opcode/tic54x.h
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/* tic54x.h -- Header file for TI TMS320C54X opcode table
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Copyright 1999, 2000 Free Software Foundation, Inc.
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Written by Timothy Wall (twall@cygnus.com)
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#ifndef _TIC54X_H_
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#define _TIC54X_H_
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typedef struct _symbol
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{
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const char *name;
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unsigned short value;
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} symbol;
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enum optype {
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OPT = 0x8000,
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OP_None = 0x0,
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OP_Xmem, /* AR3 or AR4, indirect */
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OP_Ymem, /* AR3 or AR4, indirect */
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OP_pmad, /* PROG mem, direct */
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OP_dmad, /* DATA mem, direct */
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OP_Smem,
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OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
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OP_MMR,
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OP_PA,
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OP_Sind,
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OP_xpmad,
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OP_xpmad_ms7,
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OP_MMRX,
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OP_MMRY,
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OP_SRC1, /* src accumulator in bit 8 */
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OP_SRC, /* src accumulator in bit 9 */
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OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
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OP_DST, /* dst accumulator in bit 8 */
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OP_ARX, /* arX in bits 0-3 */
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OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
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OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */
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OP_B, /* ACC B only */
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OP_A, /* ACC A only */
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OP_lk, /* 16-bit immediate, '#' optional */
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OP_TS,
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OP_k8, /* -128 <= k <= 128 */
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OP_16, /* literal "16" */
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OP_BITC, /* 0 to 16 */
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OP_CC, /* condition code */
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OP_CC2, /* 4-bit condition code */
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OP_CC3, /* 2-bit condition code */
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OP_123, /* 1, 2, or 3 */
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OP_031, /* 0-31, numeric */
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OP_k5, /* 0 to 31 */
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OP_k8u, /* 0 to 255 */
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OP_ASM, /* "ASM" */
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OP_T, /* "T" */
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OP_DP, /* "DP" */
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OP_ARP, /* "ARP" */
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OP_k3, /* 0-7 */
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OP_lku, /* 0 to 65535 */
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OP_N, /* 0/1 or ST0/ST1 */
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OP_SBIT, /* status bit or 0-15 */
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OP_12, /* one or two */
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OP_k9, /* 9 bits of data page (DP) address */
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OP_TRN, /* "TRN" */
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};
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typedef struct _template
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{
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/* The opcode mnemonic */
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const char *name;
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unsigned int words; /* insn size in words */
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int minops, maxops; /* min/max operand count */
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/* The significant bits in the opcode. Other bits are zero.
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Instructions with more than 16 bits of opcode store the rest in the upper
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16 bits.
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*/
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unsigned short opcode;
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#define INDIRECT(OP) ((OP)&0x80)
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#define MOD(OP) (((OP)>>3)&0xF)
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#define ARF(OP) ((OP)&0x7)
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#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12)
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#define SRC(OP) ((OP)&0x200)
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#define DST(OP) ((OP)&0x100)
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#define SRC1(OP) ((OP)&0x100)
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#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
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#define SHFT(OP) ((OP)&0xF)
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#define ARX(OP) ((OP)&0x7)
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#define XMEM(OP) (((OP)&0x00F0)>>4)
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#define YMEM(OP) ((OP)&0x000F)
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#define XMOD(C) (((C)&0xC)>>2)
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#define XARX(C) (((C)&0x3)+2)
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#define CC3(OP) (((OP)>>8)&0x3)
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#define SBIT(OP) ((OP)&0xF)
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#define MMR(OP) ((OP)&0x7F)
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#define MMRX(OP) ((((OP)>>4)&0xF)+16)
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#define MMRY(OP) (((OP)&0xF)+16)
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#define OPTYPE(X) ((X)&~OPT)
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/* Ones in this mask indicate which bits must match the opcode field.
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Zeroes indicate don't care bits (operands and/or opcode options) */
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unsigned short mask;
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/* An array of operand codes (at most 4 operands) */
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#define MAX_OPERANDS 4
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enum optype operand_types[MAX_OPERANDS];
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/* Special purpose flags (e.g. branch type, parallel, delay, etc)
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*/
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unsigned short flags;
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#define B_NEXT 0 /* normal execution, next insn is next address */
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#define B_BRANCH 1 /* next insn is in opcode */
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#define B_RET 2 /* next insn is on stack */
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#define B_BACC 3 /* next insn is in acc */
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#define B_REPEAT 4 /* next insn repeats */
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#define FL_BMASK 0x07
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#define FL_DELAY 0x10 /* instruction uses delay slots */
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#define FL_EXT 0x20 /* instruction takes two words */
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#define FL_FAR 0x40 /* far mode addressing */
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#define FL_LP 0x80 /* LP-only instruction */
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#define FL_NR 0x100 /* no repeat allowed */
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#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */
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unsigned short opcode2, mask2; /* some insns have an extended opcode */
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} template;
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typedef struct _partemplate {
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char *name;
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char *parname;
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unsigned int words; /* length in words */
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int minops, maxops; /* min/max operand count for 2nd part of insn */
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unsigned short opcode;
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unsigned short mask;
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enum optype operand_types[MAX_OPERANDS];
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enum optype paroperand_types[MAX_OPERANDS];
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} partemplate;
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extern const template tic54x_unknown_opcode;
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extern const template tic54x_optab[];
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extern const partemplate tic54x_paroptab[];
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extern const symbol mmregs[], regs[];
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extern const symbol condition_codes[], cc2_codes[], status_bits[];
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extern const symbol cc3_codes[];
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extern const char *misc_symbols[];
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#endif /* TIC54X_H */
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