c1ab3396dc
2004-11-25 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (optimize_imm): Adjust immediates to only those permissible for the selected instruction suffix. (process_suffix): For DefaultSize instructions, suppressing the guessing of a 'q' suffix if the instruction doesn't support it is pointless, because only an 'l' suffix can be guessed in this place. gas/testsuite/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-inval.[sl]: Remove sahf/lahf. include/opcode/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves to/from test registers are illegal in 64-bit mode. Add missing NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix (previously one had to explicitly encode a rex64 prefix). Re-enable lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings support it there. Add cmpxchg16b as per Intel's 64-bit documentation. |
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a29k.h | ||
alpha.h | ||
arc.h | ||
arm.h | ||
avr.h | ||
cgen.h | ||
ChangeLog | ||
ChangeLog-9103 | ||
convex.h | ||
cris.h | ||
crx.h | ||
d10v.h | ||
d30v.h | ||
dlx.h | ||
h8300.h | ||
hppa.h | ||
i370.h | ||
i386.h | ||
i860.h | ||
i960.h | ||
ia64.h | ||
m68hc11.h | ||
m68k.h | ||
m88k.h | ||
maxq.h | ||
mips.h | ||
mmix.h | ||
mn10200.h | ||
mn10300.h | ||
msp430.h | ||
np1.h | ||
ns32k.h | ||
or32.h | ||
pdp11.h | ||
pj.h | ||
pn.h | ||
ppc.h | ||
pyr.h | ||
s390.h | ||
sparc.h | ||
tahoe.h | ||
tic4x.h | ||
tic30.h | ||
tic54x.h | ||
tic80.h | ||
v850.h | ||
vax.h |