* cris.h (enum cris_insn_version_usage): Tweak formatting and
comments. Remove member cris_ver_sim. Add members cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. (struct cris_support_reg, struct cris_cond15): New types. (cris_conds15): Declare. (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. (NOP_Z_BITS): Define in terms of NOP_OPCODE. (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and SIZE_FIELD_UNSIGNED.
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34b30773b1
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@ -1,3 +1,18 @@
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2004-11-04 Hans-Peter Nilsson <hp@axis.com>
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* cris.h (enum cris_insn_version_usage): Tweak formatting and
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comments. Remove member cris_ver_sim. Add members
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cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
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cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
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(struct cris_support_reg, struct cris_cond15): New types.
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(cris_conds15): Declare.
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(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
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(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
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(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
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(NOP_Z_BITS): Define in terms of NOP_OPCODE.
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(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
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SIZE_FIELD_UNSIGNED.
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2004-11-04 Jan Beulich <jbeulich@novell.com>
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* i386.h (sldx_Suf): Remove.
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@ -1,5 +1,5 @@
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/* cris.h -- Header file for CRIS opcode and register tables.
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Copyright (C) 2000, 2001 Free Software Foundation, Inc.
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Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
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Contributed by Axis Communications AB, Lund, Sweden.
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Originally written for GAS 1.38.1 by Mikael Asker.
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Updated, BFDized and GNUified by Hans-Peter Nilsson.
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@ -38,15 +38,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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immediate operands. */
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enum cris_insn_version_usage
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{
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/* Any version. */
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/* Any version. */
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cris_ver_version_all=0,
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/* Indeterminate (intended for disassembly only, or obsolete). */
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cris_ver_warning,
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/* Simulator only (reserved). */
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cris_ver_sim,
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/* Only for v0..3 (Etrax 1..4). */
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cris_ver_v0_3,
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@ -59,10 +56,28 @@ enum cris_insn_version_usage
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/* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
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cris_ver_v8p,
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/* Only for v10 or higher (ETRAX 100 LX).
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Of course some or all these of may change to cris_ver_v10p if/when
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/* Only for v0..10. FIXME: Not sure what to do with this. */
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cris_ver_sim_v0_10,
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/* Only for v0..10. */
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cris_ver_v0_10,
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/* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
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cris_ver_v3_10,
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/* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
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cris_ver_v8_10,
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/* Only for v10 (ETRAX 100 LX) and same series. */
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cris_ver_v10,
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/* Only for v10 (ETRAX 100 LX) and same series. */
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cris_ver_v10p,
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/* Only for v32 or higher (codename GUINNESS).
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Of course some or all these of may change to cris_ver_v32p if/when
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there's a new revision. */
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cris_ver_v10p
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cris_ver_v32p
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};
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@ -85,6 +100,25 @@ struct cris_spec_reg
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};
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extern const struct cris_spec_reg cris_spec_regs[];
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/* Support registers (kind of special too, but not named as such). */
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struct cris_support_reg
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{
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const char *const name;
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unsigned int number;
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};
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extern const struct cris_support_reg cris_support_regs[];
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struct cris_cond15
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{
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/* The name of the condition. */
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const char *const name;
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/* What CPU version this condition name applies to. */
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enum cris_insn_version_usage applicable_version;
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};
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extern const struct cris_cond15 cris_conds15[];
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/* Opcode-dependent constants. */
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#define AUTOINCR_BIT (0x04)
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@ -163,9 +197,28 @@ extern const char *const cris_cc_strings[];
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#define ADD_PC_INCR_OPCODE \
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(0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)
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#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
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/* BA DWORD (V32). */
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#define BA_DWORD_OPCODE (0x0EBF)
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/* Nop. */
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#define NOP_OPCODE (0x050F)
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#define NOP_Z_BITS (0xFAF0)
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#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
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#define NOP_OPCODE_V32 (0x05B0)
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#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
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/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
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registers or flags. Unfortunately shuts off interrupts for one cycle
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for < v32, but there doesn't seem to be any alternative without that
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effect. */
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#define NOP_OPCODE_COMMON (0x630)
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#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
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/* LAPC.D */
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#define LAPC_DWORD_OPCODE (0x0D7F)
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#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
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/* Structure of an opcode table entry. */
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enum cris_imm_oprnd_size_type
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@ -179,7 +232,13 @@ enum cris_imm_oprnd_size_type
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/* Indicated by size of special register. */
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SIZE_SPEC_REG,
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/* Indicated by size field. */
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/* Indicated by size field, signed. */
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SIZE_FIELD_SIGNED,
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/* Indicated by size field, unsigned. */
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SIZE_FIELD_UNSIGNED,
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/* Indicated by size field, no sign implied. */
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SIZE_FIELD
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};
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