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253 Commits

Author SHA1 Message Date
Nick Clifton
388732e7f6 Add MIPS32 as a seperate MIPS architecture 2000-12-01 21:35:38 +00:00
Nick Clifton
2a91907cc0 Improve MIPS32 support 2000-12-01 20:05:32 +00:00
Jakub Jelinek
b3c74e6dd0 gas/ 
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
	instructions to loose any special insn->architecture mask.

	* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
	(sparc_md_end, sparc_arch_types, sparc_arch,
	sparc_elf_final_processing): Handle v8plusb and v9b architectures.
	(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
	request v9b architecture if they are used).

bfd/
	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
	elf32_sparc_object_p, elf32_sparc_final_write_processing):
	Support v8plusb.
	* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
	sparc64_elf_object_p): Support v9b.
	* archures.c: Declare v8plusb and v9b machines.
	* bfd-in2.h: Ditto.
	* cpu-sparc.c: Ditto.

include/opcode/
	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
	Note that '3' is used for siam operand.

opcodes/
	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
	(compute_arch_mask): Add v8plusb and v9b machines.
	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
	* opcodes/sparc-opc.c: Support for Cheetah instruction set.
	(prefetch_table): Add #invalidate.
 2000-10-20 10:38:47 +00:00
Jim Wilson
eb69b80812 Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again. 
gas/ChangeLog
	* config/tc-ia64.c (dv_sem): Add "stop".
	(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
	(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
	(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
	match above.
	(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
	* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
	* gas/ia64/dv-waw-err.s: Likewise.
	* gas/ia64/dv-imply.d: Regenerate.
	* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
	gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
	gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
	* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
	* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
	* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
	(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
	* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
	* ia64-asmtab.c: Regnerate.
 2000-09-22 19:43:49 +00:00
Nick Clifton
67b0ce5ff0 Add support for the MIPS32 2000-09-14 01:47:37 +00:00
Alan Modra
5be3981a24 doco addition. 2000-09-05 05:22:24 +00:00
Jim Wilson
6afcd43da0 Fix 3 DV bugs, and a few minor cleanups. 
gas/
	* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
	postincrement modified registers.  Handle IA64_OPND_R3_2 addl
	source registers.
	(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
	* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
	* gas/ia64/dv-raw-err.l: Likewise.
	* gas/ia64/dv-waw-err.l: Update sed pattern.
	* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
	* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
	* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
	break, mov-immediate, nop.
	* ia64-opc-f.c: Delete fpsub instructions.
	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
	address operand.  Rewrite using macros to avoid long lines.
	* ia64-opc.h (POSTINC): Define.
	* ia64-asmtab.c: Regenerate.
 2000-08-16 23:20:14 +00:00
H.J. Lu
e3c9eeaf79 2000-08-15 H.J. Lu <hjl@gnu.org> 
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
	IgnoreSize change.
 2000-08-16 17:29:23 +00:00
Jason Eckhardt
ff3d99fb37 gas: 
2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
	(i860_fix_info): New enum.
	(MD_APPLY_FIX3): Define.
	(WORKING_DOT_WORD): Define.
	(TC_HANDLES_FX_DONE): Define.
	(DIFF_EXPR_OK): Define.
	(LISTING_HEADER): Define.
	(TARGET_FORMAT): Select target format based on endian flag.
	(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
	(target_big_endian): Add external declaration.

	* config/tc-i860.c: All existing code reworked completely. Other
	new code shown below.
	(SYNTAX_SVR4): Define.
	(target_warn_expand): New variable.
	(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
	(md_longopts): Declare and define with new options (-EL, -EB,
	and -mwarn-expand).
	(md_show_usage): New function.
	(md_operand): New function.
	(obtain_reloc_for_imm16): New function.
	(md_apply_fix3): New function.
	(tc_gen_reloc): New function.

include:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* opcode/i860.h: Small formatting adjustments.

opcode:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* i860-dis.c (print_br_address): Change third argument from int
	to long.

bfd:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>
	* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
 2000-08-09 03:33:41 +00:00
Denis Chertykov
553d0fe671 * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. 
Move related opcodes closer to each other.
	Minor changes in comments, list undefined opcodes.
 2000-08-06 14:09:14 +00:00
Jason Eckhardt
4f34f5c30e 2000-07-22 Jason Eckhardt <jle@cygnus.com> 
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
	to use sbroff ('r') instead of split16 ('s').
	(J, K, L, M): New operand types for 16-bit aligned fields.
	(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
	use I, J, K, L, M instead of just I.
	(T, U): New operand types for split 16-bit aligned fields.
	(st.x): Changed these opcodes to use S, T, U instead of just S.
	(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
	exist on the i860.
	(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
	(pfeq.ss, pfeq.dd): New opcodes.
	(st.s): Fixed incorrect mask bits.
	(fmlow): Fixed incorrect mask bits.
	(fzchkl, pfzchkl): Fixed incorrect mask bits.
	(faddz, pfaddz): Fixed incorrect mask bits.
	(form, pform): Fixed incorrect mask bits.
	(pfld.l): Fixed incorrect mask bits.
	(fst.q): Fixed incorrect mask bits.
	(all floating point opcodes): Fixed incorrect mask bits for
	handling of dual bit.

	* include/elf/i860.h: New file.
	(elf_i860_reloc_type): Defined ELF32 i860 relocations.

	* bfd/cpu-i860.c: Added comments.

	* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
	bfd_elf32_i860_little_vec.
	(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
	(ELF_MAXPAGESIZE): Changed to 4096.

	* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
	new target.
	(bfd_target_vector): Added bfd_elf32_i860_little_vec.

	* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
	config for little endian elf32 i860.
	(targ_defvec): Define for the new config above
	as "bfd_elf32_i860_little_vec".
	(targ_selvecs): Define for the new config above
	as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"

	* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
	of new target vec.

	* bfd/configure: Regenerated.

	* opcodes/i860-dis.c: New file.
	(print_insn_i860): New function.
	(print_br_address): New function.
	(sign_extend): New function.
	(BITWISE_OP): New macro.
	(I860_REG_PREFIX): New macro.
	(grnames, frnames, crnames): New structures.

	* opcodes/disassemble.c (ARCH_i860): Define.
	(disassembler): Add check for bfd_arch_i860 to set disassemble
	function to print_insn_i860.

	* include/dis-asm.h (print_insn_i860): Add prototype.

	* opcodes/Makefile.in (CFILES): Added i860-dis.c.
	(ALL_MACHINES): Added i860-dis.lo.
	(i860-dis.lo): New dependences.

	* opcodes/configure.in: New bits for bfd_i860_arch.

	* opcodes/configure: Regenerated.
 2000-07-28 21:10:20 +00:00
Dave Brolley
b58a443464 2000-07-26 Dave Brolley <brolley@redhat.com> 
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
 2000-07-26 22:44:42 +00:00
Hans-Peter Nilsson
43d25e8350 cris.h: New file. 2000-07-20 15:39:41 +00:00
Nick Clifton
650536b382 Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR port. 2000-06-27 01:45:30 +00:00
Nick Clifton
8929e0a70c Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support 
for m68hc11 and m68hc12 processors.
 2000-06-19 01:22:42 +00:00
Denis Chertykov
b6c40e83e9 * avr.h: clr,lsl,rol, ... moved after add,adc, ... 2000-06-09 18:02:05 +00:00
Denis Chertykov
987dd6a80f * avr.h: New file with AVR opcodes. 2000-06-07 17:48:35 +00:00
Donald Lindsay
83d485ca0c Define the ALONE flag bit, for use in the opcode table. 2000-05-25 22:23:45 +00:00
Alan Modra
6458314f0d Allow d suffix on iret 2000-05-23 00:36:39 +00:00
Alan Modra
8c1c1f1a43 Fix fild. 2000-05-17 00:47:51 +00:00
Frank Ch. Eigler
0bf4b1e8ab * cgen/opcodes fix 
* approved by nickc

[opcodes/ChangeLog]
2000-05-16  Frank Ch. Eigler  <fche@redhat.com>

	* fr30-desc.h: Partially regenerated to account for changed
	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
	* m32r-desc.h: Ditto.

[include/opcode/ChangeLog]
2000-05-16  Frank Ch. Eigler  <fche@redhat.com>

	* cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32.  Check that
	it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
	(CGEN_MAX_IFMT_OPERANDS): Increase to 16.  Check that it exceeds
	CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
 2000-05-16 19:28:07 +00:00
Alan Modra
e6342d0038 Fix cpu_flags for sys{enter,exit} fx{save,restore} 2000-05-13 14:01:54 +00:00
Alan Modra
9484bf7072 `.arch cpu_type' pseudo for x86. 2000-05-13 09:26:23 +00:00
Tim Wall
75546193ec Support for tic54x target. 2000-05-06 17:14:34 +00:00
J.T. Conklin
cf3eb87bef * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. 
(PPC_OPERAND_VR): New operand flag for vector registers.
 2000-05-03 22:19:45 +00:00
Jeff Law
f8c723b8f8 * h8300.h (EOP): Add missing initializer. 2000-05-01 16:55:50 +00:00
Jeff Law
2d6fec0fc1 * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode 
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
        New operand types l,y,&,fe,fE,fx added to support above forms.
        (pa_opcodes): Replaced usage of 'x' as source/target for
        floating point double-word loads/stores with 'fx'.

Fr
 2000-04-21 21:04:04 +00:00
Jim Wilson
4501dfbc42 IA-64 ELF support. 2000-04-21 20:22:23 +00:00
Nick Clifton
1b3755ec07 Fix value of SHORT_A1. 
Move SHORT_AR to end of list of short instructions.
 2000-03-27 20:17:02 +00:00
Alan Modra
114d3d3070 Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warn 
messages with capital.  Don't malign Unixware, malign SysV386 instead.
 2000-03-26 14:13:01 +00:00
Nick Clifton
92976eab7d Apply patch for 100679 2000-03-02 23:01:40 +00:00
Alan Modra
e53d3a5d95 Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all 
the errors exposed by this addition.  These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
 2000-02-25 11:41:12 +00:00
Nick Clifton
7620791bd9 Rename 'flags' to 'signed_overflow_ok_p' 2000-02-24 23:57:23 +00:00
Andrew Haley
4d0ce66d1f 2000-02-24 Andrew Haley <aph@cygnus.com> 
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
        (CGEN_CPU_TABLE): flags: new field.
        Add prototypes for new functions.
 2000-02-24 21:56:53 +00:00
Alan Modra
759e2a8845 Forgot Changelog for last i386.h change. 2000-02-24 12:41:54 +00:00
Alan Modra
df256a94d6 Correct intel_syntax fsub* and fdiv* handling. Oh, how I'd like to be rid 
of UNIXWARE_COMPAT.
 2000-02-24 12:40:45 +00:00
Alan Modra
58dabf5040 Add IBM 370 support. 2000-02-23 13:52:22 +00:00
Chandra Chavva
9dfc83d797 * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation cannot 
be combined in parallel with ADD/SUBppp.
 2000-02-22 20:52:14 +00:00
Andrew Haley
196bbedaa7 g2000-02-22 Andrew Haley <aph@cygnus.com> 
* mips.h: (OPCODE_IS_MEMBER): Add comment.
 2000-02-22 19:01:25 +00:00
Andrew Haley
b7c65de2b8 ChangeLog change only. 2000-02-22 16:59:39 +00:00
Andrew Haley
95d64ccd4e 1999-12-30 Andrew Haley <aph@cygnus.com> 
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
 2000-02-22 14:39:20 +00:00
Alan Modra
1a80e0b5d2 Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and 
call tests + tweak intel mode far call and jmp.
 2000-01-15 12:06:03 +00:00
Alan Modra
a3717e6ce0 x86 indirect jump/call syntax fixes. Disassembly fix for lcall. 1999-12-27 16:10:31 +00:00
Jeff Law
488e1589f7 * mn10300.h: Add new operand types. Add new instruction formats. 1999-12-01 10:05:24 +00:00
Jeff Law
cef484e503 * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" 
instruction.
 1999-11-25 03:28:22 +00:00
Gavin Koch
10ab31ca59 For include/opcode: 
* mips.h (INSN_ISA5): New.

For opcodes:

	* mips-opc.c (I5): New.
	(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
	madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
	pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
 1999-11-18 19:53:48 +00:00
Gavin Koch
7372e38bfd For include/opcode: 
* mips.h (OPCODE_IS_MEMBER): New.

For gas:

	* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
	(mips_ip): Use OPCODE_IS_MEMBER.

For opcodes:

	* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
 1999-11-01 19:29:55 +00:00
Nick Clifton
f1a1e10e18 Define SHORT_AR (fix for CR: 101340) 1999-10-29 09:49:04 +00:00
Michael Meissner
da516da191 Add md expression support; Cleanup alpha warnings 1999-10-18 22:29:14 +00:00
Jeff Law
756b080175 * hppa.h (pa_opcodes): Add load and store cache control to 
instructions.  Add ordered access load and store.

        * hppa.h (pa_opcode): Add new entries for addb and addib.

        * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.

        * hppa.h (pa_opcodes):  Add entries for cmpb and cmpib.
 1999-10-10 07:55:25 +00:00
Diego Novillo
e1286a3825 Added seven new instructions ld, ld2w, sac, sachi, slae, st and 
st2w for d10v. Created new testsuite for d10v to verify new
instructions.
 1999-10-07 06:17:04 +00:00
Jeff Law
bf27795cff Add missing initializer lost in last change. 1999-09-23 15:46:33 +00:00
Jeff Law
1a6447612f * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" 
and "be" using completer prefixes.
 1999-09-23 14:29:10 +00:00
Jeff Law
3118b34c80 * hppa.h (pa_opcodes): Add initializers to silence compiler. 1999-09-23 13:14:33 +00:00
Jeff Law
f026123d83 * hppa.h: Update comments about character usage. 1999-09-23 13:10:07 +00:00
Jeff Law
27421fd084 * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning 
up the new fstw & bve instructions.
 1999-09-20 09:57:19 +00:00
Jeff Law
9eff6c959f * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store 
instructions.
 1999-09-19 20:05:00 +00:00
Jeff Law
c7b64ad4f0 * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. 1999-09-19 19:43:06 +00:00
Jeff Law
675e0509d0 * hppa.h (pa_opcodes): Add long offset double word load/store 
instructions.
 1999-09-19 19:19:50 +00:00
Jeff Law
45faedf39e * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and 
stores.
 1999-09-19 18:54:23 +00:00
Jeff Law
02a209f9b5 * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. 1999-09-19 18:44:13 +00:00
Jeff Law
4832d84f3d * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. 1999-09-19 18:10:28 +00:00
Jeff Law
af5442f198 * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. 1999-09-19 17:39:17 +00:00
Jeff Law
24e0770908 * hppa.h (pa_opcodes): Add new syntax "be" instructions. 1999-09-19 17:16:08 +00:00
Jeff Law
84e7327d75 * hppa.h (pa_opcodes): Note use of 'M' and 'L'. 1999-09-19 17:12:55 +00:00
Jeff Law
1ddec1532b * hppa.h (pa_opcodes): Add support for "b,l". 1999-09-19 16:55:09 +00:00
Jeff Law
4969046449 * hppa.h (pa_opcodes): Add support for "b,gate". 1999-09-19 16:41:51 +00:00
Jeff Law
5566981684 * hppa.h (pa_opcodes): Use 'fX' for first register operand 
in xmpyu.
 1999-09-18 18:08:34 +00:00
Jeff Law
67faa9adc2 * hppa.h (pa_opcodes): Fix mask for probe and probei. 1999-09-18 17:49:43 +00:00
Jeff Law
578f46be35 * hppa.h (pa_opcodes): Fix mask for depwi. 1999-09-18 17:43:47 +00:00
Jeff Law
6338a22379 * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as 
an explicit output argument.
 1999-09-07 19:46:47 +00:00
Jeff Law
6935f65eff * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. 
Add a few PA2.0 loads and store variants.
 1999-09-06 10:42:11 +00:00
Ian Lance Taylor
12ed226cc7 1999-09-04 Steve Chamberlain <sac@pobox.com> 
* pj.h: New file.
 1999-09-04 17:16:21 +00:00
Alan Modra
a4972584a4 Allow spaces in i386 FP reg names, eg. %st ( 1 ). 1999-08-29 23:44:27 +00:00
Jeff Law
9b2c866771 * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args 
by 'f'.
 1999-08-29 07:51:43 +00:00
Jeff Law
b7fdf3c074 * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. 
Add supporting args.
 1999-08-28 10:58:26 +00:00
Jeff Law
ab3ce6303a * hppa.h: Document new completers and args. 
* hppa.h (pa_opcodes):  Add 64 bit patterns and pa2.0 syntax for uxor,
        uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe.  Add pa2.0
        extensions for ssm, rsm, pdtlb, pitlb.  Add performance instructions
        pmenb and pmdis.
 1999-08-28 10:16:15 +00:00
Jeff Law
b4063b31d4 Fix minor bug in last change. 1999-08-28 09:28:31 +00:00
Jeff Law
a7192fe0ab * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, 
hshr, hsub, mixh, mixw, permh.
 1999-08-28 08:46:57 +00:00
Jeff Law
ad9cdcce7b * hppa.h (pa_opcodes): Change completers in instructions to 
use 'c' prefix.
 1999-08-28 08:16:55 +00:00
Jeff Law
5193c502b0 * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, 
hshladd, hshradd, shrpd, and shrpw instructions.  Update arg comments.
 1999-08-28 06:41:11 +00:00
Jeff Law
39484d8592 * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, 
fnegabs to use 'I' instead of 'F'.
 1999-08-28 06:27:12 +00:00
Alan Modra
e5af6ca113 Add AMD athlon support to x86 assembler and disassembler. 1999-08-21 12:40:35 +00:00
Doug Evans
d0c72719e5 * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. 1999-08-19 05:45:30 +00:00
Jeff Law
85038a8a7f * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, 
and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
 1999-08-06 16:03:53 +00:00
Jeff Law
55c98dbaae * hppa.h: Document 64 bit condition completers. 1999-08-06 15:49:29 +00:00
Jeff Law
978c8e91e3 * hppa.h (pa_opcodes): Change condition args to use '?' prefix. 1999-08-05 22:58:08 +00:00
Alan Modra
0274eb115d Support for gcc to generate 16-bit i386 code. (.code16gcc) 1999-08-04 10:07:41 +00:00
Jeff Law
83849fdd14 * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". 
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
 1999-07-28 10:31:15 +00:00
Jeff Law
733df03348 * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, 
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
 1999-07-28 08:06:30 +00:00
Alan Modra
02309525c5 8 
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
 1999-07-13 07:41:47 +00:00
Alan Modra
bec8046d67 o 
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
 1999-07-13 07:41:46 +00:00
Jeff Law
ca7cd5dc64 * hppa.h (struct pa_opcode): Add new field "flags". 
(FLAGS_STRICT): Define.
 1999-06-30 23:20:56 +00:00
Jeff Law
386449a2f8 * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. 1999-06-25 03:29:45 +00:00
Jeff Law
233881c2a2 * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. 1999-06-25 03:23:12 +00:00
Alan Modra
30b962fd67 P 
include/opcode/i386.h: Allow bswapl, arplw, and other dodgy insns.
opcodes/i386-dis.c: Fix a comment
 1999-06-23 06:00:09 +00:00
Jeff Law
664151086b * hppa.h (pa_opcodes): Move integer arithmetic instructions after 
integer logical instructions.
 1999-05-28 14:26:52 +00:00
Ian Lance Taylor
6a26bbce7b 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> 
* m68k.h: Document new formats `E', `G', `H' and new places `N',
	`n', `o'.
	* m68k.h: Define mcf5206e, mcf5307, mcf.  Document new format `u'
	and new places `m', `M', `h'.
 1999-05-27 22:31:03 +00:00
Jeff Law
4b69b0a1f1 * hppa.h (pa_opcodes): Add several processor specific system 
instructions.
 1999-05-27 03:19:32 +00:00
Jeff Law
171cdecb9f * hppa.h (pa_opcodes): Add second entry for "comb", "comib", 
"addb", and "addib" to be used by the disassembler.
 1999-05-26 16:04:11 +00:00
Alan Modra
4b5775a3e9 P 
i386 PIII SIMD support, remove ReverseRegRegmem kludge
tidy a few things in i386 intel mode disassembly
 1999-05-13 06:00:27 +00:00
Richard Henderson
a594afbb42 * ppc.h (PPC_OPCODE_64_BRIDGE): New. 1999-05-08 23:28:34 +00:00
Richard Henderson
a3acbf4694 19990502 sourceware import 1999-05-03 07:29:06 +00:00