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Add web build, unify screen update and frame wait function, update CI

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OctoSpacc
2023-11-04 16:49:35 +01:00
parent ee19b03b1b
commit 2026d954ee
8 changed files with 251 additions and 122 deletions
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38
LibMultiSpacc/neslib/NROM256.cfg
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@@ -8,34 +8,28 @@ MEMORY {
ZP: start = $00, size = $100, type = rw, define = yes;
# INES Cartridge Header
HEADER: start = $0, size = $10, file = %O ,fill = yes;
HEADER: start = $0, size = $10, file = %O, fill = yes;
# 2 16K ROM Banks
# - startup
# - code
# - rodata
# - data (load)
PRG: start = $8000, size = $7f00, file = %O ,fill = yes, define = yes;
PRG: start = $8000, size = $7f00, file = %O, fill = yes, define = yes;
# DPCM Samples at end of the ROM
DMC: start = $ff00, size = $fa, file = %O, fill = yes;
# Hardware Vectors at end of the ROM
VECTORS: start = $fffa, size = $6, file = %O, fill = yes;
# 1 8K CHR Bank
CHR: start = $0000, size = $2000, file = %O, fill = yes;
# standard 2K SRAM (-zeropage)
# $0100 famitone, palette, cpu stack
# $0200 oam buffer
# $0300..$800 ca65 stack
RAM: start = $0300, size = $0500, define = yes;
# Use this definition instead if you going to use extra 8K RAM
@@ -43,20 +37,20 @@ MEMORY {
}
SEGMENTS {
HEADER: load = HEADER, type = ro;
STARTUP: load = PRG, type = ro, define = yes;
LOWCODE: load = PRG, type = ro, optional = yes;
ONCE: load = PRG, type = ro, optional = yes;
INIT: load = PRG, type = ro, define = yes, optional = yes;
CODE: load = PRG, type = ro, define = yes;
RODATA: load = PRG, type = ro, define = yes;
DATA: load = PRG, run = RAM, type = rw, define = yes;
VECTORS: load = VECTORS, type = rw;
SAMPLES: load = DMC, type = rw;
CHARS: load = CHR, type = rw;
BSS: load = RAM, type = bss, define = yes;
HEAP: load = RAM, type = bss, optional = yes;
ZEROPAGE: load = ZP, type = zp;
HEADER: load = HEADER, type = ro;
STARTUP: load = PRG, type = ro, define = yes;
LOWCODE: load = PRG, type = ro, optional = yes;
ONCE: load = PRG, type = ro, optional = yes;
INIT: load = PRG, type = ro, define = yes, optional = yes;
CODE: load = PRG, type = ro, define = yes;
RODATA: load = PRG, type = ro, define = yes;
DATA: load = PRG, run = RAM, type = rw, define = yes;
VECTORS: load = VECTORS, type = rw;
SAMPLES: load = DMC, type = rw;
CHARS: load = CHR, type = rw;
BSS: load = RAM, type = bss, define = yes;
HEAP: load = RAM, type = bss, optional = yes;
ZEROPAGE: load = ZP, type = zp;
}
FEATURES {