SMMU: Implement backing CPU page protect/unprotect
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7a9d1ad2f8
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c85d7ccd79
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@ -5,6 +5,8 @@
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#include <deque>
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#include <memory>
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#include <array>
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#include <atomic>
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#include "common/common_types.h"
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#include "common/virtual_buffer.h"
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@ -23,6 +25,7 @@ struct DeviceMemoryManagerAllocator;
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template <typename Traits>
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class DeviceMemoryManager {
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using DeviceInterface = typename Traits::DeviceInterface;
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using DeviceMethods = Traits::DeviceMethods;
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public:
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DeviceMemoryManager(const DeviceMemory& device_memory);
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@ -35,7 +38,7 @@ public:
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DAddr AllocatePinned(size_t size);
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void Free(DAddr start, size_t size);
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void Map(DAddr address, VAddr virtual_address, size_t size, size_t p_id);
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void Map(DAddr address, VAddr virtual_address, size_t size, size_t process_id);
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void Unmap(DAddr address, size_t size);
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// Write / Read
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@ -57,6 +60,8 @@ public:
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size_t RegisterProcess(Memory::Memory* memory);
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void UnregisterProcess(size_t id);
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void UpdatePagesCachedCount(DAddr addr, size_t size, s32 delta);
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private:
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static constexpr bool supports_pinning = Traits::supports_pinning;
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static constexpr size_t device_virtual_bits = Traits::device_virtual_bits;
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@ -90,8 +95,52 @@ private:
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Common::VirtualBuffer<u32> compressed_physical_ptr;
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Common::VirtualBuffer<u32> compressed_device_addr;
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// Process memory interfaces
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std::deque<size_t> id_pool;
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std::deque<Memory::Memory*> registered_processes;
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// Memory protection management
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static constexpr size_t guest_max_as_bits = 39;
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static constexpr size_t guest_as_size = 1ULL << guest_max_as_bits;
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static constexpr size_t guest_mask = guest_as_size - 1ULL;
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static constexpr size_t process_id_start_bit = guest_max_as_bits;
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std::pair<size_t, VAddr> ExtractCPUBacking(size_t page_index) {
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auto content = cpu_backing_address[page_index];
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const VAddr address = content & guest_mask;
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const size_t process_id = static_cast<size_t>(content >> process_id_start_bit);
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return std::make_pair(process_id, address);
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}
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void InsertCPUBacking(size_t page_index, VAddr address, size_t process_id) {
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cpu_backing_address[page_index] = address | (process_id << page_index);
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}
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Common::VirtualBuffer<VAddr> cpu_backing_address;
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static constexpr size_t subentries = 4;
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static constexpr size_t subentries_mask = subentries - 1;
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class CounterEntry final {
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public:
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CounterEntry() = default;
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std::atomic_uint16_t& Count(std::size_t page) {
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return values[page & subentries_mask];
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}
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const std::atomic_uint16_t& Count(std::size_t page) const {
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return values[page & subentries_mask];
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}
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private:
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std::array<std::atomic_uint16_t, subentries> values{};
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};
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static_assert(sizeof(CounterEntry) == subentries * sizeof(u16), "CounterEntry should be 8 bytes!");
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static constexpr size_t num_counter_entries = (1ULL << (device_virtual_bits - page_bits)) / subentries;
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using CachedPages = std::array<CounterEntry, num_counter_entries>;
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std::unique_ptr<CachedPages> cached_pages;
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};
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} // namespace Core
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@ -2,12 +2,15 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <atomic>
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#include <limits>
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#include <memory>
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#include <type_traits>
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#include "common/address_space.h"
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#include "common/address_space.inc"
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/div_ceil.h"
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#include "common/scope_exit.h"
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#include "core/device_memory.h"
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#include "core/device_memory_manager.h"
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@ -51,7 +54,11 @@ struct DeviceMemoryManagerAllocator {
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}
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DAddr AllocatePinned(size_t size) {
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return pin_allocator.Allocate(size);
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if constexpr (supports_pinning) {
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return pin_allocator.Allocate(size);
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} else {
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return DAddr{};
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}
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}
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void DoInRange(DAddr address, size_t size, auto pin_func, auto main_func) {
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@ -100,6 +107,7 @@ DeviceMemoryManager<Traits>::DeviceMemoryManager(const DeviceMemory& device_memo
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interface{nullptr}, compressed_physical_ptr(device_as_size >> Memory::YUZU_PAGEBITS),
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compressed_device_addr(1ULL << (physical_max_bits - Memory::YUZU_PAGEBITS)) {
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impl = std::make_unique<DeviceMemoryManagerAllocator<Traits>>();
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cached_pages = std::make_unique<CachedPages>();
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}
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template <typename Traits>
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@ -132,14 +140,14 @@ void DeviceMemoryManager<Traits>::Free(DAddr start, size_t size) {
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template <typename Traits>
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void DeviceMemoryManager<Traits>::Map(DAddr address, VAddr virtual_address, size_t size,
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size_t p_id) {
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Core::Memory::Memory* process_memory = registered_processes[p_id];
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size_t process_id) {
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Core::Memory::Memory* process_memory = registered_processes[process_id];
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size_t start_page_d = address >> Memory::YUZU_PAGEBITS;
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size_t num_pages = Common::AlignUp(size, Memory::YUZU_PAGESIZE) >> Memory::YUZU_PAGEBITS;
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std::atomic_thread_fence(std::memory_order_acquire);
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for (size_t i = 0; i < num_pages; i++) {
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auto* ptr = process_memory->GetPointer(
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Common::ProcessAddress(virtual_address + i * Memory::YUZU_PAGESIZE));
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const VAddr new_vaddress = virtual_address + i * Memory::YUZU_PAGESIZE;
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auto* ptr = process_memory->GetPointer(Common::ProcessAddress(new_vaddress));
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if (ptr == nullptr) [[unlikely]] {
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compressed_physical_ptr[start_page_d + i] = 0;
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continue;
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@ -147,6 +155,7 @@ void DeviceMemoryManager<Traits>::Map(DAddr address, VAddr virtual_address, size
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auto phys_addr = static_cast<u32>(GetRawPhysicalAddr(ptr) >> Memory::YUZU_PAGEBITS) + 1U;
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compressed_physical_ptr[start_page_d + i] = phys_addr;
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compressed_device_addr[phys_addr - 1U] = static_cast<u32>(start_page_d + i);
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InsertCPUBacking(start_page_d + i, new_vaddress, process_id);
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}
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std::atomic_thread_fence(std::memory_order_release);
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}
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@ -159,6 +168,7 @@ void DeviceMemoryManager<Traits>::Unmap(DAddr address, size_t size) {
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for (size_t i = 0; i < num_pages; i++) {
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auto phys_addr = compressed_physical_ptr[start_page_d + i];
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compressed_physical_ptr[start_page_d + i] = 0;
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cpu_backing_address[start_page_d + i] = 0;
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if (phys_addr != 0) {
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compressed_device_addr[phys_addr - 1] = 0;
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}
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@ -301,4 +311,66 @@ void DeviceMemoryManager<Traits>::UnregisterProcess(size_t id) {
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id_pool.push_front(id);
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}
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template <typename Traits>
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void DeviceMemoryManager<Traits>::UpdatePagesCachedCount(DAddr addr, size_t size, s32 delta) {
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u64 uncache_begin = 0;
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u64 cache_begin = 0;
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u64 uncache_bytes = 0;
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u64 cache_bytes = 0;
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const auto* MarkRegionCaching = &DeviceMemoryManager<Traits>::DeviceMethods::MarkRegionCaching;
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std::atomic_thread_fence(std::memory_order_acquire);
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const size_t page_end = Common::DivCeil(addr + size, Memory::YUZU_PAGESIZE);
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size_t page = addr >> Memory::YUZU_PAGEBITS;
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auto [process_id, base_vaddress] = ExtractCPUBacking(page);
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size_t vpage = base_vaddress >> Memory::YUZU_PAGEBITS;
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auto* memory_interface = registered_processes[process_id];
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for (; page != page_end; ++page) {
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std::atomic_uint16_t& count = cached_pages->at(page >> 2).Count(page);
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if (delta > 0) {
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ASSERT_MSG(count.load(std::memory_order::relaxed) < std::numeric_limits<u16>::max(),
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"Count may overflow!");
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} else if (delta < 0) {
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ASSERT_MSG(count.load(std::memory_order::relaxed) > 0, "Count may underflow!");
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} else {
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ASSERT_MSG(false, "Delta must be non-zero!");
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}
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// Adds or subtracts 1, as count is a unsigned 8-bit value
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count.fetch_add(static_cast<u16>(delta), std::memory_order_release);
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// Assume delta is either -1 or 1
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if (count.load(std::memory_order::relaxed) == 0) {
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if (uncache_bytes == 0) {
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uncache_begin = vpage;
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}
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uncache_bytes += Memory::YUZU_PAGESIZE;
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} else if (uncache_bytes > 0) {
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MarkRegionCaching(memory_interface, uncache_begin << Memory::YUZU_PAGEBITS,
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uncache_bytes, false);
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uncache_bytes = 0;
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}
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if (count.load(std::memory_order::relaxed) == 1 && delta > 0) {
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if (cache_bytes == 0) {
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cache_begin = vpage;
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}
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cache_bytes += Memory::YUZU_PAGESIZE;
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} else if (cache_bytes > 0) {
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MarkRegionCaching(memory_interface, cache_begin << Memory::YUZU_PAGEBITS, cache_bytes,
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true);
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cache_bytes = 0;
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}
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vpage++;
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}
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if (uncache_bytes > 0) {
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MarkRegionCaching(memory_interface, uncache_begin << Memory::YUZU_PAGEBITS, uncache_bytes,
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false);
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}
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if (cache_bytes > 0) {
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MarkRegionCaching(memory_interface, cache_begin << Memory::YUZU_PAGEBITS, cache_bytes,
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true);
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}
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}
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} // namespace Core
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@ -5,6 +5,17 @@
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#include "video_core/host1x/gpu_device_memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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namespace Tegra {
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struct MaxwellDeviceMethods {
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static inline void MarkRegionCaching(Core::Memory::Memory* interface, VAddr address,
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size_t size, bool caching) {
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interface->RasterizerMarkRegionCached(address, size, caching);
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}
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};
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} // namespace Tegra
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template struct Core::DeviceMemoryManagerAllocator<Tegra::MaxwellDeviceTraits>;
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template class Core::DeviceMemoryManager<Tegra::MaxwellDeviceTraits>;
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@ -9,10 +9,13 @@ class RasterizerInterface;
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namespace Tegra {
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struct MaxwellDeviceMethods;
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struct MaxwellDeviceTraits {
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static constexpr bool supports_pinning = true;
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static constexpr size_t device_virtual_bits = 34;
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using DeviceInterface = typename VideoCore::RasterizerInterface;
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using DeviceMethods = typename MaxwellDeviceMethods;
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};
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using MaxwellDeviceMemoryManager = Core::DeviceMemoryManager<MaxwellDeviceTraits>;
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