shader_ir: Implement NOP
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978f7067ee
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2ff8044806
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@ -559,6 +559,11 @@ union Instruction {
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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union {
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BitField<8, 5, ConditionCode> cc;
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BitField<13, 1, u64> trigger;
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} nop;
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union {
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BitField<8, 8, Register> gpr;
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BitField<20, 24, s64> offset;
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@ -1516,6 +1521,7 @@ public:
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TMML, // Texture Mip Map Level
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SUST, // Surface Store
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EXIT,
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NOP,
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IPA,
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OUT_R, // Emit vertex/primitive
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ISBERD,
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@ -1795,6 +1801,7 @@ private:
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INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
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INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
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INST("11101011001-----", Id::SUST, Type::Image, "SUST"),
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INST("0101000010110---", Id::NOP, Type::Trivial, "NOP"),
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INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
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INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
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INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
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@ -22,6 +22,12 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::NOP: {
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UNIMPLEMENTED_IF(instr.nop.cc != Tegra::Shader::ConditionCode::T);
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UNIMPLEMENTED_IF(instr.nop.trigger != 0);
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// With the previous preconditions, this instruction is a no-operation.
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break;
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}
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case OpCode::Id::EXIT: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}",
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