Merge pull request #3054 from FernandoS27/fix-tld4-2
shader_ir: Fix regression on TLD4
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commit
11e39da02b
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@ -119,7 +119,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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: instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI);
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WriteTexInstructionFloat(
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bb, instr,
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GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless), true);
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GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless));
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break;
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}
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case OpCode::Id::TLD4S: {
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@ -366,11 +366,10 @@ const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg,
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components,
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bool is_tld4) {
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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if (!is_tld4 && !instr.tex.IsComponentEnabled(elem)) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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@ -326,7 +326,7 @@ private:
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Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits);
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void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components, bool is_tld4 = false);
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const Node4& components);
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void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components, bool ignore_mask = false);
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