132030fcf2
- During interrupt handling the PICSR, table pointers and current
interrupt line have been saved in incorrect registers and/or stored on
the stack.
- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
line in r22. Those are callee-saved registers, so that the register
values will be preserved.
* or1k/interruts-asm.S: Change registers to callee-saved.
163 lines
5.1 KiB
ArmAsm
163 lines
5.1 KiB
ArmAsm
/* interrupts-asm.S -- interrupt handling for OpenRISC 1000.
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*
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* Copyright (c) 2011, 2012, 2014 Authors
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*
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* Contributor Julius Baxter <juliusbaxter@gmail.com>
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* Contributor Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* -------------------------------------------------------------------------- */
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/*!Generic interrupt handler function for or1k
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*/
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/* -------------------------------------------------------------------------- */
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#include "include/or1k-asm.h"
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#include "include/or1k-sprs.h"
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.extern _or1k_interrupt_handler_table
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.extern _or1k_interrupt_handler_data_ptr_table
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/* -------------------------------------------------------------------------- */
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/*!Function to call appropriate interrupt handler
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*/
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/* -------------------------------------------------------------------------- */
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.section .text
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.global _or1k_interrupt_handler
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.type _or1k_interrupt_handler,@function
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_or1k_interrupt_handler:
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/* Make room on stack, save link address register */
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l.addi r1,r1,-4
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l.sw 0(r1),r9
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/* Read PICSR */
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l.mfspr r20,r0,OR1K_SPR_PIC_PICSR_ADDR
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/* Load handler table base address */
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// Needs to be callee-saved register
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l.movhi r16,hi(_or1k_interrupt_handler_table)
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l.ori r16,r16,lo(_or1k_interrupt_handler_table)
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/* Load data pointer table base address */
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// Needs to be callee-saved register
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l.movhi r18,hi(_or1k_interrupt_handler_data_ptr_table)
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l.ori r18,r18,lo(_or1k_interrupt_handler_data_ptr_table)
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#ifdef __OR1K_MULTICORE__
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/* Read the addresses of the arrays of cores */
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/* r7 = (*or1k_interrupt_handler_table) */
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l.lwz r16,0(r16)
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/* r12 = (*or1k_interrupt_handler_data_ptr_table) */
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l.lwz r18,0(r18)
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/* Generate offset in arrays */
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/* r14 = coreid */
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l.mfspr r14,r0,OR1K_SPR_SYS_COREID_ADDR
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/* r14 = coreid*32*4 = off */
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l.slli r14,r14,7
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/* r7 = (*or1k_exception_handler_table)[coreid] */
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l.add r16,r16,r14
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/* r12 = (*or1k_exception_handler_table)[coreid] */
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l.add r18,r18,r14
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#endif
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.L0:
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/* Find first set bit in PICSR */
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l.ff1 r4,r20
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/* Any bits set? */
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l.sfne r4,r0
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/* If none, finish */
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf .L2))
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/* What is IRQ function table offset? */
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l.addi r22,r4,-1
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l.slli r6,r22,2
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/* Add this to table bases */
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l.add r14,r6,r16
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l.add r13,r6,r18
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/* Fetch handler function address */
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l.lwz r14,0(r14)
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/* Double check it's valid, compare against INTERRUPT_HANDLER_NOT_SET */
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l.sfne r14,r0
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/* Skip if no handler: TODO: Indicate interrupt fired but no handler*/
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf .L1))
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/* Call handler, load data pointer */
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OR1K_DELAYED(
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OR1K_INST(l.lwz r3,0(r13)),
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OR1K_INST(l.jalr r14)
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)
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.L1:
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/* Clear bit from PICSR, return to start of checking loop */
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l.ori r6,r0,1
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l.sll r6,r6,r22
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OR1K_DELAYED(
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OR1K_INST(l.xor r20,r20,r6),
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OR1K_INST(l.j .L0)
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)
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.L2:
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/* Finish up - write PICSR back, restore r9*/
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l.lwz r9,0(r1)
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l.mtspr r0,r20,OR1K_SPR_PIC_PICSR_ADDR
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OR1K_DELAYED(
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OR1K_INST(l.addi r1,r1,4),
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OR1K_INST(l.jr r9)
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)
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/* -------------------------------------------------------------------------- */
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/*!Function to enable an interrupt handler in the PICMR
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_interrupt_enable
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.type or1k_interrupt_enable,@function
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/* r3 should have IRQ line for peripheral */
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or1k_interrupt_enable:
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l.addi r1,r1,-4
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l.sw 0(r1),r4
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l.ori r4,r0,0x1
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l.sll r4,r4,r3
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l.mfspr r3,r0,OR1K_SPR_PIC_PICMR_ADDR
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l.or r3,r3,r4
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l.mtspr r0,r3,OR1K_SPR_PIC_PICMR_ADDR
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l.lwz r4,0(r1)
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OR1K_DELAYED(
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OR1K_INST(l.addi r1,r1,4),
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OR1K_INST(l.jr r9)
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)
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/* -------------------------------------------------------------------------- */
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/*!Function to disable an interrupt handler in the PICMR
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_interrupt_disable
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.type or1k_interrupt_disable,@function
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/* r3 should have IRQ line for peripheral */
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or1k_interrupt_disable:
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l.addi r1,r1,-4
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l.sw 0(r1),r4
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l.ori r4,r0,0x1
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l.sll r4,r4,r3
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l.xori r4,r4,0xffff
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l.mfspr r3,r0,OR1K_SPR_PIC_PICMR_ADDR
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l.and r3,r3,r4
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l.mtspr r0,r3,OR1K_SPR_PIC_PICMR_ADDR
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l.lwz r4,0(r1)
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OR1K_DELAYED(
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OR1K_INST(l.addi r1,r1,4),
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OR1K_INST(l.jr r9)
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)
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