Commit Graph

580 Commits

Author SHA1 Message Date
Svein Seldal 14d304da97 Updates for fixing tic4x arch tagging of its object files.
* bfd/coffcode.h (coff_set_flags): Added get/set arch hooks.
	* include/coff/tic4x.h (TICOFF_TARGET_MACHINE_GET): Fixed define bug
	* include/coff/ti.h (TICOFF_TARGET_MACHINE_GET): Added macros
	* ld/Makefile.am: Added etic3xcoff.o and etic4xcoff_onchip.o
	* ld/Makefile.in: Regenerate
	* ld/configure.tgt: Added extra target emulations
	* ld/emulparams/tic3xcoff.sh: Remove old settings
	* ld/emulparams/tic4xcoff.sh: Ditto
	* ld/emulparams/tic3xcoff-onchip.sh: Added new
	* ld/scripttempl/tic4xcoff.sc: Revise and combine both c3x and c4x
	* ld/scripttempl/tic3xcoff.sc: Remove
2003-01-20 22:34:39 +00:00
Martin Schwidefsky d52cfbfdd8 * s390.h: Rename R_390_GOTOFF to R_390_GOTOFF32. Add new gotoff,
gotplt and pltoff relocations.
2003-01-20 11:51:38 +00:00
Alan Modra d4d80d8c65 missed changelog entry 2003-01-17 01:33:13 +00:00
Alan Modra 8c228f4b0f * common.h: Formatting, typo fixes.
(DT_ENCODING): Correct value.

	* common.h (ELFOSABI_AROS): Define.
	(ELFOSABI_OPENVMS): Likewise.
	(ELFOSABI_NSK): Likewise.
2003-01-17 01:32:46 +00:00
Alan Modra 0036d6bdaa * ppc.h: Split out ppc64 definitions to..
* pcc64.h: ..here.  New file.
	(R_PPC64_REL30): Rename from R_PPC64_ADDR30.
2003-01-16 04:08:47 +00:00
Nick Clifton 948039cf4a Change EM_MSP430 value to new, officially assigned number. 2003-01-13 16:37:47 +00:00
DJ Delorie be99c75bd8 merge from gcc 2003-01-10 03:27:26 +00:00
Chris Demetriou f981849c93 2003-01-07 Chris Demetriou <cgd@broadcom.com>
* mips.h: Fix missing space in comment.
        (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
        (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
        by four bits.
2003-01-08 07:36:47 +00:00
Stan Cox d26127a55a * dis-asm.h (print_insn_iq2000): Declare.
* common.h (EM_IQ2000): Define.
	* iq2000.h: New file.
2003-01-03 18:03:18 +00:00
Chris Demetriou 4aa028aae0 [ gas/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * config/tc-mips.c: Update copyright years to include 2003.
        (mips_ip): Fix indentation of "+A", "+B", and "+C" handling.
        Additionally, clean up their code slightly and clean up their
        comments some more.


        * doc/c-mips.texi: Add MIPS32r2 to ".set mipsN" documentation.

[ gas/testsuite/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/elf_arch_mips32r2.d: Fix file description comment.

[ include/opcode/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * mips.h: Update copyright years to include 2002 (which had
        been missed previously) and 2003.  Make comments about "+A",
        "+B", and "+C" operand types more descriptive.
2003-01-02 20:03:09 +00:00
Chris Demetriou ba5b714aab [ gas/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
	the "+D" operand, which will be used only by the disassembler.

[ gas/testsuite/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0sel-names-mips32.d: New test.
	* gas/mips/cp0sel-names-mips32r2.d: New test.
	* gas/mips/cp0sel-names-mips64.d: New test.
	* gas/mips/cp0sel-names-numeric.d: New test.
	* gas/mips/cp0sel-names-sb1.d: New test.
	* gas/mips/cp0sel-names.s: New test source file.
	* gas/mips/mips.exp: Run new tests.

[ include/opcode/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Note that the "+D" operand type name is now used.

[ opcodes/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0sel_name): New structure.
	(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
	(mips_cp0sel_names_sb1): New arrays.
	(mips_arch_choice): New structure members "cp0sel_names" and
	"cp0sel_names_len".
	(mips_arch_choices): Add references to new cp0sel_names arrays
	as appropriate, and make all existing entries reference
	appropriate mips_XXX_names_numeric arrays rather than simply
	using NULL.
	(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
	(lookup_mips_cp0sel_name): New function.
	(set_default_mips_dis_options): Set mips_cp0sel_names and
	mips_cp0sel_names_len as appropriate.  Remove now-unnecessary
	checks for NULL register name arrays.
	(parse_mips_dis_option): Likewise.
	(print_insn_arg): Handle "+D" operand type.
	* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
	of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
	names symbolically.
2002-12-31 08:11:18 +00:00
Chris Demetriou 1de386c0a1 [ bfd/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
	* archures.c (bfd_mach_mipsisa32r2): New define.
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsisa32r2): New enum value.
	(arch_info_struct): Add entry for I_mipsisa32r2.
	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
	(_bfd_mips_elf_final_write_processing): Add
	bfd_mach_mipsisa32r2 case.
	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
	binaries marked as using MIPS32 Release 2.

[ binutils/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
	changes in MIPS -M options.

[ gas/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
	CPU variants.
	* configure: Regenerate.
	* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
	(macro_build): Handle "K" operand.
	(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
	CPU_HAS_DROR and CPU_HAS_ROR are currently used.
	(mips_ip): New variable "lastpos", and implement "+A", "+B",
	and "+C" operands for MIPS32 Release 2 ins/ext instructions.
	Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
	(validate_mips_insn): Implement "+" as a way to extend the
	allowed operands, and implement "K", "+A", "+B", and "+C"
	operands.
	(OPTION_MIPS32R2): New define.
	(md_longopts): Add entry for OPTION_MIPS32R2.
	(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
	(md_parse_option): Handle OPTION_MIPS32R2.
	(s_mipsset): Reimplement handling of ".set mipsN" options
	and add support for ".set mips32r2".
	(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
	(md_show_usage): Document "-mips32r2" option.
	* doc/as.texinfo: Document "-mips32r2" option.
	* doc/c-mips.texi: Likewise.

[ gas/testsuite/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0-names-mips32r2.d: New test.
	* gas/mips/hwr-names-mips32r2.d: New test.
	* gas/mips/hwr-names-numeric.d: New test.
	* gas/mips/hwr-names.s: New test source file.
	* gas/mips/mips32r2.d: New test.
	* gas/mips/mips32r2.s: New test source file.
	* gas/mips/mips32r2-ill.l: New test.
	* gas/mips/mips32r2-ill.s: New test source file.
	* gas/mips/mips.exp: Add mips32r2 architecture data array
	entry.  Run new tests mentioned above.

[ include/elf/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h (E_MIPS_ARCH_32R2): New define.

[ include/opcode/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Document "+" as the start of two-character operand
	type names, and add new "K", "+A", "+B", and "+C" operand types.
	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
	defines.

[ opcodes/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
	(mips_hwr_names_mips3264r2): New arrays.
	(mips_arch_choice): New "hwr_names" member.
	(mips_arch_choices): Adjust for structure change, and add a new
	entry for "mips32r2" ISA.
	(mips_hwr_names): New variable.
	(set_default_mips_dis_options): Set mips_hwr_names.
	(parse_mips_dis_option): New "hwr-names" option which sets
	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
	(print_insn_arg): Change return type to "int"
	and use that to indicate number of characters consumed.
	Add support for "+" operand extension character, "+A", "+B",
	"+C", and "K" operands.
	(print_insn_mips): Adjust for changes to print_insn_arg.
	(print_mips_disassembler_options): Adjust for "hwr-names"
	addition and "reg-names" change.
	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
	Note that hardware rotate instructions (ror, rorv) can be
	used on MIPS32 Release 2, and add the official mnemonics
	for them (rotr, rotrv) and the similar "rotl" mnemonic for
	left-rotate.
2002-12-31 07:29:29 +00:00
Nick Clifton 9f3255cee6 Add support for msp430. 2002-12-30 19:25:12 +00:00
Nick Clifton df73991943 Added some more pseudo opcodes for system call processing. 2002-12-30 10:50:32 +00:00
Chris Demetriou 08fe4973cd [ binutils/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * doc/binutils.texi (objdump): Document MIPS -M options.

[ gas/testsuite/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/cp0-names-mips32.d: New file.
        * gas/mips/cp0-names-mips64.d: New file.
        * gas/mips/cp0-names-numeric.d: New file.
        * gas/mips/cp0-names-sb1.d: New file.
        * gas/mips/cp0-names.s: New file.
        * gas/mips/fpr-names-32.d: New file.
        * gas/mips/fpr-names-64.d: New file.
        * gas/mips/fpr-names-n32.d: New file.
        * gas/mips/fpr-names-numeric.d: New file.
        * gas/mips/fpr-names.s: New file.
        * gas/mips/gpr-names-32.d: New file.
        * gas/mips/gpr-names-64.d: New file.
        * gas/mips/gpr-names-n32.d: New file.
        * gas/mips/gpr-names-numeric.d: New file.
        * gas/mips/gpr-names.s: New file.
        * gas/mips/mips.exp: Run new tests.

[ include/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * dis-asm.h (print_mips_disassembler_options): Prototype.

[ include/opcode/ChangeLog ]
2002-12-19  Chris Demetriou  <cgd@broadcom.com>

        * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
        (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
        (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
        (OP_OP_SDC2, OP_OP_SDC3): Define.

[ opcodes/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * disassemble.c (disassembler_usage): Add invocation of
        print_mips_disassembler_options.
        * mips-dis.c (print_mips_disassembler_options)
        (set_default_mips_dis_options, parse_mips_dis_option)
        (parse_mips_dis_options, choose_abi_by_name, choose_arch_by_name)
        (choose_arch_by_number): New functions.
        (mips_abi_choice, mips_arch_choice): New structures.
        (mips32_reg_names, mips64_reg_names, reg_names): Remove.
        (mips_gpr_names_numeric, mips_gpr_names_oldabi)
        (mips_gpr_names_newabi, mips_fpr_names_numeric)
        (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
        (mips_cp0_names_numeric, mips_cp0_names_mips3264)
        (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
        (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
        (mips_cp0_names): New variables.
        (print_insn_args): Use new variables to print GPR, FPR, and CP0
        register names.
        (mips_isa_type): Remove.
        (print_insn_mips): Remove ISA and CPU setup since it is now done...
        (_print_insn_mips): Here.  Remove register setup code, and
        call set_default_mips_dis_options and parse_mips_dis_options
        instead.
        (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
2002-12-27 08:00:31 +00:00
Kazu Hirata d9633de92c * sim-h8300.h: Remove ^M. 2002-12-26 06:14:43 +00:00
Alan Modra e2ddab05fc * bfdlink.h (struct bfd_link_info): Add "strip_discarded". 2002-12-23 11:53:12 +00:00
DJ Delorie 120f285b61 * xstormy16.h: Add XSTORMY16_12. 2002-12-20 21:13:42 +00:00
Alan Modra e9f731caf7 * bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with
bit-fields.  Rearrange to put all like types together.
2002-12-19 23:05:39 +00:00
DJ Delorie 02f2ba2b0b * xstormy16.h (START_RELOC_NUMBERS) Add relocation numbers
for R_XSTORMY16_LO16 and R_XSTORMY16_HI16.
2002-12-17 03:57:00 +00:00
Alan Modra 84c221c08e * hppa.h (completer_chars): #if 0 out. 2002-12-16 09:57:03 +00:00
Alan Modra b446bff5bc * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
"default_args".
	(struct not_wot): Constify "args".
	(struct not): Constify "name".
	(numopcodes): Delete.
	(endop): Delete.
2002-12-16 09:53:48 +00:00
Alan Modra b7ff6b340d * pj.h (pj_opc_info_t): Add union.
* pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.

	* config/tc-pj.c (little, big, parse_exp_save_ilp): Prototype.
	(c_to_r, ipush_code, fake_opcode, alias): Likewise.
	(fake_opcode): Adjust for pj_opc_int_t change.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	(ipush_code): Correct parse_exp_save_ilp call.  Test pending_reloc
	instead of non-existent third arg of parse_exp_save_ilp.
	(md_parse_option): Correct "little" and "big" calls.
2002-12-12 21:52:05 +00:00
Nick Clifton d6a24c4840 Add support for displaying extension to DWARF2 used by Unified Parallel C
compiler.
2002-12-10 17:48:27 +00:00
Jim Wilson 94d815b251 Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
	* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
	* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
	instruction.
	(emit_one_bundle): Handle "hint" instruction.
	(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
	* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
	* gas/ia64/opc-b.s: Ditto.
	* gas/ia64/opc-f.d: Ditto.
	* gas/ia64/opc-f.s: Ditto.
	* gas/ia64/opc-i.d: Ditto.
	* gas/ia64/opc-i.s: Ditto.
	* gas/ia64/opc-m.d: Ditto.
	* gas/ia64/opc-m.s: Ditto.
	* gas/ia64/opc-x.d: Ditto.
	* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
	* ia64.h: Fix copyright message.
	(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
	* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
	* ia64-opc-b.c: Add "hint.b" instruction.
	* ia64-opc-f.c: Add "hint.f" instruction.
	* ia64-opc-i.c: Add "hint.i" instruction.
	* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
	"cmp8xchg16" instructions.
	* ia64-opc-x.c: Add "hint.x" instruction.
	* ia64-opc.h (AR_CSD): New macro.
	* ia64-ic.tbl: Update according to SDM2.1.
	* ia64-raw.tbl: Ditto.
	* ia64-waw.tbl: Ditto.
	* ia64-gen.c (in_iclass): Handle "hint" like "nop".
	(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
	AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
	* ia64-asmtab.c: Regenerate.
2002-12-05 02:08:02 +00:00
Richard Henderson 270268370a include/opcode/
* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
bfd/
        * cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry.
opcodes/
        * ia64-opc-m.c: Add ld8.mov.
        * ia64-asmtab.c: Regenerate.
gas/
        * config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case.
gas/testsuite/
        * gas/ia64/ldxmov-1.[ds]: New.
        * gas/ia64/ldxmov-2.[ls]: New.
        * gas/ia64/ia64.exp: Run them.
2002-12-03 18:15:46 +00:00
Alan Modra fcdef14b08 * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
Constify "leaf" and "multi".
2002-12-02 21:51:52 +00:00
Stephane Carrez 8d49f1c93e * m68hc11.h (EF_M68HC12_MACH, EF_M68HCS12_MACH): Define.
(EF_M68HC11_MACH_MASK, EF_M68HC11_MACH): Define.
	(EF_M68HC11_MERGE_MACH, EF_M68HC11_CAN_MERGE_MACH): Define.
2002-12-01 12:16:21 +00:00
Alan Modra 73593ea1dd s/boolean/bfd_boolean/ s/true/TRUE/ s/false/FALSE/. Simplify
comparisons of bfd_boolean vars with TRUE/FALSE.  Formatting.
2002-11-30 08:39:45 +00:00
Alan Modra 5a74d15e43 include/elf/ChangeLog
* internal.h (elf32_internal_ehdr, Elf32_Internal_Ehdr,
	elf64_internal_ehdr, Elf64_Internal_Ehdr, elf32_internal_phdr,
	Elf32_Internal_Phdr, elf64_internal_phdr, Elf64_Internal_Phdr,
	elf32_internal_shdr, Elf32_Internal_Shdr, elf64_internal_shdr,
	Elf64_Internal_Shdr, elf32_internal_sym, elf64_internal_sym,
	Elf32_Internal_Sym, Elf64_Internal_Sym, Elf32_Internal_Note,
	elf32_internal_note, elf32_internal_rel, Elf32_Internal_Rel,
	elf64_internal_rel, Elf64_Internal_Rel, elf32_internal_rela,
	elf64_internal_rela, Elf32_Internal_Rela, Elf64_Internal_Rela,
	elf32_internal_dyn, elf64_internal_dyn, Elf32_Internal_Dyn,
	Elf64_Internal_Dyn, elf32_internal_verdef, elf64_internal_verdef,
	elf32_internal_verdaux, elf64_internal_verdaux, elf32_internal_verneed,
	elf64_internal_verneed, elf32_internal_vernaux, elf64_internal_vernaux,
	elf32_internal_versym, elf64_internal_versym, Elf32_Internal_Verdef,
	Elf64_Internal_Verdef, Elf32_Internal_Verdaux, Elf64_Internal_Verdaux,
	Elf32_Internal_Verneed, Elf64_Internal_Verneed, Elf32_Internal_Vernaux,
	Elf64_Internal_Vernaux, Elf32_Internal_Versym, Elf64_Internal_Versym,
	Elf32_Internal_Syminfo, Elf64_Internal_Syminfo): Delete.
	(Elf_Internal_Rel): Delete.

bfd/ChangeLog
	* elf-bfd.h: Replace occurrences of Elf32_Internal_* and
	Elf64_Internal_* with Elf_Internal_*.  Replace Elf_Internal_Rel
	with Elf_Internal_Rela.
	* elf-hppa.h, elf-m10200.c, elf-m10300.c, elf32-arc.c, elf32-arm.h,
	elf32-avr.c, elf32-cris.c, elf32-d10v.c, elf32-d30v.c, elf32-dlx.c,
	elf32-fr30.c, elf32-frv.c, elf32-gen.c, elf32-h8300.c, elf32-hppa.c,
	elf32-i370.c, elf32-i386.c, elf32-i860.c, elf32-i960.c, elf32-ip2k.c,
	elf32-m32r.c, elf32-m68hc11.c, elf32-m68hc12.c, elf32-m68k.c,
	elf32-mcore.c, elf32-mips.c, elf32-openrisc.c, elf32-or32.c,
	elf32-ppc.c, elf32-s390.c, elf32-sh.c, elf32-v850.c, elf32-vax.c,
	elf32-xstormy16.c, elf64-alpha.c, elf64-gen.c, elf64-hppa.c,
	elf64-mips.c, elf64-mmix.c, elf64-ppc.c, elf64-s390.c, elf64-sh64.c,
	elf64-sparc.c, elf64-x86-64.c, elfarm-nabi.c, elfarm-oabi.c,
	elfcode.h, elflink.h, elfn32-mips.c, elfxx-ia64.c, elfxx-mips.c: Ditto.
	* elf-hppa.h (elf_hppa_internal_shdr): Delete.  Use Elf_Internal_Shdr
	throughout instead.
	* elf.c (_bfd_elf_no_info_to_howto_rel): Delete.
	* elfcode.h (elf_swap_reloca_in): Pass source operand as a bfd_byte *.
	Remove INLINE keyword.
	(elf_swap_reloc_in): Likewise.  Also clear r_addend.
	(elf_swap_reloc_out, elf_swap_reloca_out): Pass destination operand
	as a bfd_byte *.
	(elf_write_relocs): Consolidate REL and RELA code.
	(elf_slurp_reloc_table_from_section): Simplify REL code.
	(NAME(_bfd_elf,size_info)): Populate reloc swap entries.
	* elf-bfd.h (MAX_INT_RELS_PER_EXT_REL): Define.
	* elflink.h (elf_link_read_relocs_from_section): Consolidate REL and
	RELA code.
	(elf_link_adjust_relocs): Likewise.  Don't malloc space for temp
	reloc array, use a fixed size of MAX_INT_RELS_PER_EXT_REL.
	(elf_link_output_relocs): Likewise.
	(elf_reloc_link_order): Likewise.
	(elf_finish_pointer_linker_section): Likewise.
	(struct elf_link_sort_rela): Remove union.
	(elf_link_sort_cmp1): Update to suit.
	(elf_link_sort_cmp2): Here too.
	(elf_link_sort_relocs): Consolidate REL and RELA code.  Fix memory
	over-allocation for int_rels_per_ext_rel != 1 case.
	* elf32-arm.h: Update all bfd_elf32_swap_reloc_out calls.
	* elf32-i386.c: Likewise.
	* elf32-cris.c: Likewise for bfd_elf32_swap_reloca_out.
	* elf32-hppa.c, elf32-i370.c, elf32-m68k.c, elf32-ppc.c, elf32-s390.c,
	elf32-sh.c, elf32-vax.c, elfxx-mips.c: Likewise.
	* elf64-alpha.c: Likewise for bfd_elf64_swap_reloca_out.
	* elf64-hppa.c, elf64-mips.c, elf64-ppc.c, elf64-s390.c, elf64-sh64.c,
	elf64-sparc.c, elf64-x86-64.c: Likewise.
	* elfxx-ia64.c: Likewise for bfd_elfNN_swap_reloca_out.
	* elfxx-mips.c (sort_dynamic_relocs): Likewise for
	bfd_elf32_swap_reloc_in.

	* elf32-arm.h: Update elf32_arm_info_to_howto calls.
	* elf32-mips.c: Likewise for mips_info_to_howto_rel.
	(mips_elf64_swap_reloc_in): Zero r_addend.
	(mips_elf64_be_swap_reloc_in): Likewise.
	(mips_elf64_slurp_one_reloc_table): Simplify.

	* elf64-alpha.c (alpha_elf_size_info): Populate reloc swap entries.
	* elf64-hppa.c (hppa64_elf_size_info): Likewise.
	* elf64-sparc.c (sparc64_elf_size_info): Likewise.
2002-11-28 11:55:34 +00:00
Jason Thorpe f29c4db185 * libiberty.h (basename): Add NetBSD to the list. 2002-11-24 06:58:20 +00:00
DJ Delorie aa1ad0633b merge from gcc 2002-11-22 21:02:07 +00:00
Klee Dienes ec97538aa2 2002-11-19 Klee Dienes <kdienes@apple.com>
* h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
        fields.
        (h8_opcodes). Modify initializer and initializer macros to no
        longer initialize the removed fields.
2002-11-19 22:56:14 +00:00
Svein Seldal dfac831ba8 Fixed LDHI constraint 2002-11-19 11:59:12 +00:00
Klee Dienes f7133e95e9 2002-11-11 Klee Dienes <kdienes@apple.com>
* h8300.h (h8_opcode): Remove 'length' field.
	(h8_opcodes): Mark as 'const' (both the declaration and
	definition).  Modify initializer and initializer macros to no
	longer initialize the length field.

2002-11-11  Klee Dienes  <kdienes@apple.com>

	* h8300-dis.c: Include libiberty.h (for xmalloc).
	(struct h8_instruction): New type, used to wrap h8_opcodes with a
	length field (computed at run-time).
	(h8_instructions): New variable.
	(bfd_h8_disassemble_init): Allocate the storage for
	h8_instructions.  Fill h8_instructions with pointers to the
	appropriate opcode and the correct value for the length field.
	(bfd_h8_disassemble): Iterate through h8_instructions instead of
	h8_opcodes.
2002-11-18 16:52:44 +00:00
Klee Dienes 2b92bf13ea 2002-11-18 Klee Dienes <kdienes@apple.com>
* arc.h (arc_ext_opcodes): Declare as extern.
	(arc_ext_operands): Declare as extern.
	* i860.h (i860_opcodes): Declare as const.

2002-11-18  Klee Dienes  <kdienes@apple.com>

	* arc-opc.c (arc_ext_opcodes): Define.
	(arc_ext_operands): Define.
	* i386-dis.c (Suffix3DNow): Declare as const.
	* arm-opc.h (arm_opcodes): Declare as const.
	(thumb_opcodes): Declare as const.
	* h8500-opc.h (h8500_table): Declare as const.
	(h8500_table): Use a NULL for the opcode in the terminator, so
	that code testing (opcode->name) behaves correctly.
	* mcore-opc.h (mcore_table): Declare as const.
	* sh-opc.h (sh_table): Declare as const.
	* w65-opc.h (optable): Declare as const.
	* z8k-opc.h (z8k_table): Declare as const.
2002-11-18 16:49:56 +00:00
Svein Seldal dea6510472 Fixups in ChangeLog entries which has been filed in the wrong place. 2002-11-18 14:00:44 +00:00
Svein Seldal 6aec25d6c3 * gas/config/tc-tic4x.c: Fixed proper commandline
parameters. Added support for new opcode-list format. General
	error message fixups.
	(c4x_inst_add): Reject insn not for our CPU
	(md_begin): Added matrix for setting the proper opcode-level &
	device-flags according to cpu type and revision. Rewrite the
	opcode hasher.
	(c4x_operand_parse): Fix opcode bug
	(c4x_operands_match): New function argument. Added dry-run
	mechanism, that is optional error generation. Added constraint 'i'
	and 'j'.
	(c4x_insn_check): Added new function for post-verification of the
	generated insn.
	(md_assemble): Check all opcodes before croaking because of an
	argument mismatch. Need this to be able to fully support
	ortogonally arguments.
	(md_parse_options): Revised commandprompt swicthes and added new
	ones.
	(md_show_usage): Complete rewrite of printout.
	* gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn
	* gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter
	* gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter
	* gas/testsuite/gas/tic4x/allopcodes.S: Add support for new
	opclass.h changes
	* gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for
	the new enhanced opcodes.
	* gas/testsuite/gas/tic4x/opcodes.s: Regenerate
	* gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above
	* gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above
	* gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for
	the enhanced and special insns.
	* gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite
	* include/opcode/tic4x.h: File reordering. Added enhanced opcodes.
	* opcodes/tic4x-dis.c: Added support for enhanced and special
	insn.
	(c4x_print_op): Added insn class 'i' and 'j'
	(c4x_hash_opcode_special): Add to support special insn
	(c4x_hash_opcode): Update to support the new opcode-list
	format. Add support for the new special insns.
	(c4x_disassemble): New opcode-list support.
2002-11-18 09:09:34 +00:00
Klee Dienes 6a1c5a0395 2002-11-16 Klee Dienes <kdienes@apple.com>
* opcode/m88k.h (INSTAB): Remove 'next' field.
        (instruction): Remove definition; replace with extern declaration
        and mark as const.
W
2002-11-16 18:43:03 +00:00
Svein Seldal dab41351ea * gas/config/tc-tic4x.c: Remove c4x_pseudo_ignore function.
(c4x_operands_match): Added check for 8-bits LDF insn. Give
	  warning when using constant direct bigger than 2^16. Add the new
	  arguments.
	* include/opcode/tic4x.h: Major rewrite of entire file. Define
	  instruction classes, and put each instruction into a class.
	* opcodes/tic4x-dis.c: (c4x_print_op): Add support for the new
	  argument format. Fix bug in 'N' register printer.
2002-11-16 12:23:23 +00:00
Nick Clifton 69920bb5bd Add --enable-auto-import extension. 2002-11-14 18:03:17 +00:00
Svein Seldal bc612556a8 gas tic4x target enhancements (long list - see gas/ChangeLog and
include/ChangeLog)
2002-11-11 14:29:01 +00:00
DJ Delorie aaa7b02155 merge from gcc 2002-10-27 01:02:05 +00:00
DJ Delorie 238c78807d merge from gcc 2002-10-27 01:01:04 +00:00
DJ Delorie 7583434335 merge from gcc 2002-10-25 00:01:55 +00:00
DJ Delorie 6b67d752cc merge from gcc 2002-10-16 13:47:35 +00:00
Alan Modra ad1d049af9 * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. 2002-10-14 10:55:14 +00:00
Kaz Kojima 95a962432f * sh.h: Add SH TLS relocs. 2002-10-11 14:36:03 +00:00
Richard Sandiford 00a8c44a5b Fix date in last commit. 2002-09-30 12:08:05 +00:00
Richard Sandiford bf42f57df6 [include/opcode/]
* mips.h: Update comment for new opcodes.
	(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
	(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
	(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
	(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
	(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
	Don't match CPU_R4111 with INSN_4100.

[opcodes/]
	* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
	(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
	and bfd_mach_mips5500.
	* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
	(N411, N412, N5, N54, N55): New convenience defines.
	(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
	Change dmadd16 and madd16 from V1 to N411.
2002-09-30 11:58:09 +00:00