opcodes/ChangeLog
* cr16-dis.c (match_opcode,make_instruction: Remove static declaration. (dwordU,wordU): Moved typedefs to opcode/cr16.h (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_' bfd/Changelog * config.bfd (cr16*-*-uclinux*): New target support. include/opcode/ChangeLog * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c (make_instruction,match_opcode): Added function prototypes. (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
This commit is contained in:
Nick Clifton
parent
3b1c1875dd
commit
ff84dbd31f
@ -1,3 +1,9 @@
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2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
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(make_instruction,match_opcode): Added function prototypes.
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(cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
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2012-11-23 Alan Modra <amodra@gmail.com>
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* ppc.h (ppc_parse_cpu): Update prototype.
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@ -1,5 +1,5 @@
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/* cr16.h -- Header file for CR16 opcode and register tables.
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Copyright 2007, 2008, 2010 Free Software Foundation, Inc.
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Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc.
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Contributed by M R Swami Reddy
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This file is part of GAS, GDB and the GNU binutils.
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@ -26,21 +26,21 @@
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Therefore, order MUST be preserved. */
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typedef enum
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{
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/* 16-bit general purpose registers. */
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r0, r1, r2, r3,
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r4, r5, r6, r7,
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r8, r9, r10, r11,
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r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
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{
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/* 16-bit general purpose registers. */
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r0, r1, r2, r3,
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r4, r5, r6, r7,
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r8, r9, r10, r11,
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r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
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/* 32-bit general purpose registers. */
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r12 = 12, r13 = 13, r14 = 14, r15 = 15,
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era = 14, sp = 15, RA,
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/* 32-bit general purpose registers. */
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r12 = 12, r13 = 13, r14 = 14, r15 = 15,
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era = 14, sp = 15, RA,
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/* Not a register. */
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nullregister,
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MAX_REG
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}
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/* Not a register. */
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nullregister,
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MAX_REG
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}
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reg;
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/* CR16 processor registers and special registers :
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@ -48,33 +48,33 @@ reg;
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(cr16_pregtab). Therefore, order MUST be preserved. */
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typedef enum
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{
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/* processor registers. */
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dbs = MAX_REG,
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dsr, dcrl, dcrh,
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car0l, car0h, car1l, car1h,
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cfg, psr, intbasel, intbaseh,
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ispl, isph, uspl, usph,
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dcr = dcrl,
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car0 = car0l,
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car1 = car1l,
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intbase = intbasel,
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isp = ispl,
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usp = uspl,
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/* Not a processor register. */
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nullpregister = usph + 1,
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MAX_PREG
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}
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{
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/* processor registers. */
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dbs = MAX_REG,
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dsr, dcrl, dcrh,
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car0l, car0h, car1l, car1h,
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cfg, psr, intbasel, intbaseh,
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ispl, isph, uspl, usph,
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dcr = dcrl,
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car0 = car0l,
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car1 = car1l,
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intbase = intbasel,
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isp = ispl,
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usp = uspl,
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/* Not a processor register. */
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nullpregister = usph + 1,
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MAX_PREG
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}
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preg;
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/* CR16 Register types. */
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typedef enum
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{
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CR16_R_REGTYPE, /* r<N> */
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CR16_RP_REGTYPE, /* reg pair */
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CR16_P_REGTYPE /* Processor register */
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}
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{
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CR16_R_REGTYPE, /* r<N> */
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CR16_RP_REGTYPE, /* reg pair */
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CR16_P_REGTYPE /* Processor register */
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}
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reg_type;
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/* CR16 argument types :
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@ -89,69 +89,69 @@ reg_type;
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idxrp - index with register pair
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rbase - register base
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rpbase - register pair base
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pr - processor register */
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pr - processor register. */
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typedef enum
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{
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arg_r,
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arg_c,
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arg_cr,
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arg_crp,
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arg_ic,
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arg_icr,
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arg_idxr,
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arg_idxrp,
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arg_rbase,
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arg_rpbase,
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arg_rp,
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arg_pr,
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arg_prp,
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arg_cc,
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arg_ra,
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/* Not an argument. */
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nullargs
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}
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{
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arg_r,
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arg_c,
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arg_cr,
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arg_crp,
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arg_ic,
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arg_icr,
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arg_idxr,
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arg_idxrp,
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arg_rbase,
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arg_rpbase,
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arg_rp,
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arg_pr,
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arg_prp,
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arg_cc,
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arg_ra,
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/* Not an argument. */
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nullargs
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}
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argtype;
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/* CR16 operand types:The operand types correspond to instructions operands.*/
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/* CR16 operand types:The operand types correspond to instructions operands. */
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typedef enum
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{
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dummy,
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/* N-bit signed immediate. */
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imm3, imm4, imm5, imm6, imm16, imm20, imm32,
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/* N-bit unsigned immediate. */
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uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
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/* N-bit signed displacement. */
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disps5, disps17, disps25,
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/* N-bit unsigned displacement. */
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dispe9,
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/* N-bit absolute address. */
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abs20, abs24,
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/* Register relative. */
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rra, rbase, rbase_disps20, rbase_dispe20,
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/* Register pair relative. */
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rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
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rpbase_disps20, rpbase_dispe20,
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/* Register index. */
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rindex7_abs20, rindex8_abs20,
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/* Register pair index. */
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rpindex_disps0, rpindex_disps14, rpindex_disps20,
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/* register. */
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regr,
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/* register pair. */
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regp,
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/* processor register. */
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pregr,
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/* processor register 32 bit. */
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pregrp,
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/* condition code - 4 bit. */
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cc,
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/* Not an operand. */
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nulloperand,
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/* Maximum supported operand. */
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MAX_OPRD
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}
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{
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dummy,
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/* N-bit signed immediate. */
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imm3, imm4, imm5, imm6, imm16, imm20, imm32,
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/* N-bit unsigned immediate. */
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uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
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/* N-bit signed displacement. */
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disps5, disps17, disps25,
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/* N-bit unsigned displacement. */
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dispe9,
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/* N-bit absolute address. */
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abs20, abs24,
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/* Register relative. */
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rra, rbase, rbase_disps20, rbase_dispe20,
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/* Register pair relative. */
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rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
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rpbase_disps20, rpbase_dispe20,
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/* Register index. */
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rindex7_abs20, rindex8_abs20,
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/* Register pair index. */
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rpindex_disps0, rpindex_disps14, rpindex_disps20,
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/* register. */
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regr,
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/* register pair. */
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regp,
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/* processor register. */
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pregr,
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/* processor register 32 bit. */
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pregrp,
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/* condition code - 4 bit. */
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cc,
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/* Not an operand. */
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nulloperand,
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/* Maximum supported operand. */
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MAX_OPRD
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}
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operand_type;
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/* CR16 instruction types. */
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@ -239,126 +239,126 @@ operand_type;
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/* Single operand description. */
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typedef struct
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{
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/* Operand type. */
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operand_type op_type;
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/* Operand location within the opcode. */
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unsigned int shift;
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}
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{
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/* Operand type. */
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operand_type op_type;
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/* Operand location within the opcode. */
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unsigned int shift;
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}
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operand_desc;
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/* Instruction data structure used in instruction table. */
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typedef struct
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{
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/* Name. */
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const char *mnemonic;
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/* Size (in words). */
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unsigned int size;
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/* Constant prefix (matched by the disassembler). */
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unsigned long match; /* ie opcode */
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/* Match size (in bits). */
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/* MASK: if( (i & match_bits) == match ) then match */
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int match_bits;
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/* Attributes. */
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unsigned int flags;
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/* Operands (always last, so unreferenced operands are initialized). */
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operand_desc operands[MAX_OPERANDS];
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}
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{
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/* Name. */
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const char *mnemonic;
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/* Size (in words). */
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unsigned int size;
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/* Constant prefix (matched by the disassembler). */
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unsigned long match; /* ie opcode */
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/* Match size (in bits). */
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/* MASK: if( (i & match_bits) == match ) then match */
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int match_bits;
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/* Attributes. */
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unsigned int flags;
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/* Operands (always last, so unreferenced operands are initialized). */
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operand_desc operands[MAX_OPERANDS];
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}
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inst;
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/* Data structure for a single instruction's arguments (Operands). */
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typedef struct
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{
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/* Register or base register. */
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reg r;
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/* Register pair register. */
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reg rp;
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/* Index register. */
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reg i_r;
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/* Processor register. */
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preg pr;
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/* Processor register. 32 bit */
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preg prp;
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/* Constant/immediate/absolute value. */
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long constant;
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/* CC code. */
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unsigned int cc;
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/* Scaled index mode. */
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unsigned int scale;
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/* Argument type. */
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argtype type;
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/* Size of the argument (in bits) required to represent. */
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int size;
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{
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/* Register or base register. */
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reg r;
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/* Register pair register. */
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reg rp;
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/* Index register. */
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reg i_r;
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/* Processor register. */
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preg pr;
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/* Processor register. 32 bit */
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preg prp;
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/* Constant/immediate/absolute value. */
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long constant;
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/* CC code. */
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unsigned int cc;
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/* Scaled index mode. */
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unsigned int scale;
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/* Argument type. */
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argtype type;
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/* Size of the argument (in bits) required to represent. */
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int size;
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/* The type of the expression. */
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unsigned char X_op;
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}
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unsigned char X_op;
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}
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argument;
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/* Internal structure to hold the various entities
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corresponding to the current assembling instruction. */
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typedef struct
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{
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/* Number of arguments. */
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int nargs;
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/* The argument data structure for storing args (operands). */
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argument arg[MAX_OPERANDS];
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{
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/* Number of arguments. */
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int nargs;
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/* The argument data structure for storing args (operands). */
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argument arg[MAX_OPERANDS];
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/* The following fields are required only by CR16-assembler. */
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#ifdef TC_CR16
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/* Expression used for setting the fixups (if any). */
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expressionS exp;
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bfd_reloc_code_real_type rtype;
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/* Expression used for setting the fixups (if any). */
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expressionS exp;
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bfd_reloc_code_real_type rtype;
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#endif /* TC_CR16 */
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/* Instruction size (in bytes). */
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int size;
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}
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/* Instruction size (in bytes). */
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int size;
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}
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ins;
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/* Structure to hold information about predefined operands. */
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typedef struct
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{
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/* Size (in bits). */
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unsigned int bit_size;
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/* Argument type. */
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argtype arg_type;
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/* One bit syntax flags. */
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int flags;
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}
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{
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/* Size (in bits). */
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unsigned int bit_size;
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/* Argument type. */
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argtype arg_type;
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/* One bit syntax flags. */
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int flags;
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}
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operand_entry;
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/* Structure to hold trap handler information. */
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typedef struct
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{
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/* Trap name. */
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char *name;
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/* Index in dispatch table. */
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unsigned int entry;
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}
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{
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/* Trap name. */
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char *name;
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/* Index in dispatch table. */
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unsigned int entry;
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}
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trap_entry;
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/* Structure to hold information about predefined registers. */
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typedef struct
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{
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/* Name (string representation). */
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char *name;
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/* Value (enum representation). */
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union
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{
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/* Name (string representation). */
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char *name;
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/* Value (enum representation). */
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union
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{
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/* Register. */
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reg reg_val;
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/* processor register. */
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preg preg_val;
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} value;
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/* Register image. */
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int image;
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/* Register type. */
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reg_type type;
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}
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/* Register. */
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reg reg_val;
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/* processor register. */
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preg preg_val;
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} value;
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/* Register image. */
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int image;
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/* Register type. */
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reg_type type;
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}
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reg_entry;
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/* CR16 opcode table. */
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@ -435,4 +435,17 @@ extern const inst *instruction;
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typedef long long int LONGLONG;
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typedef unsigned long long ULONGLONG;
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/* Data types for opcode handling. */
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typedef unsigned long dwordU;
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typedef unsigned short wordU;
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/* Globals to store opcode data and build the instruction. */
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extern wordU cr16_words[3];
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extern ULONGLONG cr16_allWords;
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extern ins cr16_currInsn;
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/* Prototypes for function in cr16-dis.c. */
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extern void make_instruction (void);
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extern int match_opcode (void);
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#endif /* _CR16_H_ */
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