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@ -1,93 +1,110 @@
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/* Opcode table for the ARC.
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Copyright 1994, 1995, 1997 Free Software Foundation, Inc.
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Copyright 1994, 1995, 1997, 2000 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* List of the various cpu types.
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The tables currently use bit masks to say whether the instruction or
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whatever is supported by a particular cpu. This lets us have one entry
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apply to several cpus.
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This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd
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and bfd from this. Also note that these numbers are bit values as we want
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to allow for things available on more than one ARC (but not necessarily all
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ARCs). */
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/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
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The cpu type is treated independently of endianness.
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The complete `mach' number includes endianness.
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The `base' cpu must be 0. The cpu type is treated independently of
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endianness. The complete `mach' number includes endianness.
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These values are internal to opcodes/bfd/binutils/gas. */
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#define ARC_MACH_BASE 0
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#define ARC_MACH_UNUSED1 1
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#define ARC_MACH_UNUSED2 2
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#define ARC_MACH_UNUSED4 4
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#define ARC_MACH_5 0
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#define ARC_MACH_6 1
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#define ARC_MACH_7 2
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#define ARC_MACH_8 4
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/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */
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#define ARC_MACH_BIG 8
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#define ARC_MACH_BIG 16
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/* Mask of number of bits necessary to record cpu type. */
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#define ARC_MACH_CPU_MASK 7
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#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
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/* Mask of number of bits necessary to record cpu type + endianness. */
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#define ARC_MACH_MASK 15
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#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
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/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */
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typedef unsigned int arc_insn;
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struct arc_opcode {
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char *syntax; /* syntax of insn */
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unsigned long mask, value; /* recognize insn if (op&mask)==value */
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int flags; /* various flag bits */
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char *syntax; /* syntax of insn */
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unsigned long mask, value; /* recognize insn if (op&mask) == value */
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int flags; /* various flag bits */
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/* Values for `flags'. */
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/* Return CPU number, given flag bits. */
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#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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/* Return MACH number, given flag bits. */
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#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
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/* First opcode flag bit available after machine mask. */
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#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0)
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#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
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/* This insn is a conditional branch. */
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#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
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#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1)
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#define SYNTAX_LENGTH (SYNTAX_3OP )
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#define SYNTAX_2OP (SYNTAX_3OP << 1)
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#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1)
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#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
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#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1)
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/* These values are used to optimize assembly and disassembly. Each insn is
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on a list of related insns (same first letter for assembly, same insn code
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for disassembly). */
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struct arc_opcode *next_asm; /* Next instruction to try during assembly. */
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struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */
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#define I(x) (((x) & 31) << 27)
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#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
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#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
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#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
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#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
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/* Macros to create the hash values for the lists. */
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/* These values are used to optimize assembly and disassembly. Each insn
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is on a list of related insns (same first letter for assembly, same
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insn code for disassembly). */
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struct arc_opcode *next_asm; /* Next instr to try during assembly. */
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struct arc_opcode *next_dis; /* Next instr to try during disassembly. */
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/* Macros to create the hash values for the lists. */
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#define ARC_HASH_OPCODE(string) \
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((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
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#define ARC_HASH_ICODE(insn) \
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((unsigned int) (insn) >> 27)
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/* Macros to access `next_asm', `next_dis' so users needn't care about the
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underlying mechanism. */
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/* Macros to access `next_asm', `next_dis' so users needn't care about the
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underlying mechanism. */
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#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
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#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
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};
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/* this is an "insert at front" linked list per Metaware spec
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that new definitions override older ones. */
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struct arc_opcode *arc_ext_opcodes;
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struct arc_operand_value {
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char *name; /* eg: "eq" */
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short value; /* eg: 1 */
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unsigned char type; /* index into `arc_operands' */
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unsigned char flags; /* various flag bits */
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char *name; /* eg: "eq" */
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short value; /* eg: 1 */
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unsigned char type; /* index into `arc_operands' */
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unsigned char flags; /* various flag bits */
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/* Values for `flags'. */
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@ -97,18 +114,23 @@ struct arc_operand_value {
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#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
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};
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struct arc_ext_operand_value {
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struct arc_ext_operand_value *next;
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struct arc_operand_value operand;
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} *arc_ext_operands;
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struct arc_operand {
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/* One of the insn format chars. */
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/* One of the insn format chars. */
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unsigned char fmt;
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/* The number of bits in the operand (may be unused for a modifier). */
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/* The number of bits in the operand (may be unused for a modifier). */
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unsigned char bits;
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/* How far the operand is left shifted in the instruction, or
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the modifier's flag bit (may be unused for a modifier. */
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/* How far the operand is left shifted in the instruction, or
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the modifier's flag bit (may be unused for a modifier. */
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unsigned char shift;
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/* Various flag bits. */
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/* Various flag bits. */
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int flags;
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/* Values for `flags'. */
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@ -150,6 +172,19 @@ struct arc_operand {
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in special ways. */
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#define ARC_OPERAND_FAKE 0x100
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/* separate flags operand for j and jl instructions */
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#define ARC_OPERAND_JUMPFLAGS 0x200
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/* allow warnings and errors to be issued after call to insert_xxxxxx */
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#define ARC_OPERAND_WARN 0x400
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#define ARC_OPERAND_ERROR 0x800
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/* this is a load operand */
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#define ARC_OPERAND_LOAD 0x8000
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/* this is a store operand */
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#define ARC_OPERAND_STORE 0x10000
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/* Modifier values. */
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/* A dot is required before a suffix. Eg: .le */
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#define ARC_MOD_DOT 0x1000
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@ -166,52 +201,57 @@ struct arc_operand {
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/* Non-zero if the operand type is really a modifier. */
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#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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/* enforce read/write only register restrictions */
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#define ARC_REGISTER_READONLY 0x01
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#define ARC_REGISTER_WRITEONLY 0x02
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#define ARC_REGISTER_NOSHORT_CUT 0x04
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If it is NULL, execute
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i |= (p & ((1 << o->bits) - 1)) << o->shift;
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(I is the instruction which we are filling in, O is a pointer to
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this structure, and OP is the opcode value; this assumes twos
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complement arithmetic).
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged.
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If it is NULL, execute
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i |= (p & ((1 << o->bits) - 1)) << o->shift;
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(I is the instruction which we are filling in, O is a pointer to
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this structure, and OP is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged.
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REG is non-NULL when inserting a register value. */
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REG is non-NULL when inserting a register value. */
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arc_insn (*insert) PARAMS ((arc_insn insn,
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const struct arc_operand *operand, int mods,
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const struct arc_operand_value *reg, long value,
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const char **errmsg));
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & ARC_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(I is the instruction, O is a pointer to this structure, and OP
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & ARC_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(I is the instruction, O is a pointer to this structure, and OP
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is the result; this assumes twos complement arithmetic).
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INSN is a pointer to an array of two `arc_insn's. The first element is
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the insn, the second is the limm if present.
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed.
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INSN is a pointer to an array of two `arc_insn's. The first element is
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the insn, the second is the limm if present.
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Operands that have a printable form like registers and suffixes have
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their struct arc_operand_value pointer stored in OPVAL. */
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Operands that have a printable form like registers and suffixes have
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their struct arc_operand_value pointer stored in OPVAL. */
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long (*extract) PARAMS ((arc_insn *insn,
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const struct arc_operand *operand,
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@ -219,9 +259,8 @@ struct arc_operand {
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int *invalid));
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};
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/* Bits that say what version of cpu we have.
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These should be passed to arc_init_opcode_tables.
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At present, all there is is the cpu type. */
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/* Bits that say what version of cpu we have. These should be passed to
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arc_init_opcode_tables. At present, all there is is the cpu type. */
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/* CPU number, given value passed to `arc_init_opcode_tables'. */
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#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
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@ -243,16 +282,16 @@ struct arc_operand {
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#define ARC_MASK_REG 63
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/* Delay slot types. */
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#define ARC_DELAY_NONE 0 /* no delay slot */
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#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
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#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
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#define ARC_DELAY_NONE 0 /* no delay slot */
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#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
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#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
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/* Non-zero if X will fit in a signed 9 bit field. */
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#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
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extern const struct arc_operand arc_operands[];
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extern const int arc_operand_count;
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extern /*const*/ struct arc_opcode arc_opcodes[];
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extern struct arc_opcode arc_opcodes[];
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extern const int arc_opcodes_count;
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extern const struct arc_operand_value arc_suffixes[];
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extern const int arc_suffixes_count;
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@ -262,6 +301,7 @@ extern unsigned char arc_operand_map[];
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/* Utility fns in arc-opc.c. */
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int arc_get_opcode_mach PARAMS ((int, int));
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/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */
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void arc_opcode_init_tables PARAMS ((int));
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void arc_opcode_init_insert PARAMS ((void));
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@ -269,6 +309,7 @@ void arc_opcode_init_extract PARAMS ((void));
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const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
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const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
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int arc_opcode_limm_p PARAMS ((long *));
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const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value));
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const struct arc_operand_value *arc_opcode_lookup_suffix
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PARAMS ((const struct arc_operand *type, int value));
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int arc_opcode_supported PARAMS ((const struct arc_opcode *));
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int arc_opval_supported PARAMS ((const struct arc_operand_value *));
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Nick Clifton