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* libc/machine/cr16/asm.h: Added some missing instructions

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and removed few unsupported instructions of cr16 target.
This commit is contained in:
Corinna Vinschen 2012-05-21 11:55:15 +00:00
parent fe66a97ae4
commit bb39d14401
2 changed files with 168 additions and 304 deletions
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5
newlib/ChangeLog
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@ -1,3 +1,8 @@
2012-05-21 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
* libc/machine/cr16/asm.h: Added some missing instructions
and removed few unsupported instructions of cr16 target.
2012-05-10 Yaakov Selkowitz <yselkowitz@users.sourceforge.net> 2012-05-10 Yaakov Selkowitz <yselkowitz@users.sourceforge.net>
* libc/include/string.h (memrchr): Declare. * libc/include/string.h (memrchr): Declare.

339
newlib/libc/machine/cr16/sys/asm.h
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@ -1,6 +1,6 @@
/* asm.h -- CR16 architecture intrinsic functions /* asm.h -- CR16 architecture intrinsic functions
* *
* Copyright (c) 2004 National Semiconductor Corporation * Copyright (c) 2012 National Semiconductor Corporation
* *
* The authors hereby grant permission to use, copy, modify, distribute, * The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided * and license this software and its documentation for any purpose, provided
@ -20,14 +20,6 @@
the user's responsibility to use the intrinsic functions with appropriate the user's responsibility to use the intrinsic functions with appropriate
immediate values. */ immediate values. */
/* Absolute Instructions */
#define _absb_(src, dest) __asm__("absb %1, %0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _absw_(src, dest) __asm__("absw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _absd_(src, dest) __asm__("absd %1, %0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* Addition Instructions */ /* Addition Instructions */
#define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \ #define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \
"ri" ((unsigned char)src), "0" (dest) : "cc") "ri" ((unsigned char)src), "0" (dest) : "cc")
@ -38,83 +30,53 @@
#define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \ #define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \
"ri" ((unsigned short)src), "0" (dest) : "cc") "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \ #define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \
"ri" ((unsigned int)src), "0" (dest) : "cc") "ri" ((unsigned long)src), "0" (dest) : "cc")
#define _addud_(src, dest) __asm__("addud %1, %0" : "=r" (dest) : \
"ri" ((unsigned int)src), "0" (dest) : "cc")
/* Add with Carry */ /* Add with Carry */
#define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \ #define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \
"ri" ((unsigned char)src), "0" (dest) : "cc") "ri" ((unsigned char)src), "0" (dest) : "cc")
#define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \ #define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \
"ri" ((unsigned short)src), "0" (dest) : "cc") "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _addcd_(src, dest) __asm__("addcd %1, %0" : "=r" (dest) : \
"ri" ((unsigned int)src), "0" (dest) : "cc")
/* Q-format Add */
#define _addqb_(src, dest) __asm__("addqb %1, %0" : "=r" (dest) : \
"r" ((unsigned char)src), "0" (dest) : "cc")
#define _addqw_(src, dest) __asm__("addqw %1, %0" : "=r" (dest) : \
"r" ((unsigned short)src), "0" (dest) : "cc")
#define _addqd_(src, dest) __asm__("addqd %1, %0" : "=r" (dest) : \
"r" ((unsigned int)src), "0" (dest) : "cc")
/* Bitwise Logical AND */ /* Bitwise Logical AND */
#define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \ #define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest)) "ri" ((unsigned char)src) , "0" (dest))
#define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \ #define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \
"ri" ((unsigned short)src) , "0" (dest)) "ri" ((unsigned short)src) , "0" (dest))
#define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \ #define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \
"ri" ((unsigned int)src) , "0" (dest)) "ri" ((unsigned long)src) , "0" (dest))
/* Arithmetic shift Instructions */
#define _ashub_(count, dest) __asm__("ashub %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
#define _ashuw_(count, dest) __asm__("ashuw %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
#define _ashud_(count, dest) __asm__("ashud %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
/* bswap Instruction */
#define _bswap_(src, dest) __asm__("bswap %1,%0" : "=r" (dest) : \
"r" ((unsigned int)src) , "0" (dest))
/* cbit (clear bit) Instructions */ /* cbit (clear bit) Instructions */
#define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \ #define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc") "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \ #define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc") "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _cbitd_(pos, dest) __asm__("cbitd %1,%0" : "=r" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc")
/* Compare Instructions */ /* Compare Instructions */
#define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \ #define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \
"ri" ((unsigned char)src1) , "r" (src2) : "cc") "ri" ((unsigned char)src1) , "r" (src2) : "cc")
#define _cmpw_(src1,src2) __asm__("cmpw %0,%1" : /* no output */ \ #define _cmpw_(src1, src2) __asm__("cmpw %0,%1" : /* no output */ : \
: "ri" ((unsigned short)src1) , "r" (src2) : "cc") "ri" ((unsigned short)src1) , "r" (src2) : "cc")
#define _cmpd_(src1,src2) __asm__("cmpd %0,%1" : /* no output */ \ #define _cmpd_(src1, src2) __asm__("cmpd %0,%1" : /* no output */ : \
: "ri" ((unsigned int)src1) , "r" (src2) : "cc") "ri" ((unsigned long)src1) , "r" (src2) : "cc")
/* cntl Count Leading Ones Instructions */
#define _cntl1b_(src, dest) __asm__("cntl1b %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _cntl1w_(src, dest) __asm__("cntl1w %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _cntl1d_(src, dest) __asm__("cntl1d %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* cntl Count Leading Zeros Instructions */
#define _cntl0b_(src, dest) __asm__("cntl0b %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _cntl0w_(src, dest) __asm__("cntl0w %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _cntl0d_(src, dest) __asm__("cntl0d %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* cntl Count Leading Signs Instructions */
#define _cntlsb_(src, dest) __asm__("cntlsb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _cntlsw_(src, dest) __asm__("cntlsw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _cntlsd_(src, dest) __asm__("cntlsd %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* Disable Inerrupts instructions */ /* Disable Inerrupts instructions */
#define _di_() __asm__ volatile ("di\n" : : : "cc") #define _di_() __asm__ volatile ("di\n" : : : "cc")
#define _disable_() __asm__ volatile ("di\n" : : : "cc") #define _disable_() __asm__ volatile ("di\n" : : : "cc")
#define _disable_interrupt_() _di_
/* Enable Inerrupts instructions */ /* Enable Inerrupts instructions */
#define _ei_() __asm__ volatile ("ei\n" : : : "cc") #define _ei_() __asm__ volatile ("ei\n" : : : "cc")
#define _enable_() __asm__ volatile ("ei\n" : : : "cc") #define _enable_() __asm__ volatile ("ei\n" : : : "cc")
#define _enable_interrupt_() _ei_
/* Enable Inerrupts instructions and Wait */ /* Enable Inerrupts instructions and Wait */
#define _eiwait_() __asm__ volatile ("eiwait" : : : "cc") #define _eiwait_() __asm__ volatile ("eiwait" : : : "cc")
@ -122,9 +84,18 @@
/* excp Instructions */ /* excp Instructions */
#define _excp_(vector) __asm__ volatile ("excp " # vector) #define _excp_(vector) __asm__ volatile ("excp " # vector)
/* getpid Instruction */ /* lpr and lprd Instructions */
#define _getrfid_(dest) __asm__("getrfid %0" : "=r" (dest) : \ #define _lpr_(procreg, src) __asm__("lpr\t%0," procreg : \
/* No input */ : "cc") /* no output */ : "r" (src) : "cc")
#define _lprd_(procregd, src) __asm__("lprd\t%0," procregd : \
/* no output */ : "r" (src) : "cc")
/* Left Shift Instructions */
#define _lshb_(count, dest) __asm__("lshb %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
#define _lshw_(count, dest) __asm__("lshw %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
#define _lshd_(count, dest) __asm__("lshd %1,%0" : "=r" (dest) : \
"ri" ((char)count) , "0" (dest) )
/* Load Instructions */ /* Load Instructions */
#define _loadb_(base, dest) __asm__("loadb %1,%0" : "=r" (dest) : \ #define _loadb_(base, dest) __asm__("loadb %1,%0" : "=r" (dest) : \
@ -141,63 +112,15 @@
"r" ((unsigned int)src) , "i" (mask)) "r" ((unsigned int)src) , "i" (mask))
/* Multiply Accumulate Instrutions */ /* Multiply Accumulate Instrutions */
#define _macsb_(hi, lo, src1, src2) __asm__("macsb %1,%0" \
: =l (lo), =h (hi) \
: "r" ((char)src1) , "r" (src2))
#define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \ #define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \
: =l (lo), =h (hi) \ : =l (lo), =h (hi) \
: "r" ((short)src1) , "r" (src2)) : "r" ((short)src1) , "r" (src2))
#define _macsd_(hi, lo, src1, src2) __asm__("macsd %1,%0" \
: =l (lo), =h (hi) \
: "r" ((int)src1) , "r" (src2))
#define _macub_(hi, lo, src1, src2) __asm__("macub %1,%0" \
: =l (lo), =h (hi) \
:"r" ((unsigned char)src1) , "r" (src2))
#define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \ #define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \
: =l (lo), =h (hi) \ : =l (lo), =h (hi) \
: "r" ((unsigned short)src1) , "r" (src2)) : "r" ((unsigned short)src1) , "r" (src2))
#define _macud_(hi, lo, src1, src2) __asm__("macud %1,%0" \
: =l (lo), =h (hi) \
: "r" ((unsigned int)src1) , "r" (src2))
/* Q-Format Multiply Accumulate Instrutions */
#define _macqb_(src1, src2) __asm__("macqb %1,%0" \
: =l (lo), =h (hi) \
:"r" ((char)src1) , "r" (src2))
#define _macqw_(src1, src2) __asm__("macqw %1,%0" \ #define _macqw_(src1, src2) __asm__("macqw %1,%0" \
: =l (lo), =h (hi) \ : =l (lo), =h (hi) \
:"r" ((short)src1) , "r" (src2)) :"r" ((short)src1) , "r" (src2))
#define _macqd_(src1, src2) __asm__("macqd %1,%0" \
: =l (lo), =h (hi) \
:"r" ((int)src1) , "r" (src2))
/* Maximum Instructions */
#define _maxsb_(src, dest) __asm__("maxsb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _maxsw_(src, dest) __asm__("maxsw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _maxsd_(src, dest) __asm__("maxsd %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
#define _maxub_(src, dest) __asm__("maxub %1,%0" : "=r" (dest) : \
"r" ((unsigned char)src) , "0" (dest))
#define _maxuw_(src, dest) __asm__("maxuw %1,%0" : "=r" (dest) : \
"r" ((unsigned short)src) , "0" (dest))
#define _maxud_(src, dest) __asm__("maxud %1,%0" : "=r" (dest) : \
"r" ((unsigned int)src) , "0" (dest))
/* Minimum Instructions */
#define _minsb_(src, dest) __asm__("minsb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _minsw_(src, dest) __asm__("minsw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _minsd_(src, dest) __asm__("minsd %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
#define _minub_(src, dest) __asm__("minub %1,%0" : "=r" (dest) : \
"r" ((unsigned char)src) , "0" (dest))
#define _minuw_(src, dest) __asm__("minuw %1,%0" : "=r" (dest) : \
"r" ((unsigned short)src) , "0" (dest))
#define _minud_(src, dest) __asm__("minud %1,%0" : "=r" (dest) : \
"r" ((unsigned int)src) , "0" (dest))
/* Move Instructions */ /* Move Instructions */
#define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \ #define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \
@ -206,52 +129,30 @@
"ri" ((unsigned short)src) , "0" (dest)) "ri" ((unsigned short)src) , "0" (dest))
#define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \ #define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \
"ri" ((unsigned int)src) , "0" (dest)) "ri" ((unsigned int)src) , "0" (dest))
#define _movxb_(src, dest) __asm__("movxb %1,%0" : "=r" (dest) : \
/* mtpr and mfpr Insturctions */ "r" (src), "0" (dest) )
#define _mtpr_(procregd, src) __asm__("mtpr\t%0," procregd : /* no output */ : \ #define _movzb_(src, dest) __asm__("movzb %1,%0" : "=r" (dest) : \
"r" (src) : "cc") "r" (src), "0" (dest) )
#define _mfpr_(procregd, dest) __asm__("mfpr\t" procregd ",%0" : "=r" (dest) : \ #define _movxw_(src, dest) __asm__("movxw %1,%0" : "=r" (dest) : \
/* no input */ "0" (dest) : "cc") "r" (src), "0" (dest) )
#define _movzw_(src, dest) __asm__("movzw %1,%0" : "=r" (dest) : \
"r" (src), "0" (dest) )
/* Multiplication Instructions */ /* Multiplication Instructions */
#define _mulsbw_(src, dest) __asm__("mulsbw %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _mulubw_(src, dest) __asm__("mulubw %1,%0" : "=r" (dest) : \
"r" ((unsigned char)src) , "0" (dest))
#define _mulswd_(src, dest) __asm__("mulswd %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _muluwd_(src, dest) __asm__("muluwd %1,%0" : "=r" (dest) : \
"r" ((unsigned short)src) , "0" (dest))
#define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \ #define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \
"ri" ((char)src) , "0" (dest)) "ri" ((char)src) , "0" (dest))
#define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \ #define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \
"ri" ((short)src) , "0" (dest)) "ri" ((short)src) , "0" (dest))
#define _muld_(src, dest) __asm__("muld %1,%0" : "=r" (dest) : \ #define _mulsb_(src, dest) __asm__("mulsb %1,%0" : "=r" (dest) : \
"ri" ((int)src) , "0" (dest))
#define _mullsd_(hi, lo, src1, src2) __asm__("mullsd %2,%3" \
: =l (lo), =h (hi) \
: "r" ((unsigned int)src1) , "r" ((unsigned int)src2))
#define _mullud_(hi, lo, src1, src2) __asm__("mullud %2,%3" \
: =l (lo), =h (hi) \
: "r" ((int)src1) , "r" ((int)src2))
/* Q-Format Multiplication Instructions */
#define _mulqb_(src, dest) __asm__("mulqb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest)) "r" ((char)src) , "0" (dest))
#define _mulqw_(src, dest) __asm__("mulqw %1,%0" : "=r" (dest) : \ #define _mulsw_(src, dest) __asm__("mulsw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest)) "r" ((short)src) , "0" (dest))
#define _muluw_(src, dest) __asm__("muluw %1,%0" : "=r" (dest) : \
"r" ((unsigned short)src) , "0" (dest))
/* nop Instruction */ /* nop Instruction */
#define _nop_() __asm__("nop") #define _nop_() __asm__("nop")
/* Negate Instructions */
#define _negb_(src, dest) __asm__("negb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _negw_(src, dest) __asm__("negw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _negd_(src, dest) __asm__("negd %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* or Instructions */ /* or Instructions */
#define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \ #define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest)) "ri" ((unsigned char)src) , "0" (dest))
@ -260,91 +161,20 @@
#define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \ #define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \
"ri" ((unsigned int)src) , "0" (dest)) "ri" ((unsigned int)src) , "0" (dest))
/* Pop 1's Count Instructions */
#define _popcntb_(src, dest) __asm__("popcntb %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _popcntw_(src, dest) __asm__("popcntw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _popcntd_(src, dest) __asm__("popcntd %1,%0" : "=r" (dest) : \
"r" ((int)src) , "0" (dest))
/* Rotate and Mask Instructions */
#define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \
"=r" (dest) : \
"i" ((unsigned char) shift), \
"i" (end), "i" (begin), \
"r" (src), "0" (dest))
#define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \
"=r" (dest) : \
"i" ((unsigned char) shift), \
"i" (end), "i" (begin), \
"r" (src), "0" (dest))
/* retx Instruction */ /* retx Instruction */
#define _retx_() __asm__("retx") #define _retx_() __asm__("retx")
/* Rotate Instructions */
#define _rotb_(shift, dest) __asm__("rotb %1,%0" : "=r" (dest) : \
"i" ((unsigned char)shift) , "0" (dest))
#define _rotw_(shift, dest) __asm__("rotw %1,%0" : "=r" (dest) : \
"i" ((unsigned char)shift) , "0" (dest))
#define _rotd_(shift, dest) __asm__("rotd %1,%0" : "=r" (dest) : \
"i" ((unsigned char)shift) , "0" (dest))
#define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
#define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
#define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
#define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
#define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
#define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest) : \
"r" ((unsigned char)shift) , "0" (dest))
/* Set Bit Instructions */ /* Set Bit Instructions */
#define _sbitb_(pos, dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \ #define _sbitb_(pos, dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc") "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _sbitw_(pos, dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \ #define _sbitw_(pos, dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc") "i" ((unsigned char)pos) , "0" (dest) : "cc")
#define _sbitd_(pos,dest) __asm__("sbitd %1,%0" : "=mr" (dest) : \
"i" ((unsigned char)pos) , "0" (dest) : "cc")
/* setrfid Instruction */ /* spr and sprd Instructions */
#define _setrfid_(src) __asm__("setrfid %0" : /* No output */ : \ #define _spr_(procreg, dest) __asm__("spr\t" procreg ",%0" : \
"r" (src) : "cc") "=r" (dest) : /* no input */ "0" (dest) : "cc")
#define _sprd_(procregd, dest) __asm__("sprd\t" procregd ",%0" : \
/* Sign Extend Instructions */ "=r" (dest) : /* no input */ "0" (dest) : "cc")
#define _sextbw_(src, dest) __asm__("sextbw %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest) )
#define _sextbd_(src, dest) __asm__("sextbd %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest) )
#define _sextwd_(src, dest) __asm__("sextwd %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest) )
/* Shift Left Logical Instructions */
#define _sllb_(src, dest) __asm__("sllb %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _sllw_(src, dest) __asm__("sllw %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _slld_(src, dest) __asm__("slld %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
/* Shift Right Arithmetic Instructions */
#define _srab_(src, dest) __asm__("srab %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _sraw_(src, dest) __asm__("sraw %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _srad_(src, dest) __asm__("srad %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
/* Shift Right Logical Instructions */
#define _srlb_(src, dest) __asm__("srlb %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _srlw_(src, dest) __asm__("srlw %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
#define _srld_(src, dest) __asm__("srld %1,%0" : "=r" (dest) : \
"ri" ((unsigned char)src) , "0" (dest))
/* Store Instructions */ /* Store Instructions */
#define _storb_(src, address) __asm__("storb %1,%0" : "=m" (address) : \ #define _storb_(src, address) __asm__("storb %1,%0" : "=m" (address) : \
@ -366,31 +196,21 @@
#define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \ #define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \
"ri" ((unsigned short)src), "0" (dest) : "cc") "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \ #define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \
"ri" ((unsigned int)src), "0" (dest) : "cc") "ri" ((unsigned long)src), "0" (dest) : "cc")
/* Substruct with Carry Instructions */ /* Substruct with Carry Instructions */
#define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \ #define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \
"ri" ((unsigned char)src), "0" (dest) : "cc") "ri" ((unsigned char)src), "0" (dest) : "cc")
#define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \ #define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \
"ri" ((unsigned short)src), "0" (dest) : "cc") "ri" ((unsigned short)src), "0" (dest) : "cc")
#define _subcd_(src, dest) __asm__("subcd %1, %0" : "=r" (dest) : \
"ri" ((unsigned int)src), "0" (dest) : "cc")
/* Q-Format Substruct Instructions */
#define _subqb_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
"r" ((char)src) , "0" (dest))
#define _subqw_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
#define _subqd_(src, dest) __asm__("subqd %1,%0" : "=r" (dest) : \
"r" ((short)src) , "0" (dest))
/* Test Bit Instructions */ /* Test Bit Instructions */
#define _tbit_(offset, base) __asm__("tbit %0,%1" : /* no output */ : \
"ri" ((unsigned char)offset) , "r" (base) : "cc")
#define _tbitb_(pos, dest) __asm__("tbitb %0,%1" : /* No output */ : \ #define _tbitb_(pos, dest) __asm__("tbitb %0,%1" : /* No output */ : \
"i" ((unsigned char)pos) , "rm" (dest) : "cc") "i" ((unsigned char)pos) , "m" (dest) : "cc")
#define _tbitw_(pos, dest) __asm__("tbitw %0,%1" : /* No output */ : \ #define _tbitw_(pos, dest) __asm__("tbitw %0,%1" : /* No output */ : \
"i" ((unsigned char)pos) , "rm" (dest) : "cc") "i" ((unsigned char)pos) , "m" (dest) : "cc")
#define _tbitd_(pos,dest) __asm__("tbitd %0,%1" : /* No output */ : \
"i" ((unsigned char)pos) , "rm" (dest) : "cc")
/* wait Instruction*/ /* wait Instruction*/
#define _wait_() __asm__ volatile ("wait" : : : "cc") #define _wait_() __asm__ volatile ("wait" : : : "cc")
@ -401,15 +221,53 @@
#define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \ #define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \
"ri" ((unsigned short)src) , "0" (dest)) "ri" ((unsigned short)src) , "0" (dest))
#define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \ #define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \
"ri" ((unsigned int)src) , "0" (dest)) "ri" ((unsigned long)src) , "0" (dest))
/* Zero Extend Instructions */ #if !defined (__CR16C__)
#define _zextbw_(src, dest) __asm__("zextbw %1,%0" : "=r" (dest) : \ #define _di_() __asm__ volatile ("di\n" : : : "cc")
"r" ((unsigned char)src) , "0" (dest)) #else
#define _zextbd_(src, dest) __asm__("zextbd %1,%0" : "=r" (dest) : \ /* In CR16C architecture the "nop" instruction is required after the di instruction
"r" ((unsigned char)src) , "0" (dest)) in order to be sure the interrupts are indeed disabled.
#define _zextwd_(src, dest) __asm__("zextwd %1,%0" : "=r" (dest) : \ For details, refer the the CR16C Programmers Reference Manual. */
"r" ((unsigned short)src) , "0" (dest)) #define _di_() __asm__ volatile ("di\n\tnop" : : : "cc")
#endif
/* mtgpr Instruction */
#define _mtgpr_(src, gpr) \
__asm__ volatile ("movd\t%[_src], " gpr : /* no output */ \
: [_src] "ri" (src) \
: gpr )
/* mfgpr Instruction */
#define _mfgpr_(gpr, dest) \
__asm__ volatile ("movd\t" gpr ", %[_dest]" : [_dest] "=r" (dest) \
: /* no inputs */ )
/* set_i_bit Operation Definition */
#define set_i_bit() \
do \
{ \
unsigned short tpsr; \
_spr_("psr", tpsr); \
tpsr |= 0x0800; \
_lpr_("psr",tpsr); \
} while(0)
/* set_i_bit Macro Definition */
#define _enable_global_interrupt_ set_i_bit
/* clear_i_bit Operation Definition */
#define clear_i_bit() \
do \
{ \
unsigned short tpsr; \
_spr_("psr", tpsr); \
tpsr &= 0xf7ff; \
_lpr_("psr",tpsr); \
} while(0)
/* clear_i_bit Macro Definition */
#define _disbale_global_interrupt_ clear_i_bit
#define _save_asm_(x) \ #define _save_asm_(x) \
__asm__ volatile (x ::: "memory","cc", \ __asm__ volatile (x ::: "memory","cc", \
@ -419,3 +277,4 @@
#endif /* _ASM */ #endif /* _ASM */