* libc/machine/cr16/asm.h: Added some missing instructions
and removed few unsupported instructions of cr16 target.
This commit is contained in:
Corinna Vinschen
parent
fe66a97ae4
commit
bb39d14401
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@ -1,3 +1,8 @@
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2012-05-21 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
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* libc/machine/cr16/asm.h: Added some missing instructions
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and removed few unsupported instructions of cr16 target.
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2012-05-10 Yaakov Selkowitz <yselkowitz@users.sourceforge.net>
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* libc/include/string.h (memrchr): Declare.
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@ -1,6 +1,6 @@
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/* asm.h -- CR16 architecture intrinsic functions
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*
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* Copyright (c) 2004 National Semiconductor Corporation
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* Copyright (c) 2012 National Semiconductor Corporation
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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@ -20,14 +20,6 @@
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the user's responsibility to use the intrinsic functions with appropriate
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immediate values. */
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/* Absolute Instructions */
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#define _absb_(src, dest) __asm__("absb %1, %0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _absw_(src, dest) __asm__("absw %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _absd_(src, dest) __asm__("absd %1, %0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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/* Addition Instructions */
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#define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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@ -38,166 +30,97 @@
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#define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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#define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \
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"ri" ((unsigned int)src), "0" (dest) : "cc")
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#define _addud_(src, dest) __asm__("addud %1, %0" : "=r" (dest) : \
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"ri" ((unsigned int)src), "0" (dest) : "cc")
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"ri" ((unsigned long)src), "0" (dest) : "cc")
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/* Add with Carry */
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#define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \
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"ri" ((unsigned char)src), "0" (dest) : "cc")
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#define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \
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"ri" ((unsigned short)src), "0" (dest) : "cc")
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#define _addcd_(src, dest) __asm__("addcd %1, %0" : "=r" (dest) : \
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"ri" ((unsigned int)src), "0" (dest) : "cc")
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/* Q-format Add */
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#define _addqb_(src, dest) __asm__("addqb %1, %0" : "=r" (dest) : \
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"r" ((unsigned char)src), "0" (dest) : "cc")
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#define _addqw_(src, dest) __asm__("addqw %1, %0" : "=r" (dest) : \
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"r" ((unsigned short)src), "0" (dest) : "cc")
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#define _addqd_(src, dest) __asm__("addqd %1, %0" : "=r" (dest) : \
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"r" ((unsigned int)src), "0" (dest) : "cc")
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/* Bitwise Logical AND */
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#define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \
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"ri" ((unsigned long)src) , "0" (dest))
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#define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned char)src) , "0" (dest))
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#define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \
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"ri" ((unsigned int)src) , "0" (dest))
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/* Arithmetic shift Instructions */
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#define _ashub_(count, dest) __asm__("ashub %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _ashuw_(count, dest) __asm__("ashuw %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _ashud_(count, dest) __asm__("ashud %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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/* bswap Instruction */
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#define _bswap_(src, dest) __asm__("bswap %1,%0" : "=r" (dest) : \
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"r" ((unsigned int)src) , "0" (dest))
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/* cbit (clear bit) Instructions */
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#define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _cbitd_(pos, dest) __asm__("cbitd %1,%0" : "=r" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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#define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \
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"i" ((unsigned char)pos) , "0" (dest) : "cc")
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/* Compare Instructions */
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#define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \
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"ri" ((unsigned char)src1) , "r" (src2) : "cc")
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#define _cmpw_(src1,src2) __asm__("cmpw %0,%1" : /* no output */ \
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: "ri" ((unsigned short)src1) , "r" (src2) : "cc")
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#define _cmpd_(src1,src2) __asm__("cmpd %0,%1" : /* no output */ \
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: "ri" ((unsigned int)src1) , "r" (src2) : "cc")
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/* cntl Count Leading Ones Instructions */
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#define _cntl1b_(src, dest) __asm__("cntl1b %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _cntl1w_(src, dest) __asm__("cntl1w %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _cntl1d_(src, dest) __asm__("cntl1d %1,%0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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/* cntl Count Leading Zeros Instructions */
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#define _cntl0b_(src, dest) __asm__("cntl0b %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _cntl0w_(src, dest) __asm__("cntl0w %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _cntl0d_(src, dest) __asm__("cntl0d %1,%0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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/* cntl Count Leading Signs Instructions */
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#define _cntlsb_(src, dest) __asm__("cntlsb %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _cntlsw_(src, dest) __asm__("cntlsw %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _cntlsd_(src, dest) __asm__("cntlsd %1,%0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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#define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \
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"ri" ((unsigned char)src1) , "r" (src2) : "cc")
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#define _cmpw_(src1, src2) __asm__("cmpw %0,%1" : /* no output */ : \
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"ri" ((unsigned short)src1) , "r" (src2) : "cc")
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#define _cmpd_(src1, src2) __asm__("cmpd %0,%1" : /* no output */ : \
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"ri" ((unsigned long)src1) , "r" (src2) : "cc")
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/* Disable Inerrupts instructions */
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#define _di_() __asm__ volatile ("di\n" : : : "cc")
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#define _disable_() __asm__ volatile ("di\n" : : : "cc")
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#define _di_() __asm__ volatile ("di\n" : : : "cc")
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#define _disable_() __asm__ volatile ("di\n" : : : "cc")
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#define _disable_interrupt_() _di_
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/* Enable Inerrupts instructions */
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#define _ei_() __asm__ volatile ("ei\n" : : : "cc")
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#define _enable_() __asm__ volatile ("ei\n" : : : "cc")
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#define _ei_() __asm__ volatile ("ei\n" : : : "cc")
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#define _enable_() __asm__ volatile ("ei\n" : : : "cc")
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#define _enable_interrupt_() _ei_
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/* Enable Inerrupts instructions and Wait */
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#define _eiwait_() __asm__ volatile ("eiwait" : : : "cc")
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#define _eiwait_() __asm__ volatile ("eiwait" : : : "cc")
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/* excp Instructions */
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#define _excp_(vector) __asm__ volatile ("excp " # vector)
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/* getpid Instruction */
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#define _getrfid_(dest) __asm__("getrfid %0" : "=r" (dest) : \
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/* No input */ : "cc")
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#define _excp_(vector) __asm__ volatile ("excp " # vector)
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/* lpr and lprd Instructions */
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#define _lpr_(procreg, src) __asm__("lpr\t%0," procreg : \
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/* no output */ : "r" (src) : "cc")
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#define _lprd_(procregd, src) __asm__("lprd\t%0," procregd : \
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/* no output */ : "r" (src) : "cc")
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/* Left Shift Instructions */
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#define _lshb_(count, dest) __asm__("lshb %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _lshw_(count, dest) __asm__("lshw %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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#define _lshd_(count, dest) __asm__("lshd %1,%0" : "=r" (dest) : \
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"ri" ((char)count) , "0" (dest) )
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/* Load Instructions */
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#define _loadb_(base,dest) __asm__("loadb %1,%0" : "=r" (dest) : \
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#define _loadb_(base, dest) __asm__("loadb %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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#define _loadw_(base,dest) __asm__("loadw %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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#define _loadd_(base,dest) __asm__("loadd %1,%0" : "=r" (dest) : \
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#define _loadw_(base, dest) __asm__("loadw %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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#define _loadd_(base, dest) __asm__("loadd %1,%0" : "=r" (dest) : \
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"m" (base) , "0" (dest))
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/* Load Multiple Instructions */
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#define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \
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#define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \
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"r" ((unsigned int)src) , "i" (mask))
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#define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \
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#define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \
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"r" ((unsigned int)src) , "i" (mask))
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/* Multiply Accumulate Instrutions */
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#define _macsb_(hi, lo, src1, src2) __asm__("macsb %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((char)src1) , "r" (src2))
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#define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((short)src1) , "r" (src2))
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#define _macsd_(hi, lo, src1, src2) __asm__("macsd %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((int)src1) , "r" (src2))
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#define _macub_(hi, lo, src1, src2) __asm__("macub %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((unsigned char)src1) , "r" (src2))
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#define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((unsigned short)src1) , "r" (src2))
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#define _macud_(hi, lo, src1, src2) __asm__("macud %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((unsigned int)src1) , "r" (src2))
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/* Q-Format Multiply Accumulate Instrutions */
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#define _macqb_(src1, src2) __asm__("macqb %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((char)src1) , "r" (src2))
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#define _macqw_(src1, src2) __asm__("macqw %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((short)src1) , "r" (src2))
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#define _macqd_(src1, src2) __asm__("macqd %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((int)src1) , "r" (src2))
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/* Maximum Instructions */
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#define _maxsb_(src, dest) __asm__("maxsb %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _maxsw_(src, dest) __asm__("maxsw %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _maxsd_(src, dest) __asm__("maxsd %1,%0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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#define _maxub_(src, dest) __asm__("maxub %1,%0" : "=r" (dest) : \
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"r" ((unsigned char)src) , "0" (dest))
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#define _maxuw_(src, dest) __asm__("maxuw %1,%0" : "=r" (dest) : \
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"r" ((unsigned short)src) , "0" (dest))
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#define _maxud_(src, dest) __asm__("maxud %1,%0" : "=r" (dest) : \
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"r" ((unsigned int)src) , "0" (dest))
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/* Minimum Instructions */
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#define _minsb_(src, dest) __asm__("minsb %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _minsw_(src, dest) __asm__("minsw %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _minsd_(src, dest) __asm__("minsd %1,%0" : "=r" (dest) : \
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"r" ((int)src) , "0" (dest))
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#define _minub_(src, dest) __asm__("minub %1,%0" : "=r" (dest) : \
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"r" ((unsigned char)src) , "0" (dest))
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#define _minuw_(src, dest) __asm__("minuw %1,%0" : "=r" (dest) : \
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"r" ((unsigned short)src) , "0" (dest))
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#define _minud_(src, dest) __asm__("minud %1,%0" : "=r" (dest) : \
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"r" ((unsigned int)src) , "0" (dest))
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#define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((short)src1) , "r" (src2))
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#define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \
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: =l (lo), =h (hi) \
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: "r" ((unsigned short)src1) , "r" (src2))
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#define _macqw_(src1, src2) __asm__("macqw %1,%0" \
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: =l (lo), =h (hi) \
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:"r" ((short)src1) , "r" (src2))
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/* Move Instructions */
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#define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \
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"ri" ((unsigned short)src) , "0" (dest))
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#define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \
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"ri" ((unsigned int)src) , "0" (dest))
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/* mtpr and mfpr Insturctions */
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#define _mtpr_(procregd, src) __asm__("mtpr\t%0," procregd : /* no output */ : \
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"r" (src) : "cc")
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#define _mfpr_(procregd, dest) __asm__("mfpr\t" procregd ",%0" : "=r" (dest) : \
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/* no input */ "0" (dest) : "cc")
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#define _movxb_(src, dest) __asm__("movxb %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movzb_(src, dest) __asm__("movzb %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movxw_(src, dest) __asm__("movxw %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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#define _movzw_(src, dest) __asm__("movzw %1,%0" : "=r" (dest) : \
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"r" (src), "0" (dest) )
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/* Multiplication Instructions */
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#define _mulsbw_(src, dest) __asm__("mulsbw %1,%0" : "=r" (dest) : \
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"r" ((char)src) , "0" (dest))
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#define _mulubw_(src, dest) __asm__("mulubw %1,%0" : "=r" (dest) : \
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"r" ((unsigned char)src) , "0" (dest))
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#define _mulswd_(src, dest) __asm__("mulswd %1,%0" : "=r" (dest) : \
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"r" ((short)src) , "0" (dest))
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#define _muluwd_(src, dest) __asm__("muluwd %1,%0" : "=r" (dest) : \
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"r" ((unsigned short)src) , "0" (dest))
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#define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \
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"ri" ((char)src) , "0" (dest))
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#define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \
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"ri" ((short)src) , "0" (dest))
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#define _muld_(src, dest) __asm__("muld %1,%0" : "=r" (dest) : \
|
||||
"ri" ((int)src) , "0" (dest))
|
||||
#define _mullsd_(hi, lo, src1, src2) __asm__("mullsd %2,%3" \
|
||||
: =l (lo), =h (hi) \
|
||||
: "r" ((unsigned int)src1) , "r" ((unsigned int)src2))
|
||||
#define _mullud_(hi, lo, src1, src2) __asm__("mullud %2,%3" \
|
||||
: =l (lo), =h (hi) \
|
||||
: "r" ((int)src1) , "r" ((int)src2))
|
||||
|
||||
/* Q-Format Multiplication Instructions */
|
||||
#define _mulqb_(src, dest) __asm__("mulqb %1,%0" : "=r" (dest) : \
|
||||
#define _mulsb_(src, dest) __asm__("mulsb %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest))
|
||||
#define _mulqw_(src, dest) __asm__("mulqw %1,%0" : "=r" (dest) : \
|
||||
#define _mulsw_(src, dest) __asm__("mulsw %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest))
|
||||
#define _muluw_(src, dest) __asm__("muluw %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned short)src) , "0" (dest))
|
||||
|
||||
/* nop Instruction */
|
||||
#define _nop_() __asm__("nop")
|
||||
|
||||
/* Negate Instructions */
|
||||
#define _negb_(src, dest) __asm__("negb %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest))
|
||||
#define _negw_(src, dest) __asm__("negw %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest))
|
||||
#define _negd_(src, dest) __asm__("negd %1,%0" : "=r" (dest) : \
|
||||
"r" ((int)src) , "0" (dest))
|
||||
#define _nop_() __asm__("nop")
|
||||
|
||||
/* or Instructions */
|
||||
#define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _orw_(src, dest) __asm__("orw %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src) , "0" (dest))
|
||||
"ri" ((unsigned short)src) , "0" (dest))
|
||||
#define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned int)src) , "0" (dest))
|
||||
|
||||
/* Pop 1's Count Instructions */
|
||||
#define _popcntb_(src, dest) __asm__("popcntb %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest))
|
||||
#define _popcntw_(src, dest) __asm__("popcntw %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest))
|
||||
#define _popcntd_(src, dest) __asm__("popcntd %1,%0" : "=r" (dest) : \
|
||||
"r" ((int)src) , "0" (dest))
|
||||
|
||||
/* Rotate and Mask Instructions */
|
||||
#define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \
|
||||
"=r" (dest) : \
|
||||
"i" ((unsigned char) shift), \
|
||||
"i" (end), "i" (begin), \
|
||||
"r" (src), "0" (dest))
|
||||
#define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \
|
||||
"=r" (dest) : \
|
||||
"i" ((unsigned char) shift), \
|
||||
"i" (end), "i" (begin), \
|
||||
"r" (src), "0" (dest))
|
||||
"ri" ((unsigned int)src) , "0" (dest))
|
||||
|
||||
/* retx Instruction */
|
||||
#define _retx_() __asm__("retx")
|
||||
|
||||
/* Rotate Instructions */
|
||||
#define _rotb_(shift, dest) __asm__("rotb %1,%0" : "=r" (dest) : \
|
||||
"i" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotw_(shift, dest) __asm__("rotw %1,%0" : "=r" (dest) : \
|
||||
"i" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotd_(shift, dest) __asm__("rotd %1,%0" : "=r" (dest) : \
|
||||
"i" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)shift) , "0" (dest))
|
||||
#define _retx_() __asm__("retx")
|
||||
|
||||
/* Set Bit Instructions */
|
||||
#define _sbitb_(pos,dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \
|
||||
"i" ((unsigned char)pos) , "0" (dest) : "cc")
|
||||
#define _sbitw_(pos,dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \
|
||||
"i" ((unsigned char)pos) , "0" (dest) : "cc")
|
||||
#define _sbitd_(pos,dest) __asm__("sbitd %1,%0" : "=mr" (dest) : \
|
||||
"i" ((unsigned char)pos) , "0" (dest) : "cc")
|
||||
#define _sbitb_(pos, dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \
|
||||
"i" ((unsigned char)pos) , "0" (dest) : "cc")
|
||||
#define _sbitw_(pos, dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \
|
||||
"i" ((unsigned char)pos) , "0" (dest) : "cc")
|
||||
|
||||
/* setrfid Instruction */
|
||||
#define _setrfid_(src) __asm__("setrfid %0" : /* No output */ : \
|
||||
"r" (src) : "cc")
|
||||
/* spr and sprd Instructions */
|
||||
#define _spr_(procreg, dest) __asm__("spr\t" procreg ",%0" : \
|
||||
"=r" (dest) : /* no input */ "0" (dest) : "cc")
|
||||
#define _sprd_(procregd, dest) __asm__("sprd\t" procregd ",%0" : \
|
||||
"=r" (dest) : /* no input */ "0" (dest) : "cc")
|
||||
|
||||
/* Sign Extend Instructions */
|
||||
#define _sextbw_(src, dest) __asm__("sextbw %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest) )
|
||||
#define _sextbd_(src, dest) __asm__("sextbd %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest) )
|
||||
#define _sextwd_(src, dest) __asm__("sextwd %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest) )
|
||||
|
||||
/* Shift Left Logical Instructions */
|
||||
#define _sllb_(src, dest) __asm__("sllb %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _sllw_(src, dest) __asm__("sllw %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _slld_(src, dest) __asm__("slld %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
/* Shift Right Arithmetic Instructions */
|
||||
#define _srab_(src, dest) __asm__("srab %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _sraw_(src, dest) __asm__("sraw %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _srad_(src, dest) __asm__("srad %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
|
||||
/* Shift Right Logical Instructions */
|
||||
#define _srlb_(src, dest) __asm__("srlb %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _srlw_(src, dest) __asm__("srlw %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _srld_(src, dest) __asm__("srld %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
|
||||
/* Store Instructions */
|
||||
#define _storb_(src,address) __asm__("storb %1,%0" : "=m" (address) : \
|
||||
#define _storb_(src, address) __asm__("storb %1,%0" : "=m" (address) : \
|
||||
"ri" ((unsigned int)src))
|
||||
#define _storw_(src,address) __asm__("storw %1,%0" : "=m" (address) : \
|
||||
#define _storw_(src, address) __asm__("storw %1,%0" : "=m" (address) : \
|
||||
"ri" ((unsigned int)src))
|
||||
#define _stord_(src,address) __asm__("stord %1,%0" : "=m" (address) : \
|
||||
#define _stord_(src, address) __asm__("stord %1,%0" : "=m" (address) : \
|
||||
"ri" ((unsigned int)src))
|
||||
|
||||
/* Store Multiple Instructions */
|
||||
|
|
@ -361,61 +191,90 @@
|
|||
"i" (mask) , "r" ((unsigned int)src))
|
||||
|
||||
/* Substruct Instructions */
|
||||
#define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src), "0" (dest) : "cc")
|
||||
#define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src), "0" (dest) : "cc")
|
||||
#define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned int)src), "0" (dest) : "cc")
|
||||
#define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src), "0" (dest) : "cc")
|
||||
#define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src), "0" (dest) : "cc")
|
||||
#define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned long)src), "0" (dest) : "cc")
|
||||
|
||||
/* Substruct with Carry Instructions */
|
||||
#define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src), "0" (dest) : "cc")
|
||||
#define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src), "0" (dest) : "cc")
|
||||
#define _subcd_(src, dest) __asm__("subcd %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned int)src), "0" (dest) : "cc")
|
||||
|
||||
/* Q-Format Substruct Instructions */
|
||||
#define _subqb_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
|
||||
"r" ((char)src) , "0" (dest))
|
||||
#define _subqw_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest))
|
||||
#define _subqd_(src, dest) __asm__("subqd %1,%0" : "=r" (dest) : \
|
||||
"r" ((short)src) , "0" (dest))
|
||||
|
||||
#define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src), "0" (dest) : "cc")
|
||||
#define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src), "0" (dest) : "cc")
|
||||
|
||||
/* Test Bit Instructions */
|
||||
#define _tbitb_(pos,dest) __asm__("tbitb %0,%1" : /* No output */ : \
|
||||
"i" ((unsigned char)pos) , "rm" (dest) : "cc")
|
||||
#define _tbitw_(pos,dest) __asm__("tbitw %0,%1" : /* No output */ : \
|
||||
"i" ((unsigned char)pos) , "rm" (dest) : "cc")
|
||||
#define _tbitd_(pos,dest) __asm__("tbitd %0,%1" : /* No output */ : \
|
||||
"i" ((unsigned char)pos) , "rm" (dest) : "cc")
|
||||
#define _tbit_(offset, base) __asm__("tbit %0,%1" : /* no output */ : \
|
||||
"ri" ((unsigned char)offset) , "r" (base) : "cc")
|
||||
#define _tbitb_(pos, dest) __asm__("tbitb %0,%1" : /* No output */ : \
|
||||
"i" ((unsigned char)pos) , "m" (dest) : "cc")
|
||||
#define _tbitw_(pos, dest) __asm__("tbitw %0,%1" : /* No output */ : \
|
||||
"i" ((unsigned char)pos) , "m" (dest) : "cc")
|
||||
|
||||
/* wait Instruction*/
|
||||
#define _wait_() __asm__ volatile ("wait" : : : "cc")
|
||||
|
||||
/* xor Instructions */
|
||||
#define _xorb_(src, dest) __asm__("xorb %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
"ri" ((unsigned char)src) , "0" (dest))
|
||||
#define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned short)src) , "0" (dest))
|
||||
"ri" ((unsigned short)src) , "0" (dest))
|
||||
#define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \
|
||||
"ri" ((unsigned int)src) , "0" (dest))
|
||||
"ri" ((unsigned long)src) , "0" (dest))
|
||||
|
||||
/* Zero Extend Instructions */
|
||||
#define _zextbw_(src, dest) __asm__("zextbw %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)src) , "0" (dest))
|
||||
#define _zextbd_(src, dest) __asm__("zextbd %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned char)src) , "0" (dest))
|
||||
#define _zextwd_(src, dest) __asm__("zextwd %1,%0" : "=r" (dest) : \
|
||||
"r" ((unsigned short)src) , "0" (dest))
|
||||
#if !defined (__CR16C__)
|
||||
#define _di_() __asm__ volatile ("di\n" : : : "cc")
|
||||
#else
|
||||
/* In CR16C architecture the "nop" instruction is required after the di instruction
|
||||
in order to be sure the interrupts are indeed disabled.
|
||||
For details, refer the the CR16C Programmers Reference Manual. */
|
||||
#define _di_() __asm__ volatile ("di\n\tnop" : : : "cc")
|
||||
#endif
|
||||
|
||||
/* mtgpr Instruction */
|
||||
#define _mtgpr_(src, gpr) \
|
||||
__asm__ volatile ("movd\t%[_src], " gpr : /* no output */ \
|
||||
: [_src] "ri" (src) \
|
||||
: gpr )
|
||||
|
||||
#define _save_asm_(x) \
|
||||
__asm__ volatile (x ::: "memory","cc", \
|
||||
"r0","r1","r2","r3","r4","r5","r6","r7", \
|
||||
/* mfgpr Instruction */
|
||||
#define _mfgpr_(gpr, dest) \
|
||||
__asm__ volatile ("movd\t" gpr ", %[_dest]" : [_dest] "=r" (dest) \
|
||||
: /* no inputs */ )
|
||||
|
||||
/* set_i_bit Operation Definition */
|
||||
#define set_i_bit() \
|
||||
do \
|
||||
{ \
|
||||
unsigned short tpsr; \
|
||||
_spr_("psr", tpsr); \
|
||||
tpsr |= 0x0800; \
|
||||
_lpr_("psr",tpsr); \
|
||||
} while(0)
|
||||
|
||||
/* set_i_bit Macro Definition */
|
||||
#define _enable_global_interrupt_ set_i_bit
|
||||
|
||||
/* clear_i_bit Operation Definition */
|
||||
#define clear_i_bit() \
|
||||
do \
|
||||
{ \
|
||||
unsigned short tpsr; \
|
||||
_spr_("psr", tpsr); \
|
||||
tpsr &= 0xf7ff; \
|
||||
_lpr_("psr",tpsr); \
|
||||
} while(0)
|
||||
|
||||
/* clear_i_bit Macro Definition */
|
||||
#define _disbale_global_interrupt_ clear_i_bit
|
||||
|
||||
#define _save_asm_(x) \
|
||||
__asm__ volatile (x ::: "memory","cc", \
|
||||
"r0","r1","r2","r3","r4","r5","r6","r7", \
|
||||
"r8","r9","r10","r11","r12","r13")
|
||||
|
||||
#endif /* _ASM */
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue