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include/opcode/

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* ppc.h (PPC_OPCODE_405): Define.
	(PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
gas/
	* config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.
	(md_show_usage): Likewise.
opcodes/
	* ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
	* ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
	(insert_sprg, PPC405): Use PPC_OPCODE_405.
	(powerpc_opcodes): Add Xilinx APU related opcodes.
This commit is contained in:
Alan Modra 2008-07-30 06:29:21 +00:00
parent e3e942ac00
commit 79ea8bbb10
2 changed files with 13 additions and 0 deletions
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5
include/opcode/ChangeLog
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@ -1,3 +1,8 @@
2008-07-30 Michael J. Eager <eager@eagercon.com>
* ppc.h (PPC_OPCODE_405): Define.
(PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
* ppc.h (ppc_cpu_t): New typedef.

8
include/opcode/ppc.h
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@ -154,6 +154,9 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC 0x20000000
/* Opcode is supported by PowerPC 405 processor. */
#define PPC_OPCODE_405 0x40000000
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@ -304,6 +307,11 @@ extern const unsigned int num_powerpc_operands;
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
/* Xilinx APU and FSL related operands */
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an