bfd
* Makefile.am (ALL_MACHINES): Add cpu-rx.lo.
(ALL_MACHINES_CFILES): Add cpu-rx.c.
(BFD32_BACKENDS): Add elf32-rx.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rx.c.
* archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx.
Export bfd_rx_arch.
(bfd_archures_list): Add bfd_rx_arch.
* config.bfd: Add entry for rx-*-elf.
* configure.in: Add entries for bfd_elf32_rx_le_vec and
bfd_elf32_rx_be_vec.
* reloc.c: Add RX relocations.
* targets.c: Add RX target vectors.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rx.c: New file.
* elf32-rx.c: New file.
binutils
* readelf.c: Add support for RX target.
* MAINTAINERS: Add DJ and NickC as maintainers for RX.
gas
* Makefile.am: Add RX target.
* configure.in: Likewise.
* configure.tgt: Likewise.
* read.c (do_repeat_with_expander): New function.
* read.h: Provide a prototype for do_repeat_with_expander.
* doc/Makefile.am: Add RX target documentation.
* doc/all.texi: Likewise.
* doc/as.texinfo: Likewise.
* Makefile.in: Regenerate.
* NEWS: Mention support for RX architecture.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* config/rx-defs.h: New file.
* config/rx-parse.y: New file.
* config/tc-rx.h: New file.
* config/tc-rx.c: New file.
* doc/c-rx.texi: New file.
gas/testsuite
* gas/rx: New directory.
* gas/rx/*: New set of test cases.
* gas/elf/section2.e-rx: New expected output file.
* gas/all/gas.exp: Add support for RX target.
* gas/elf/elf.exp: Likewise.
* gas/lns/lns.exp: Likewise.
* gas/macros/macros.exp: Likewise.
include
* dis-asm.h: Add prototype for print_insn_rx.
include/elf
* rx.h: New file.
include/opcode
* rx.h: New file.
ld
* Makefile.am: Add rules to build RX emulation.
* configure.tgt: Likewise.
* NEWS: Mention support for RX architecture.
* Makefile.in: Regenerate.
* emulparams/elf32rx.sh: New file.
* emultempl/rxelf.em: New file.
opcodes
* Makefile.am: Add RX files.
* configure.in: Add support for RX target.
* disassemble.c: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* opc2c.c: New file.
* rx-decode.c: New file.
* rx-decode.opc: New file.
* rx-dis.c: New file.
This commit is contained in:
Nick Clifton
@ -1,3 +1,7 @@
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2009-09-29 DJ Delorie <dj@redhat.com>
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* rx.h: New file.
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2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
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* ppc.h (ppc_cpu_t): Typedef to uint64_t.
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218
include/opcode/rx.h
Normal file
218
include/opcode/rx.h
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@ -0,0 +1,218 @@
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/* Opcode decoder for the Renesas RX
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Copyright 2008, 2009
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Free Software Foundation, Inc.
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Written by DJ Delorie <dj@redhat.com>
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This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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/* The RX decoder in libopcodes is used by the simulator, gdb's
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analyzer, and the disassembler. Given an opcode data source,
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it decodes the next opcode into the following structures. */
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typedef enum
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{
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RX_AnySize = 0,
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RX_Byte, /* undefined extension */
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RX_UByte,
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RX_SByte,
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RX_Word, /* undefined extension */
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RX_UWord,
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RX_SWord,
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RX_3Byte,
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RX_Long,
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} RX_Size;
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typedef enum
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{
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RX_Operand_None,
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RX_Operand_Immediate, /* #addend */
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RX_Operand_Register, /* Rn */
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RX_Operand_Indirect, /* [Rn + addend] */
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RX_Operand_Postinc, /* [Rn+] */
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RX_Operand_Predec, /* [-Rn] */
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RX_Operand_Condition, /* eq, gtu, etc */
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RX_Operand_Flag, /* [UIOSZC] */
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} RX_Operand_Type;
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typedef enum
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{
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RXO_unknown,
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RXO_mov, /* d = s (signed) */
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RXO_movbi, /* d = [s,s2] (signed) */
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RXO_movbir, /* [s,s2] = d (signed) */
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RXO_pushm, /* s..s2 */
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RXO_popm, /* s..s2 */
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RXO_pusha, /* &s */
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RXO_xchg, /* s <-> d */
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RXO_stcc, /* d = s if cond(s2) */
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RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */
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/* These are all either d OP= s or, if s2 is set, d = s OP s2. Note
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that d may be "None". */
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RXO_and,
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RXO_or,
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RXO_xor,
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RXO_add,
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RXO_sub,
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RXO_mul,
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RXO_div,
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RXO_divu,
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RXO_shll,
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RXO_shar,
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RXO_shlr,
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RXO_adc, /* d = d + s + carry */
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RXO_sbb, /* d = d - s - ~carry */
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RXO_abs, /* d = |s| */
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RXO_max, /* d = max(d,s) */
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RXO_min, /* d = min(d,s) */
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RXO_emul, /* d:64 = d:32 * s */
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RXO_emulu, /* d:64 = d:32 * s (unsigned) */
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RXO_ediv, /* d:64 / s; d = quot, d+1 = rem */
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RXO_edivu, /* d:64 / s; d = quot, d+1 = rem */
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RXO_rolc, /* d <<= 1 through carry */
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RXO_rorc, /* d >>= 1 through carry*/
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RXO_rotl, /* d <<= #s without carry */
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RXO_rotr, /* d >>= #s without carry*/
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RXO_revw, /* d = revw(s) */
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RXO_revl, /* d = revl(s) */
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RXO_branch, /* pc = d if cond(s) */
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RXO_branchrel,/* pc += d if cond(s) */
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RXO_jsr, /* pc = d */
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RXO_jsrrel, /* pc += d */
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RXO_rts,
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RXO_nop,
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RXO_scmpu,
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RXO_smovu,
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RXO_smovb,
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RXO_suntil,
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RXO_swhile,
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RXO_smovf,
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RXO_sstr,
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RXO_rmpa,
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RXO_mulhi,
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RXO_mullo,
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RXO_machi,
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RXO_maclo,
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RXO_mvtachi,
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RXO_mvtaclo,
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RXO_mvfachi,
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RXO_mvfacmi,
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RXO_mvfaclo,
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RXO_racw,
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RXO_sat, /* sat(d) */
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RXO_satr,
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RXO_fadd, /* d op= s */
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RXO_fcmp,
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RXO_fsub,
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RXO_ftoi,
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RXO_fmul,
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RXO_fdiv,
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RXO_round,
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RXO_itof,
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RXO_bset, /* d |= (1<<s) */
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RXO_bclr, /* d &= ~(1<<s) */
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RXO_btst, /* s & (1<<s2) */
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RXO_bnot, /* d ^= (1<<s) */
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RXO_bmcc, /* d<s> = cond(s2) */
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RXO_clrpsw, /* flag index in d */
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RXO_setpsw, /* flag index in d */
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RXO_mvtcp, /* cop# in s2, cop[d] = s */
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RXO_mvfcp, /* cop# in s2, d = cop[s] */
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RXO_opecp, /* cop# in s2, do cop[s] */
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RXO_rtfi,
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RXO_rte,
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RXO_rtd, /* undocumented */
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RXO_brk,
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RXO_dbt, /* undocumented */
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RXO_int, /* vector id in s */
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RXO_stop,
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RXO_wait,
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RXO_sccnd, /* d = cond(s) ? 1 : 0 */
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} RX_Opcode_ID;
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/* Condition bitpatterns, as registers. */
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#define RXC_eq 0
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#define RXC_z 0
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#define RXC_ne 1
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#define RXC_nz 1
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#define RXC_c 2
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#define RXC_nc 3
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#define RXC_gtu 4
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#define RXC_leu 5
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#define RXC_pz 6
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#define RXC_n 7
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#define RXC_ge 8
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#define RXC_lt 9
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#define RXC_gt 10
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#define RXC_le 11
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#define RXC_o 12
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#define RXC_no 13
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#define RXC_always 14
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#define RXC_never 15
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typedef struct
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{
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RX_Operand_Type type;
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int reg;
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int addend;
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RX_Size size;
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} RX_Opcode_Operand;
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typedef struct
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{
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RX_Opcode_ID id;
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int n_bytes;
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int prefix;
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char * syntax;
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RX_Size size;
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/* By convention, these are destination, source1, source2. */
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RX_Opcode_Operand op[3];
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/* The logic here is:
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newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
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Only the O, S, Z, and C flags are affected. */
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char flags_0; /* This also clears out flags-to-be-set. */
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char flags_1;
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char flags_s;
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} RX_Opcode_Decoded;
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/* Within the syntax, %c-style format specifiers are as follows:
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%% = '%' character
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%0 = operand[0] (destination)
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%1 = operand[1] (source)
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%2 = operand[2] (2nd source)
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%s = operation size (b/w/l)
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%SN = operand size [N] (N=0,1,2)
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%aN = op[N] as an address (N=0,1,2)
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Register numbers 0..15 are general registers. 16..31 are control
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registers. 32..47 are condition codes. */
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int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
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