131 lines
5.5 KiB
Diff
131 lines
5.5 KiB
Diff
From a9ce8a34cfe43f0ea168ad2efea0fd0c1fd14a2a Mon Sep 17 00:00:00 2001
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From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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Date: Thu, 21 Sep 2023 16:15:16 +0200
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Subject: [PATCH 014/198] drm/amd/display: Move the memory allocation out of
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dcn20_validate_bandwidth_fp().
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dcn20_validate_bandwidth_fp() is invoked while FPU access has been
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enabled. FPU access requires disabling preemption even on PREEMPT_RT.
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It is not possible to allocate memory with disabled preemption even with
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GFP_ATOMIC on PREEMPT_RT.
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Move the memory allocation before FPU access is enabled.
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To preserve previous "clean" state of "pipes" add a memset() before the
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second invocation of dcn20_validate_bandwidth_internal() where the
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variable is used.
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Link: https://lore.kernel.org/r/20230921141516.520471-6-bigeasy@linutronix.de
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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---
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.../drm/amd/display/dc/dcn20/dcn20_resource.c | 10 +++++++++-
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.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 16 +++++++---------
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.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 5 ++---
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3 files changed, 18 insertions(+), 13 deletions(-)
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diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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index d587f807dfd7..5036a3e60832 100644
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--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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@@ -2141,9 +2141,17 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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bool fast_validate)
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{
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bool voltage_supported;
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+ display_e2e_pipe_params_st *pipes;
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+
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+ pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
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+ if (!pipes)
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+ return false;
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+
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DC_FP_START();
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- voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
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+ voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
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DC_FP_END();
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+
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+ kfree(pipes);
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return voltage_supported;
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}
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diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
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index 89d4e969cfd8..68970d6cf031 100644
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--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
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+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
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@@ -2018,7 +2018,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
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}
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static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
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- bool fast_validate)
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+ bool fast_validate, display_e2e_pipe_params_st *pipes)
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{
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bool out = false;
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@@ -2027,7 +2027,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
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int vlevel = 0;
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int pipe_split_from[MAX_PIPES];
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int pipe_cnt = 0;
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- display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
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DC_LOGGER_INIT(dc->ctx->logger);
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BW_VAL_TRACE_COUNT();
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@@ -2062,16 +2061,14 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
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out = false;
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validate_out:
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- kfree(pipes);
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BW_VAL_TRACE_FINISH();
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return out;
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}
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-bool dcn20_validate_bandwidth_fp(struct dc *dc,
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- struct dc_state *context,
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- bool fast_validate)
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+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
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+ bool fast_validate, display_e2e_pipe_params_st *pipes)
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{
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bool voltage_supported = false;
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bool full_pstate_supported = false;
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@@ -2090,11 +2087,11 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc,
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ASSERT(context != dc->current_state);
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if (fast_validate) {
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- return dcn20_validate_bandwidth_internal(dc, context, true);
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+ return dcn20_validate_bandwidth_internal(dc, context, true, pipes);
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}
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// Best case, we support full UCLK switch latency
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- voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
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+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
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full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
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if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
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@@ -2106,7 +2103,8 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc,
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// Fallback: Try to only support G6 temperature read latency
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context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
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- voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
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+ memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));
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+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
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dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
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if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
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diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
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index a81a0b9e6884..b6c34198ddc8 100644
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--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
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+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
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@@ -61,9 +61,8 @@ void dcn20_update_bounding_box(struct dc *dc,
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unsigned int num_states);
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void dcn20_patch_bounding_box(struct dc *dc,
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struct _vcs_dpi_soc_bounding_box_st *bb);
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-bool dcn20_validate_bandwidth_fp(struct dc *dc,
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- struct dc_state *context,
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- bool fast_validate);
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+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
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+ bool fast_validate, display_e2e_pipe_params_st *pipes);
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void dcn20_fpu_set_wm_ranges(int i,
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struct pp_smu_wm_range_sets *ranges,
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struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
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--
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2.44.0
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