octospacc/OcttBitsOfFun
1
0
Fork 0
mirror of https://gitlab.com/octtspacc/OcttBitsOfFun synced 2025-02-16 19:40:37 +01:00
Code Issues Packages Projects Releases Wiki Activity

Woopsie

Browse Source
This commit is contained in:
OctoSpacc 2023-11-23 01:13:40 +01:00
parent 6635eb9eeb
commit 64da9bf1df
16 changed files with 9234 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

271
BouncyCubePs1.asm/Cube.asm Normal file
View File

@ -0,0 +1,271 @@
; PSX 'Bare Metal' Cube CPU Demo by krom (Peter Lemon):
; Joypad Control:
; Up, Down: -Y, +Y Translation
; Left, Right: -X, +X Translation
; L1, L2: -Z, +Z Translation
; Triangle, X: -X, +X Rotation
; Circle, Square: -Y, +Y Rotation
; R1, R2: -Z, +Z Rotation
.psx
.create "Cube.ps1.bin", 0x80010000
.include "LIB/PSX.INC" ; Include PSX Definitions
.include "LIB/PSX_GPU.INC" ; Include PSX GPU Definitions & Macros
.include "LIB/PSX_INPUT.INC" ; Include PSX Input Definitions & Macros
.include "LIB/3D.INC" ; Include 3D Definitions & Macros
.org 0x80010000 ; Entry Point Of Code
InitJoy PadBuffer ; Initialise Joypads & Setup VSync Wait Routine Using BIOS: Buffer Address
la a0,IO_BASE ; A0 = I/O Port Base Address ($1F80XXXX)
; Setup Screen Mode
WRGP1 GPURESET,0 ; Write GP1 Command Word (Reset GPU)
WRGP1 GPUDISPEN,0 ; Write GP1 Command Word (Enable Display)
WRGP1 GPUDISPM,HRES320+VRES240+BPP15+VNTSC ; Write GP1 Command Word (Set Display Mode: 320x240, 15BPP, NTSC)
WRGP1 GPUDISPH,0xC60260 ; Write GP1 Command Word (Horizontal Display Range 608..3168)
WRGP1 GPUDISPV,0x042018 ; Write GP1 Command Word (Vertical Display Range 24..264)
; Setup Drawing Area
WRGP0 GPUDRAWM,0x000508 ; Write GP0 Command Word (Drawing To Display Area Allowed Bit 10, Texture Page Colors = 15BPP Bit 7..8, Texture Page Y Base = 0 Bit 4, Texture Page X Base = 512 Bit 0..3)
WRGP0 GPUDRAWATL,0x000000 ; Write GP0 Command Word (Set Drawing Area Top Left X1=0, Y1=0)
WRGP0 GPUDRAWABR,0x03BD3F ; Write GP0 Command Word (Set Drawing Area Bottom Right X2=319, Y2=239)
WRGP0 GPUDRAWOFS,0x000000 ; Write GP0 Command Word (Set Drawing Offset X=0, Y=0)
.macro CopyTextureVram, TEXTURE, X,Y
CopyRectCPU X,Y, 256,256 ; Copy Rectangle (CPU To VRAM): X,Y, Width,Height
li t0,32767 ; T0 = Data Copy Word Count
la a1,TEXTURE ; A1 = Texture RAM Offset
CopyTextureThis:
lw t1,0(a1) ; T1 = DATA Word
addiu a1,4 ; A1 += 4 (Delay Slot)
sw t1,GP0(a0) ; Write GP0 Packet Word
bnez t0,CopyTextureThis ; IF (T0 != 0) Copy Texture A
subiu t0,1 ; T0-- (Delay Slot)
.endmacro
.macro CubePositionMoveCheck, joykey,position,branch
IsJoyDown joykey,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
beqz t0,branch
nop ; Delay Slot
la a1,position
lw t0,0(a1)
nop ; Delay Slot
.endmacro
CopyTextureVram TextureA, 512,0
CopyTextureVram TextureB, 768,0
;CopyTextureVram TextureC, 0,256
CopyTextureVram TextureD, 256,256
CopyTextureVram TextureE, 512,256
CopyTextureVram TextureF, 768,256
ReverseCubeAccelY:
la a2,YAccel ; Load cube acceleration
lw t1,0(a2) ; in t1
nop
subu t1,$0,t1 ; Reverse acceleration
sw t1,0(a2) ; ...
la a1,YPos ; Load cube Y position
lw t0,0(a1) ; ...
nop
add t0,t1 ; Accelerate cube
sw t0,0(a1) ; Commit cube Y position
b PRESSEND
;ReverseCubeAccelY
Refresh:
WaitVSync PadBuffer,PadData ; Wait For Vertical Retrace Period & Store XOR Pad Data: Buffer Address, Data Address
FillRectVRAM 0xEEDDFF, 0,0, 320,240 ; Fill Rectangle In VRAM: Color, X,Y, Width,Height
XYZPos XPos,YPos,ZPos ; Object X,Y,Z Translation: X,Y,Z
XYZRotCalc XRot,YRot,ZRot,SinCos256 ; XYZ Rotation Calculation: X Rotation, Y Rotation, Z Rotation, Matrix Sin & Cos Pre-Calculated Table
; Move cube towards the left
la a1,XPos ; Load cube X position
lw t0,0(a1) ;
nop ; Chill
subiu t0,32 ; Move cube left
sw t0,0(a1) ; Store position
; Gravity pulling cube down, its force remaking it jump
la a1,YPos ; Load cube Y position
lw t0,0(a1) ; ...
li t2,+8192-1024 ; Set compare value of ... floor Y
li t3,-8192-1024 ; ... roof Y
;beq t0,t2,ReverseCubeAccelY ; [If cube touches ... floor
;nop
;beq t0,t3,ReverseCubeAccelY ; reverse direction] ... roof
slt t4,t0,t2 ; if cubeY >= floorY
beq t4,$0,ReverseCubeAccelY ; then reverse it
la a2,YAccel ; Load cube acceleration
lw t1,0(a2) ; ...
nop
addi t1,16 ; Get acceleration stronger
sw t1,0(a2) ; Then store it
nop
add t0,t1 ; Accelerate cube
sw t0,0(a1) ; Commit cube Y position
; PRESSUP:
; CubePositionMoveCheck JOY_UP,YPos,PRESSDOWN
; subiu t0,256 ; Y Position--
; sw t0,0(a1)
; PRESSDOWN:
; CubePositionMoveCheck JOY_DOWN,YPos,PRESSLEFT
; addiu t0,256 ; Y Position++
; sw t0,0(a1)
; PRESSLEFT:
; CubePositionMoveCheck JOY_LEFT,XPos,PRESSRIGHT
; subiu t0,256 ; X Position--
; sw t0,0(a1)
; PRESSRIGHT:
; CubePositionMoveCheck JOY_RIGHT,XPos,PRESSL1
; addiu t0,256 ; X Position++
; sw t0,0(a1)
; PRESSL1:
; IsJoyDown JOY_L1,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSL2
; nop ; Delay Slot
; la a1,ZPos ; Z Position--
; lw t0,0(a1)
; li t1,10240
; beq t0,t1,PRESSL2
; nop ; Delay Slot
; subiu t0,256
; sw t0,0(a1)
; PRESSL2:
; IsJoyDown JOY_L2,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESST
; nop ; Delay Slot
; la a1,ZPos ; Z Position++
; lw t0,0(a1)
; li t1,25600
; beq t0,t1,PRESST
; nop ; Delay Slot
; addiu t0,256
; sw t0,0(a1)
; PRESST:
; IsJoyDown JOY_T,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSX
; nop ; Delay Slot
; la a1,XRot ; X Rotation--
; lw t0,0(a1)
; nop ; Delay Slot
; subiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
; PRESSX:
; IsJoyDown JOY_X,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSC
; nop ; Delay Slot
; la a1,XRot ; X Rotation++
; lw t0,0(a1)
; nop ; Delay Slot
; addiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
; PRESSC:
; IsJoyDown JOY_C,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSS
; nop ; Delay Slot
; la a1,YRot ; Y Rotation--
; lw t0,0(a1)
; nop ; Delay Slot
; subiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
; PRESSS:
; IsJoyDown JOY_S,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSR1
; nop ; Delay Slot
; la a1,YRot ; Y Rotation++
; lw t0,0(a1)
; nop ; Delay Slot
; addiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
; PRESSR1:
; IsJoyDown JOY_R1,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSR2
; nop ; Delay Slot
; la a1,ZRot ; Z Rotation--
; lw t0,0(a1)
; nop ; Delay Slot
; subiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
; PRESSR2:
; IsJoyDown JOY_R2,PadData ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
; beqz t0,PRESSEND
; nop ; Delay Slot
; la a1,ZRot ; Z Rotation++
; lw t0,0(a1)
; nop ; Delay Slot
; addiu t0,1
; andi t0,0xFF
; sw t0,0(a1)
PRESSEND:
ShadeTexQuadCullBackZSort ShadeTexCubeQuad,ShadeTexCubeQuadEnd,PolySort ; Shaded Texture Quad Back Face Cull Z Sort: Object Start Address, Object End Address, Sort Address
b Refresh
nop ; Delay Slot
PadBuffer:
dw 0 ; Pad Buffer (Automatically Stored Every Frame)
PadData:
dw 0 ; Pad Data (Read From VSync Routine)
XPos:
dw 16384 ; X Position Word
YPos:
dw 512 ; Y Position Word
ZPos:
dw 25600 ; Z Position Word
YAccel:
dw -64
XRot:
dw 0 ; X Rotate Word (0..255)
YRot:
dw 0 ; Y Rotate Word (0..255)
ZRot:
dw 0 ; Z Rotate Word (0..255)
Matrix3D: ; 3D Matrix: Set To Default Identity Matrix (All Numbers Multiplied By 256 For 24.8 Fixed Point Format)
dw 256, 0, 0, 0 ; X = 1.0, 0.0, 0.0, X Translation = 0.0
dw 0, 256, 0, 0 ; 0.0, Y = 1.0, 0.0, Y Translation = 0.0
dw 0, 0, 256, 0 ; 0.0, 0.0, Z = 1.0, Z Translation = 0.0
; Matrix Sin & Cos Pre-Calculated Table
.include "sincos256.asm" ; Matrix Sin & Cos Pre-Calculated Table (256 Rotations)
; Object Data
.include "objects.asm" ; Object Data
TextureA:
.incbin "GFX/A.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
TextureB:
.incbin "GFX/B.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
;TextureC:
; .incbin "GFX/C.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
TextureD:
.incbin "GFX/D.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
TextureE:
.incbin "GFX/E.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
TextureF:
.incbin "GFX/F.bin" ; Include 256x256 15BPP Texture Data (131072 Bytes)
PolySort: ; Polygon Sorting Area
.close

1
BouncyCubePs1.asm/GFX/A.bin Normal file
View File

File diff suppressed because one or more lines are too long

6
BouncyCubePs1.asm/GFX/B.bin Normal file
View File

File diff suppressed because one or more lines are too long

1
BouncyCubePs1.asm/GFX/C.bin Normal file
View File

File diff suppressed because one or more lines are too long

1
BouncyCubePs1.asm/GFX/D.bin Normal file
View File

File diff suppressed because one or more lines are too long

1
BouncyCubePs1.asm/GFX/E.bin Normal file
View File

File diff suppressed because one or more lines are too long

1
BouncyCubePs1.asm/GFX/F.bin Normal file
View File

File diff suppressed because one or more lines are too long

5533
BouncyCubePs1.asm/LIB/3D.INC Normal file
View File

File diff suppressed because it is too large Load Diff

427
BouncyCubePs1.asm/LIB/PSX.INC Normal file
View File

@ -0,0 +1,427 @@
;============== (Key: R=Read, W=Write)
; PSX Include
;==============
; Memory Map
RAM_KUSEG equ 0x00000000 ; Main RAM KUSEG (Cached) (First 64KB Reserved For BIOS) 2048KB/RW
RAM_KSEG0 equ 0x80000000 ; Main RAM KSEG0 (Uncached) (First 64KB Reserved For BIOS) 2048KB/RW
RAM_KSEG1 equ 0xA0000000 ; Main RAM KSEG1 (Virtual) (First 64KB Reserved For BIOS) 2048KB/RW
EXP1_KUSEG equ 0x1F000000 ; Expansion Region 1 (ROM/RAM) KUSEG (Cached) 8192KB/RW
EXP1_KSEG0 equ 0x9F000000 ; Expansion Region 1 (ROM/RAM) KSEG0 (Uncached) 8192KB/RW
EXP1_KSEG1 equ 0xBF000000 ; Expansion Region 1 (ROM/RAM) KSEG1 (Virtual) 8192KB/RW
SPM_KUSEG equ 0x1F800000 ; Scratchpad (D-Cache Used As Fast RAM) KUSEG (Cached) 1KB/RW
SPM_KSEG0 equ 0x9F800000 ; Scratchpad (D-Cache Used As Fast RAM) KSEG0 (Uncached) 1KB/RW
SPM_KSEG1 equ 0xBF800000 ; Scratchpad (D-Cache Used As Fast RAM) KSEG1 (Virtual) 1KB/RW
IOP_KUSEG equ 0x1F801000 ; I/O Ports KUSEG (Cached) 8KB/RW
IOP_KSEG0 equ 0x9F801000 ; I/O Ports KSEG0 (Uncached) 8KB/RW
IOP_KSEG1 equ 0xBF801000 ; I/O Ports KSEG1 (Virtual) 8KB/RW
EXP2_KUSEG equ 0x1F802000 ; Expansion Region 2 (I/O Ports) KUSEG (Cached) 8KB/RW
EXP2_KSEG0 equ 0x9F802000 ; Expansion Region 2 (I/O Ports) KSEG0 (Uncached) 8KB/RW
EXP2_KSEG1 equ 0xBF802000 ; Expansion Region 2 (I/O Ports) KSEG1 (Virtual) 8KB/RW
EXP3_KUSEG equ 0x1FA00000 ; Expansion Region 3 (Whatever Purpose) KUSEG (Cached) 2048KB/RW
EXP3_KSEG0 equ 0x9FA00000 ; Expansion Region 3 (Whatever Purpose) KSEG0 (Uncached) 2048KB/RW
EXP3_KSEG1 equ 0xBFA00000 ; Expansion Region 3 (Whatever Purpose) KSEG1 (Virtual) 2048KB/RW
BIOS_KUSEG equ 0x1FC00000 ; BIOS ROM (Kernel) (4096K Max) KUSEG (Cached) 4096KB/R
BIOS_KSEG0 equ 0x9FC00000 ; BIOS ROM (Kernel) (4096K max) KSEG0 (Uncached) 4096KB/R
BIOS_KSEG1 equ 0xBFC00000 ; BIOS ROM (Kernel) (4096K max) KSEG1 (Virtual) 4096KB/R
IOP_KSEG2 equ 0xFFFE0000 ; I/O Ports (Cache Control) KSEG2 512B/RW
; I/O Map
IO_BASE equ 0x1F800000 ; I/O Port Base Address ($1F80XXXX)
; Expansion Region 1
EXP1_BASE equ 0x1F000000 ; $1F000000..$1F07FFFF Expansion Region 1: Region (Default 512KB, Max 8MB) 8192KB/RW
EXP1_ROM equ 0x1F000000 ; $1F000000..$1F0000FF Expansion Region 1: ROM Header (IDs & Entrypoints) 256B/R
; Scratchpad
SPM_RAM equ 0x0000 ; $1F800000..$1F8003FF Scratchpad: (1KB Fast RAM) (Data Cache Mapped To Fixed Address) 1KB/RW
; Memory Control 1
EXP1_ADDR equ 0x1000 ; $1F801000..$1F801003 Memory Control 1: Expansion 1 Base Address (Usually $1F000000) 4B/RW
EXP2_ADDR equ 0x1004 ; $1F801004..$1F801007 Memory Control 1: Expansion 2 Base Address (usually $1F802000) 4B/RW
EXP1_DELAY equ 0x1008 ; $1F801008..$1F80100B Memory Control 1: Expansion 1 Delay/Size (Usually $0013243F/512KB 8-Bit BUS) 4B/RW
EXP3_DELAY equ 0x100C ; $1F80100C..$1F80100F Memory Control 1: Expansion 3 Delay/Size (Usually $00003022/1B) 4B/RW
BIOS_DELAY equ 0x1010 ; $1F801010..$1F801013 Memory Control 1: BIOS ROM Delay/Size (Usually $0013243F/512KB 8-Bit BUS) 4B/RW
SPU_DELAY equ 0x1014 ; $1F801014..$1F801017 Memory Control 1: SPU Delay/Size (Usually $200931E1) 4B/RW
CDROM_DELAY equ 0x1018 ; $1F801018..$1F80101B Memory Control 1: CDROM Delay/Size (Usually $00020843 Or $00020943) 4B/RW
EXP2_DELAY equ 0x101C ; $1F80101C..$1F80101F Memory Control 1: Expansion 2 Delay/Size (Usually $00070777/128B 8-Bit BUS) 4B/RW
COM_DELAY equ 0x1020 ; $1F801020..$1F801023 Memory Control 1: COMMON Delay/Size ($00031125 Or $0000132C Or $00001325) 4B/RW
; Peripheral I/O Ports
JOY_DATA equ 0x1040 ; $1F801040..$1F801043 Peripheral I/O Ports: Joypad/Memory Card Data 4B/RW
JOY_STAT equ 0x1044 ; $1F801044..$1F801047 Peripheral I/O Ports: Joypad/Memory Card Status 4B/R
JOY_MODE equ 0x1048 ; $1F801048..$1F801049 Peripheral I/O Ports: Joypad/Memory Card Mode 2B/RW
JOY_CTRL equ 0x104A ; $1F80104A..$1F80104D Peripheral I/O Ports: Joypad/Memory Card Control 4B/RW
JOY_BAUD equ 0x104E ; $1F80104E..$1F80104F Peripheral I/O Ports: Joypad/Memory Card Baudrate 2B/RW
SIO_DATA equ 0x1050 ; $1F801050..$1F801053 Peripheral I/O Ports: Serial Port Data 4B/RW
SIO_STAT equ 0x1054 ; $1F801054..$1F801057 Peripheral I/O Ports: Serial Port Status 4B/R
SIO_MODE equ 0x1058 ; $1F801058..$1F801059 Peripheral I/O Ports: Serial Port Mode 2B/RW
SIO_CTRL equ 0x105A ; $1F80105A..$1F80105B Peripheral I/O Ports: Serial Port Control 2B/RW
SIO_MISC equ 0x105C ; $1F80105C..$1F80105D Peripheral I/O Ports: Serial Port Internal Register 2B/RW
SIO_BAUD equ 0x105E ; $1F80105E..$1F80105F Peripheral I/O Ports: Serial Port Baudrate 2B/RW
; Memory Control 2
RAM_SIZE equ 0x1060 ; $1F801060..$1F801063 Memory Control 2: RAM Size (Usually $00000B88/2MB RAM Mirrored In First 8MB) 4B/RW
; Interrupt Control
I_STAT equ 0x1070 ; $1F801070..$1F801073 Interrupt Control: Interrupt Status Register 4B/RW
I_MASK equ 0x1074 ; $1F801074..$1F801077 Interrupt Control: Interrupt Mask Register 4B/RW
; DMA Registers
D0_MADR equ 0x1080 ; $1F801080..$1F801083 DMA Registers: DMA Channel 0 Base Address (MDECin) 4B/RW
D0_BCR equ 0x1084 ; $1F801084..$1F801087 DMA Registers: DMA Channel 0 Block Control (MDECin) 4B/RW
D0_CHCR equ 0x1088 ; $1F801088..$1F80108B DMA Registers: DMA Channel 0 Channel Control (MDECin) 4B/RW
D1_MADR equ 0x1090 ; $1F801090..$1F801093 DMA Registers: DMA Channel 1 Base Address (MDECout) 4B/RW
D1_BCR equ 0x1094 ; $1F801094..$1F801097 DMA Registers: DMA Channel 1 Block Control (MDECout) 4B/RW
D1_CHCR equ 0x1098 ; $1F801098..$1F80109B DMA Registers: DMA Channel 1 Channel Control (MDECout) 4B/RW
D2_MADR equ 0x10A0 ; $1F8010A0..$1F8010A3 DMA Registers: DMA Channel 2 Base Address (GPU Display List & Image Data) 4B/RW
D2_BCR equ 0x10A4 ; $1F8010A4..$1F8010A7 DMA Registers: DMA Channel 2 Block Control (GPU Display List & Image Data) 4B/RW
D2_CHCR equ 0x10A8 ; $1F8010A8..$1F8010AB DMA Registers: DMA Channel 2 Channel Control (GPU Display List & Image Data) 4B/RW
D3_MADR equ 0x10B0 ; $1F8010B0..$1F8010B3 DMA Registers: DMA Channel 3 Base Address (CDROM) 4B/RW
D3_BCR equ 0x10B4 ; $1F8010B4..$1F8010B7 DMA Registers: DMA Channel 3 Block Control (CDROM) 4B/RW
D3_CHCR equ 0x10B8 ; $1F8010B8..$1F8010BB DMA Registers: DMA Channel 3 Channel Control (CDROM) 4B/RW
D4_MADR equ 0x10C0 ; $1F8010C0..$1F8010C3 DMA Registers: DMA Channel 4 Base Address (SPU) 4B/RW
D4_BCR equ 0x10C4 ; $1F8010C4..$1F8010C7 DMA Registers: DMA Channel 4 Block Control (SPU) 4B/RW
D4_CHCR equ 0x10C8 ; $1F8010C8..$1F8010CB DMA Registers: DMA Channel 4 Channel Control (SPU) 4B/RW
D5_MADR equ 0x10D0 ; $1F8010D0..$1F8010D3 DMA Registers: DMA Channel 5 Base Address (PIO Expansion Port) 4B/RW
D5_BCR equ 0x10D4 ; $1F8010D4..$1F8010D7 DMA Registers: DMA Channel 5 Block Control (PIO Expansion Port) 4B/RW
D5_CHCR equ 0x10D8 ; $1F8010D8..$1F8010DB DMA Registers: DMA Channel 5 Channel Control (PIO Expansion Port) 4B/RW
D6_MADR equ 0x10E0 ; $1F8010E0..$1F8010E3 DMA Registers: DMA Channel 6 Base Address (OTC Reverse Clear OT, GPU Related) 4B/RW
D6_BCR equ 0x10E4 ; $1F8010E4..$1F8010E7 DMA Registers: DMA Channel 6 Block Control (OTC Reverse Clear OT, GPU Related) 4B/RW
D6_CHCR equ 0x10E8 ; $1F8010E8..$1F8010EB DMA Registers: DMA Channel 6 Channel Control (OTC Reverse Clear OT, GPU Related) 4B/RW
DPCR equ 0x10F0 ; $1F8010F0..$1F8010F3 DMA Registers: DMA Control Register 4B/RW
DICR equ 0x10F4 ; $1F8010F4..$1F8010F7 DMA Registers: DMA Interrupt Register 4B/RW
D_UNK1 equ 0x10F8 ; $1F8010F8..$1F8010FB DMA Registers: DMA Unknown (Changes To $7FE358D1 After DMA Transfer) 4B/RW
D_UNK2 equ 0x10FC ; $1F8010FC..$1F8010FF DMA Registers: DMA Unknown (Usually $00FFFFF7) (Maybe OTC Fill Value) 4B/RW
; Timers (AKA Root Counters)
T0_CNT equ 0x1100 ; $1F801100..$1F801103 Timers: Timer 0 Current Counter Value (Dotclock) 4B/RW
T0_CNTM equ 0x1104 ; $1F801104..$1F801107 Timers: Timer 0 Counter Mode (Dotclock) 4B/RW
T0_CNTT equ 0x1108 ; $1F801108..$1F80110B Timers: Timer 0 Counter Target Value (Dotclock) 4B/RW
T1_CNT equ 0x1110 ; $1F801110..$1F801113 Timers: Timer 1 Current Counter Value (Horizontal Retrace) 4B/RW
T1_CNTM equ 0x1114 ; $1F801114..$1F801117 Timers: Timer 1 Counter Mode (Horizontal Retrace) 4B/RW
T1_CNTT equ 0x1118 ; $1F801118..$1F80111B Timers: Timer 1 Counter Target Value (Horizontal Retrace) 4B/RW
T2_CNT equ 0x1120 ; $1F801120..$1F801123 Timers: Timer 2 Current Counter Value (1/8 System Clock) 4B/RW
T2_CNTM equ 0x1124 ; $1F801124..$1F801127 Timers: Timer 2 Counter Mode (1/8 System Clock) 4B/RW
T2_CNTT equ 0x1128 ; $1F801128..$1F80112B Timers: Timer 2 Counter Target Value (1/8 System Clock) 4B/RW
; CDROM Registers (Address.Read/Write.Index)
CD_STAT equ 0x1800 ; $1F801800..$1F801800 CDROM Registers: CD Index/Status Register (Bit 0..1 R/W, Bit 2..7 Read Only) 1B/RW
CD_RRFI equ 0x1801 ; $1F801801..$1F801801 CDROM Registers: Read CD Response Fifo (Usually With Index1) 1B/R
CD_RDFI equ 0x1802 ; $1F801802..$1F801802 CDROM Registers: Read CD Data Fifo 8-Bit/16-Bit (Usually With Index0..1) 1B/R
CD_R0INT equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Read 0 CD Interrupt Enable Register 1B/R
CD_R1FLG equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Read 1 CD Interrupt Flag Register 1B/RW
CD_R2INT equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Read 2 CD Interrupt Enable Register (Mirror) 1B/R
CD_R3FLG equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Read 3 CD Interrupt Flag Register (Mirror) 1B/RW
CD_W0COM equ 0x1801 ; $1F801801..$1F801801 CDROM Registers: Write 0 CD Command Register 1B/W
CD_W0PFI equ 0x1802 ; $1F801802..$1F801802 CDROM Registers: Write 0 CD Parameter Fifo 1B/W
CD_W0REQ equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Write 0 CD Request Register 1B/W
CD_W1UNK equ 0x1801 ; $1F801801..$1F801801 CDROM Registers: Write 1 CD Unknown/Unused 1B/W
CD_W1INT equ 0x1802 ; $1F801802..$1F801802 CDROM Registers: Write 1 CD Interrupt Enable Register 1B/W
CD_W1FLG equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Write 1 CD Interrupt Flag Register 1B/RW
CD_W2UNK equ 0x1801 ; $1F801801..$1F801801 CDROM Registers: Write 2 CD Unknown/Unused 1B/W
CD_W2VLL equ 0x1802 ; $1F801802..$1F801802 CDROM Registers: Write 2 CD Audio Volume For Left-CD-Out To Left-SPU-Input 1B/W
CD_W2VLR equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Write 2 CD Audio Volume For Left-CD-Out To Right-SPU-Input 1B/W
CD_W3VRR equ 0x1801 ; $1F801801..$1F801801 CDROM Registers: Write 3 CD Audio Volume For Right-CD-Out To Right-SPU-Input 1B/W
CD_W3VRL equ 0x1802 ; $1F801802..$1F801802 CDROM Registers: Write 3 CD Audio Volume For Right-CD-Out To Left-SPU-Input 1B/W
CD_W3VAC equ 0x1803 ; $1F801803..$1F801803 CDROM Registers: Write 3 CD Audio Volume Apply Changes (By Writing Bit 5 = 1) 1B/W
; GPU Registers
GP0 equ 0x1810 ; $1F801810..$1F801813 GPU Registers: Write GP0 Commands/Packets (Rendering & VRAM Access) 4B/W
GP1 equ 0x1814 ; $1F801814..$1F801817 GPU Registers: Write GP1 Commands (Display Control) 4B/W
GPUREAD equ 0x1810 ; $1F801810..$1F801813 GPU Registers: Read Responses To GP0($C0) & GP1($10) Commands 4B/R
GPUSTAT equ 0x1814 ; $1F801814..$1F801817 GPU Registers: Read GPU Status Register 4B/R
; MDEC Registers
MDECPAR equ 0x1820 ; $1F801820..$1F801823 MDEC Registers: Write MDEC Command/Parameter Register 4B/W
MDECCNT equ 0x1824 ; $1F801824..$1F801827 MDEC Registers: Write MDEC Control/Reset Register 4B/W
MDECREAD equ 0x1820 ; $1F801820..$1F801823 MDEC Registers: Read MDEC Data/Response Register 4B/R
MDECSTAT equ 0x1824 ; $1F801824..$1F801827 MDEC Registers: Read MDEC Status Register 4B/R
; SPU Voice Registers (0..23)
SPUVOL0 equ 0x1C00 ; $1F801C00..$1F801C03 SPU Voice Registers: Voice 0 Volume Left/Right 4B/RW
SPUVOL1 equ 0x1C10 ; $1F801C10..$1F801C13 SPU Voice Registers: Voice 1 Volume Left/Right 4B/RW
SPUVOL2 equ 0x1C20 ; $1F801C20..$1F801C23 SPU Voice Registers: Voice 2 Volume Left/Right 4B/RW
SPUVOL3 equ 0x1C30 ; $1F801C30..$1F801C33 SPU Voice Registers: Voice 3 Volume Left/Right 4B/RW
SPUVOL4 equ 0x1C40 ; $1F801C40..$1F801C43 SPU Voice Registers: Voice 4 Volume Left/Right 4B/RW
SPUVOL5 equ 0x1C50 ; $1F801C50..$1F801C53 SPU Voice Registers: Voice 5 Volume Left/Right 4B/RW
SPUVOL6 equ 0x1C60 ; $1F801C60..$1F801C63 SPU Voice Registers: Voice 6 Volume Left/Right 4B/RW
SPUVOL7 equ 0x1C70 ; $1F801C70..$1F801C73 SPU Voice Registers: Voice 7 Volume Left/Right 4B/RW
SPUVOL8 equ 0x1C80 ; $1F801C80..$1F801C83 SPU Voice Registers: Voice 8 Volume Left/Right 4B/RW
SPUVOL9 equ 0x1C90 ; $1F801C90..$1F801C93 SPU Voice Registers: Voice 9 Volume Left/Right 4B/RW
SPUVOL10 equ 0x1CA0 ; $1F801CA0..$1F801CA3 SPU Voice Registers: Voice 10 Volume Left/Right 4B/RW
SPUVOL11 equ 0x1CB0 ; $1F801CB0..$1F801CB3 SPU Voice Registers: Voice 11 Volume Left/Right 4B/RW
SPUVOL12 equ 0x1CC0 ; $1F801CC0..$1F801CC3 SPU Voice Registers: Voice 12 Volume Left/Right 4B/RW
SPUVOL13 equ 0x1CD0 ; $1F801CD0..$1F801CD3 SPU Voice Registers: Voice 13 Volume Left/Right 4B/RW
SPUVOL14 equ 0x1CE0 ; $1F801CE0..$1F801CE3 SPU Voice Registers: Voice 14 Volume Left/Right 4B/RW
SPUVOL15 equ 0x1CF0 ; $1F801CF0..$1F801CF3 SPU Voice Registers: Voice 15 Volume Left/Right 4B/RW
SPUVOL16 equ 0x1D00 ; $1F801D00..$1F801D03 SPU Voice Registers: Voice 16 Volume Left/Right 4B/RW
SPUVOL17 equ 0x1D10 ; $1F801D10..$1F801D13 SPU Voice Registers: Voice 17 Volume Left/Right 4B/RW
SPUVOL18 equ 0x1D20 ; $1F801D20..$1F801D23 SPU Voice Registers: Voice 18 Volume Left/Right 4B/RW
SPUVOL19 equ 0x1D30 ; $1F801D30..$1F801D33 SPU Voice Registers: Voice 19 Volume Left/Right 4B/RW
SPUVOL20 equ 0x1D40 ; $1F801D40..$1F801D43 SPU Voice Registers: Voice 20 Volume Left/Right 4B/RW
SPUVOL21 equ 0x1D50 ; $1F801D50..$1F801D53 SPU Voice Registers: Voice 21 Volume Left/Right 4B/RW
SPUVOL22 equ 0x1D60 ; $1F801D60..$1F801D63 SPU Voice Registers: Voice 22 Volume Left/Right 4B/RW
SPUVOL23 equ 0x1D70 ; $1F801D70..$1F801D73 SPU Voice Registers: Voice 23 Volume Left/Right 4B/RW
SPUFRQ0 equ 0x1C04 ; $1F801C04..$1F801C05 SPU Voice Registers: Voice 0 ADPCM Sample Rate 2B/RW
SPUFRQ1 equ 0x1C14 ; $1F801C14..$1F801C15 SPU Voice Registers: Voice 1 ADPCM Sample Rate 2B/RW
SPUFRQ2 equ 0x1C24 ; $1F801C24..$1F801C25 SPU Voice Registers: Voice 2 ADPCM Sample Rate 2B/RW
SPUFRQ3 equ 0x1C34 ; $1F801C34..$1F801C35 SPU Voice Registers: Voice 3 ADPCM Sample Rate 2B/RW
SPUFRQ4 equ 0x1C44 ; $1F801C44..$1F801C45 SPU Voice Registers: Voice 4 ADPCM Sample Rate 2B/RW
SPUFRQ5 equ 0x1C54 ; $1F801C54..$1F801C55 SPU Voice Registers: Voice 5 ADPCM Sample Rate 2B/RW
SPUFRQ6 equ 0x1C64 ; $1F801C64..$1F801C65 SPU Voice Registers: Voice 6 ADPCM Sample Rate 2B/RW
SPUFRQ7 equ 0x1C74 ; $1F801C74..$1F801C75 SPU Voice Registers: Voice 7 ADPCM Sample Rate 2B/RW
SPUFRQ8 equ 0x1C84 ; $1F801C84..$1F801C85 SPU Voice Registers: Voice 8 ADPCM Sample Rate 2B/RW
SPUFRQ9 equ 0x1C94 ; $1F801C94..$1F801C95 SPU Voice Registers: Voice 9 ADPCM Sample Rate 2B/RW
SPUFRQ10 equ 0x1CA4 ; $1F801CA4..$1F801CA5 SPU Voice Registers: Voice 10 ADPCM Sample Rate 2B/RW
SPUFRQ11 equ 0x1CB4 ; $1F801CB4..$1F801CB5 SPU Voice Registers: Voice 11 ADPCM Sample Rate 2B/RW
SPUFRQ12 equ 0x1CC4 ; $1F801CC4..$1F801CC5 SPU Voice Registers: Voice 12 ADPCM Sample Rate 2B/RW
SPUFRQ13 equ 0x1CD4 ; $1F801CD4..$1F801CD5 SPU Voice Registers: Voice 13 ADPCM Sample Rate 2B/RW
SPUFRQ14 equ 0x1CE4 ; $1F801CE4..$1F801CE5 SPU Voice Registers: Voice 14 ADPCM Sample Rate 2B/RW
SPUFRQ15 equ 0x1CF4 ; $1F801CF4..$1F801CF5 SPU Voice Registers: Voice 15 ADPCM Sample Rate 2B/RW
SPUFRQ16 equ 0x1D04 ; $1F801D04..$1F801D05 SPU Voice Registers: Voice 16 ADPCM Sample Rate 2B/RW
SPUFRQ17 equ 0x1D14 ; $1F801D14..$1F801D15 SPU Voice Registers: Voice 17 ADPCM Sample Rate 2B/RW
SPUFRQ18 equ 0x1D24 ; $1F801D24..$1F801D25 SPU Voice Registers: Voice 18 ADPCM Sample Rate 2B/RW
SPUFRQ19 equ 0x1D34 ; $1F801D34..$1F801D35 SPU Voice Registers: Voice 19 ADPCM Sample Rate 2B/RW
SPUFRQ20 equ 0x1D44 ; $1F801D44..$1F801D45 SPU Voice Registers: Voice 20 ADPCM Sample Rate 2B/RW
SPUFRQ21 equ 0x1D54 ; $1F801D54..$1F801D55 SPU Voice Registers: Voice 21 ADPCM Sample Rate 2B/RW
SPUFRQ22 equ 0x1D64 ; $1F801D64..$1F801D65 SPU Voice Registers: Voice 22 ADPCM Sample Rate 2B/RW
SPUFRQ23 equ 0x1D74 ; $1F801D74..$1F801D75 SPU Voice Registers: Voice 23 ADPCM Sample Rate 2B/RW
SPUBASE0 equ 0x1C06 ; $1F801C06..$1F801C07 SPU Voice Registers: Voice 0 ADPCM Start Address 2B/RW
SPUBASE1 equ 0x1C16 ; $1F801C16..$1F801C17 SPU Voice Registers: Voice 1 ADPCM Start Address 2B/RW
SPUBASE2 equ 0x1C26 ; $1F801C26..$1F801C27 SPU Voice Registers: Voice 2 ADPCM Start Address 2B/RW
SPUBASE3 equ 0x1C36 ; $1F801C36..$1F801C37 SPU Voice Registers: Voice 3 ADPCM Start Address 2B/RW
SPUBASE4 equ 0x1C46 ; $1F801C46..$1F801C47 SPU Voice Registers: Voice 4 ADPCM Start Address 2B/RW
SPUBASE5 equ 0x1C56 ; $1F801C56..$1F801C57 SPU Voice Registers: Voice 5 ADPCM Start Address 2B/RW
SPUBASE6 equ 0x1C66 ; $1F801C66..$1F801C67 SPU Voice Registers: Voice 6 ADPCM Start Address 2B/RW
SPUBASE7 equ 0x1C76 ; $1F801C76..$1F801C77 SPU Voice Registers: Voice 7 ADPCM Start Address 2B/RW
SPUBASE8 equ 0x1C86 ; $1F801C86..$1F801C87 SPU Voice Registers: Voice 8 ADPCM Start Address 2B/RW
SPUBASE9 equ 0x1C96 ; $1F801C96..$1F801C97 SPU Voice Registers: Voice 9 ADPCM Start Address 2B/RW
SPUBASE10 equ 0x1CA6 ; $1F801CA6..$1F801CA7 SPU Voice Registers: Voice 10 ADPCM Start Address 2B/RW
SPUBASE11 equ 0x1CB6 ; $1F801CB6..$1F801CB7 SPU Voice Registers: Voice 11 ADPCM Start Address 2B/RW
SPUBASE12 equ 0x1CC6 ; $1F801CC6..$1F801CC7 SPU Voice Registers: Voice 12 ADPCM Start Address 2B/RW
SPUBASE13 equ 0x1CD6 ; $1F801CD6..$1F801CD7 SPU Voice Registers: Voice 13 ADPCM Start Address 2B/RW
SPUBASE14 equ 0x1CE6 ; $1F801CE6..$1F801CE7 SPU Voice Registers: Voice 14 ADPCM Start Address 2B/RW
SPUBASE15 equ 0x1CF6 ; $1F801CF6..$1F801CF7 SPU Voice Registers: Voice 15 ADPCM Start Address 2B/RW
SPUBASE16 equ 0x1D06 ; $1F801D06..$1F801D07 SPU Voice Registers: Voice 16 ADPCM Start Address 2B/RW
SPUBASE17 equ 0x1D16 ; $1F801D16..$1F801D17 SPU Voice Registers: Voice 17 ADPCM Start Address 2B/RW
SPUBASE18 equ 0x1D26 ; $1F801D26..$1F801D27 SPU Voice Registers: Voice 18 ADPCM Start Address 2B/RW
SPUBASE19 equ 0x1D36 ; $1F801D36..$1F801D37 SPU Voice Registers: Voice 19 ADPCM Start Address 2B/RW
SPUBASE20 equ 0x1D46 ; $1F801D46..$1F801D47 SPU Voice Registers: Voice 20 ADPCM Start Address 2B/RW
SPUBASE21 equ 0x1D56 ; $1F801D56..$1F801D57 SPU Voice Registers: Voice 21 ADPCM Start Address 2B/RW
SPUBASE22 equ 0x1D66 ; $1F801D66..$1F801D67 SPU Voice Registers: Voice 22 ADPCM Start Address 2B/RW
SPUBASE23 equ 0x1D76 ; $1F801D76..$1F801D77 SPU Voice Registers: Voice 23 ADPCM Start Address 2B/RW
SPUADSR0 equ 0x1C08 ; $1F801C08..$1F801C0B SPU Voice Registers: Voice 0 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR1 equ 0x1C18 ; $1F801C18..$1F801C1B SPU Voice Registers: Voice 1 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR2 equ 0x1C28 ; $1F801C28..$1F801C2B SPU Voice Registers: Voice 2 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR3 equ 0x1C38 ; $1F801C38..$1F801C3B SPU Voice Registers: Voice 3 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR4 equ 0x1C48 ; $1F801C48..$1F801C4B SPU Voice Registers: Voice 4 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR5 equ 0x1C58 ; $1F801C58..$1F801C5B SPU Voice Registers: Voice 5 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR6 equ 0x1C68 ; $1F801C68..$1F801C6B SPU Voice Registers: Voice 6 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR7 equ 0x1C78 ; $1F801C78..$1F801C7B SPU Voice Registers: Voice 7 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR8 equ 0x1C88 ; $1F801C88..$1F801C8B SPU Voice Registers: Voice 8 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR9 equ 0x1C98 ; $1F801C98..$1F801C9B SPU Voice Registers: Voice 9 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR10 equ 0x1CA8 ; $1F801CA8..$1F801CAB SPU Voice Registers: Voice 10 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR11 equ 0x1CB8 ; $1F801CB8..$1F801CBB SPU Voice Registers: Voice 11 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR12 equ 0x1CC8 ; $1F801CC8..$1F801CCB SPU Voice Registers: Voice 12 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR13 equ 0x1CD8 ; $1F801CD8..$1F801CDB SPU Voice Registers: Voice 13 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR14 equ 0x1CE8 ; $1F801CE8..$1F801CEB SPU Voice Registers: Voice 14 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR15 equ 0x1CF8 ; $1F801CF8..$1F801CFB SPU Voice Registers: Voice 15 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR16 equ 0x1D08 ; $1F801D08..$1F801D0B SPU Voice Registers: Voice 16 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR17 equ 0x1D18 ; $1F801D18..$1F801D1B SPU Voice Registers: Voice 17 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR18 equ 0x1D28 ; $1F801D28..$1F801D2B SPU Voice Registers: Voice 18 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR19 equ 0x1D38 ; $1F801D38..$1F801D3B SPU Voice Registers: Voice 19 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR20 equ 0x1D48 ; $1F801D48..$1F801D4B SPU Voice Registers: Voice 20 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR21 equ 0x1D58 ; $1F801D58..$1F801D5B SPU Voice Registers: Voice 21 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR22 equ 0x1D68 ; $1F801D68..$1F801D6B SPU Voice Registers: Voice 22 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSR23 equ 0x1D78 ; $1F801D78..$1F801D7B SPU Voice Registers: Voice 23 ADSR (Attack/Decay/Sustain/Release) 4B/RW
SPUADSRVOL0 equ 0x1C0C ; $1F801C0C..$1F801C0D SPU Voice Registers: Voice 0 ADSR Current Volume 2B/RW
SPUADSRVOL1 equ 0x1C1C ; $1F801C1C..$1F801C1D SPU Voice Registers: Voice 1 ADSR Current Volume 2B/RW
SPUADSRVOL2 equ 0x1C2C ; $1F801C2C..$1F801C2D SPU Voice Registers: Voice 2 ADSR Current Volume 2B/RW
SPUADSRVOL3 equ 0x1C3C ; $1F801C3C..$1F801C3D SPU Voice Registers: Voice 3 ADSR Current Volume 2B/RW
SPUADSRVOL4 equ 0x1C4C ; $1F801C4C..$1F801C4D SPU Voice Registers: Voice 4 ADSR Current Volume 2B/RW
SPUADSRVOL5 equ 0x1C5C ; $1F801C5C..$1F801C5D SPU Voice Registers: Voice 5 ADSR Current Volume 2B/RW
SPUADSRVOL6 equ 0x1C6C ; $1F801C6C..$1F801C6D SPU Voice Registers: Voice 6 ADSR Current Volume 2B/RW
SPUADSRVOL7 equ 0x1C7C ; $1F801C7C..$1F801C7D SPU Voice Registers: Voice 7 ADSR Current Volume 2B/RW
SPUADSRVOL8 equ 0x1C8C ; $1F801C8C..$1F801C8D SPU Voice Registers: Voice 8 ADSR Current Volume 2B/RW
SPUADSRVOL9 equ 0x1C9C ; $1F801C9C..$1F801C9D SPU Voice Registers: Voice 9 ADSR Current Volume 2B/RW
SPUADSRVOL10 equ 0x1CAC ; $1F801CAC..$1F801CAD SPU Voice Registers: Voice 10 ADSR Current Volume 2B/RW
SPUADSRVOL11 equ 0x1CBC ; $1F801CBC..$1F801CBD SPU Voice Registers: Voice 11 ADSR Current Volume 2B/RW
SPUADSRVOL12 equ 0x1CCC ; $1F801CCC..$1F801CCD SPU Voice Registers: Voice 12 ADSR Current Volume 2B/RW
SPUADSRVOL13 equ 0x1CDC ; $1F801CDC..$1F801CDD SPU Voice Registers: Voice 13 ADSR Current Volume 2B/RW
SPUADSRVOL14 equ 0x1CEC ; $1F801CEC..$1F801CED SPU Voice Registers: Voice 14 ADSR Current Volume 2B/RW
SPUADSRVOL15 equ 0x1CFC ; $1F801CFC..$1F801CFD SPU Voice Registers: Voice 15 ADSR Current Volume 2B/RW
SPUADSRVOL16 equ 0x1D0C ; $1F801D0C..$1F801D0D SPU Voice Registers: Voice 16 ADSR Current Volume 2B/RW
SPUADSRVOL17 equ 0x1D1C ; $1F801D1C..$1F801D1D SPU Voice Registers: Voice 17 ADSR Current Volume 2B/RW
SPUADSRVOL18 equ 0x1D2C ; $1F801D2C..$1F801D2D SPU Voice Registers: Voice 18 ADSR Current Volume 2B/RW
SPUADSRVOL19 equ 0x1D3C ; $1F801D3C..$1F801D3D SPU Voice Registers: Voice 19 ADSR Current Volume 2B/RW
SPUADSRVOL20 equ 0x1D4C ; $1F801D4C..$1F801D4D SPU Voice Registers: Voice 20 ADSR Current Volume 2B/RW
SPUADSRVOL21 equ 0x1D5C ; $1F801D5C..$1F801D5D SPU Voice Registers: Voice 21 ADSR Current Volume 2B/RW
SPUADSRVOL22 equ 0x1D6C ; $1F801D6C..$1F801D6D SPU Voice Registers: Voice 22 ADSR Current Volume 2B/RW
SPUADSRVOL23 equ 0x1D7C ; $1F801D7C..$1F801D7D SPU Voice Registers: Voice 23 ADSR Current Volume 2B/RW
SPULOOP0 equ 0x1C0E ; $1F801C0E..$1F801C0F SPU Voice Registers: Voice 0 ADPCM Repeat Address 2B/RW
SPULOOP1 equ 0x1C1E ; $1F801C1E..$1F801C1F SPU Voice Registers: Voice 1 ADPCM Repeat Address 2B/RW
SPULOOP2 equ 0x1C2E ; $1F801C2E..$1F801C2F SPU Voice Registers: Voice 2 ADPCM Repeat Address 2B/RW
SPULOOP3 equ 0x1C3E ; $1F801C3E..$1F801C3F SPU Voice Registers: Voice 3 ADPCM Repeat Address 2B/RW
SPULOOP4 equ 0x1C4E ; $1F801C4E..$1F801C4F SPU Voice Registers: Voice 4 ADPCM Repeat Address 2B/RW
SPULOOP5 equ 0x1C5E ; $1F801C5E..$1F801C5F SPU Voice Registers: Voice 5 ADPCM Repeat Address 2B/RW
SPULOOP6 equ 0x1C6E ; $1F801C6E..$1F801C6F SPU Voice Registers: Voice 6 ADPCM Repeat Address 2B/RW
SPULOOP7 equ 0x1C7E ; $1F801C7E..$1F801C7F SPU Voice Registers: Voice 7 ADPCM Repeat Address 2B/RW
SPULOOP8 equ 0x1C8E ; $1F801C8E..$1F801C8F SPU Voice Registers: Voice 8 ADPCM Repeat Address 2B/RW
SPULOOP9 equ 0x1C9E ; $1F801C9E..$1F801C9F SPU Voice Registers: Voice 9 ADPCM Repeat Address 2B/RW
SPULOOP10 equ 0x1CAE ; $1F801CAE..$1F801CAF SPU Voice Registers: Voice 10 ADPCM Repeat Address 2B/RW
SPULOOP11 equ 0x1CBE ; $1F801CBE..$1F801CBF SPU Voice Registers: Voice 11 ADPCM Repeat Address 2B/RW
SPULOOP12 equ 0x1CCE ; $1F801CCE..$1F801CCF SPU Voice Registers: Voice 12 ADPCM Repeat Address 2B/RW
SPULOOP13 equ 0x1CDE ; $1F801CDE..$1F801CDF SPU Voice Registers: Voice 13 ADPCM Repeat Address 2B/RW
SPULOOP14 equ 0x1CEE ; $1F801CEE..$1F801CEF SPU Voice Registers: Voice 14 ADPCM Repeat Address 2B/RW
SPULOOP15 equ 0x1CFE ; $1F801CFE..$1F801CFF SPU Voice Registers: Voice 15 ADPCM Repeat Address 2B/RW
SPULOOP16 equ 0x1D0E ; $1F801D0E..$1F801D0F SPU Voice Registers: Voice 16 ADPCM Repeat Address 2B/RW
SPULOOP17 equ 0x1D1E ; $1F801D1E..$1F801D1F SPU Voice Registers: Voice 17 ADPCM Repeat Address 2B/RW
SPULOOP18 equ 0x1D2E ; $1F801D2E..$1F801D2F SPU Voice Registers: Voice 18 ADPCM Repeat Address 2B/RW
SPULOOP19 equ 0x1D3E ; $1F801D3E..$1F801D3F SPU Voice Registers: Voice 19 ADPCM Repeat Address 2B/RW
SPULOOP20 equ 0x1D4E ; $1F801D4E..$1F801D4F SPU Voice Registers: Voice 20 ADPCM Repeat Address 2B/RW
SPULOOP21 equ 0x1D5E ; $1F801D5E..$1F801D5F SPU Voice Registers: Voice 21 ADPCM Repeat Address 2B/RW
SPULOOP22 equ 0x1D6E ; $1F801D6E..$1F801D6F SPU Voice Registers: Voice 22 ADPCM Repeat Address 2B/RW
SPULOOP23 equ 0x1D7E ; $1F801D7E..$1F801D7F SPU Voice Registers: Voice 23 ADPCM Repeat Address 2B/RW
; SPU Control Registers
SPUMVOL equ 0x1D80 ; $1F801D80..$1F801D83 SPU Control Registers: Main Volume Left/Right 4B/RW
SPUEVOL equ 0x1D84 ; $1F801D84..$1F801D87 SPU Control Registers: Echo/Reverb Output Volume Left/Right 4B/RW
SPUKON equ 0x1D88 ; $1F801D88..$1F801D8B SPU Control Registers: Voice 0..23 Key ON (Start Attack/Decay/Sustain) 4B/W
SPUKOFF equ 0x1D8C ; $1F801D8C..$1F801D8F SPU Control Registers: Voice 0..23 Key OFF (Start Release) 4B/W
SPUPMON equ 0x1D90 ; $1F801D90..$1F801D93 SPU Control Registers: Voice 1..23 Pitch Modulation Enable Flags 4B/RW
SPUNON equ 0x1D94 ; $1F801D94..$1F801D97 SPU Control Registers: Voice 0..23 Channel Noise Enable Flags 4B/RW
SPUEON equ 0x1D98 ; $1F801D98..$1F801D9B SPU Control Registers: Voice 0..23 Channel Echo/Reverb Enable Flags 4B/RW
SPUENDX equ 0x1D9C ; $1F801D9C..$1F801D9F SPU Control Registers: Voice 0..23 Channel ON/OFF (Status) 4B/R
SPUUNK1 equ 0x1DA0 ; $1F801DA0..$1F801DA1 SPU Control Registers: Unknown/Unused 2B/RW
SPUEBASE equ 0x1DA2 ; $1F801DA2..$1F801DA3 SPU Control Registers: Sound RAM Echo/Reverb Work Area Start Address 2B/RW
SPUIRQ equ 0x1DA4 ; $1F801DA4..$1F801DA5 SPU Control Registers: Sound RAM IRQ Address 2B/RW
SPUDBASE equ 0x1DA6 ; $1F801DA6..$1F801DA7 SPU Control Registers: Sound RAM Data Transfer Address 2B/RW
SPUDFIFO equ 0x1DA8 ; $1F801DA8..$1F801DA9 SPU Control Registers: Sound RAM Data Transfer Fifo 2B/RW
SPUCNT equ 0x1DAA ; $1F801DAA..$1F801DAB SPU Control Registers: SPU Control Register 2B/RW
SPUDCNT equ 0x1DAC ; $1F801DAC..$1F801DAD SPU Control Registers: Sound RAM Data Transfer Control (Should Be $0004) 2B/RW
SPUSTAT equ 0x1DAE ; $1F801DAE..$1F801DAF SPU Control Registers: SPU Status Register 2B/R
SPUCDVOL equ 0x1DB0 ; $1F801DB0..$1F801DB3 SPU Control Registers: CD Volume Left/Right (CD-DA & Compressed XA-ADPCM) 4B/RW
SPUEXVOL equ 0x1DB4 ; $1F801DB4..$1F801DB7 SPU Control Registers: External Audio Input Volume Left/Right 4B/RW
SPUCMVOL equ 0x1DB8 ; $1F801DB8..$1F801DBB SPU Control Registers: Current Main Volume Left/Right 4B/RW
SPUUNK2 equ 0x1DBC ; $1F801DBC..$1F801DBF SPU Control Registers: Unknown/Unused 4B/RW
; SPU Echo/Reverb Configuration Area
SPUDAPF1 equ 0x1DC0 ; $1F801DC0..$1F801DC1 SPU Echo/Reverb Configuration Area: APF Offset 1 2B/RW
SPUDAPF2 equ 0x1DC2 ; $1F801DC2..$1F801DC3 SPU Echo/Reverb Configuration Area: APF Offset 2 2B/RW
SPUVIIR equ 0x1DC4 ; $1F801DC4..$1F801DC5 SPU Echo/Reverb Configuration Area: Reflection Volume 1 2B/RW
SPUVCOMB1 equ 0x1DC6 ; $1F801DC6..$1F801DC7 SPU Echo/Reverb Configuration Area: Comb Volume 1 2B/RW
SPUVCOMB2 equ 0x1DC8 ; $1F801DC8..$1F801DC9 SPU Echo/Reverb Configuration Area: Comb Volume 2 2B/RW
SPUVCOMB3 equ 0x1DCA ; $1F801DCA..$1F801DCB SPU Echo/Reverb Configuration Area: Comb Volume 3 2B/RW
SPUVCOMB4 equ 0x1DCC ; $1F801DCC..$1F801DCD SPU Echo/Reverb Configuration Area: Comb Volume 4 2B/RW
SPUVWALL equ 0x1DCE ; $1F801DCE..$1F801DCF SPU Echo/Reverb Configuration Area: Reflection Volume 2 2B/RW
SPUVAPF1 equ 0x1DD0 ; $1F801DD0..$1F801DD1 SPU Echo/Reverb Configuration Area: APF Volume 1 2B/RW
SPUVAPF2 equ 0x1DD2 ; $1F801DD2..$1F801DD3 SPU Echo/Reverb Configuration Area: APF Volume 2 2B/RW
SPUMSAME equ 0x1DD4 ; $1F801DD4..$1F801DD7 SPU Echo/Reverb Configuration Area: Same Side Reflection Address 1 Left/Right 4B/RW
SPUMCOMB1 equ 0x1DD8 ; $1F801DD8..$1F801DDB SPU Echo/Reverb Configuration Area: Comb Address 1 Left/Right 4B/RW
SPUMCOMB2 equ 0x1DDC ; $1F801DDC..$1F801DDF SPU Echo/Reverb Configuration Area: Comb Address 2 Left/Right 4B/RW
SPUDSAME equ 0x1DE0 ; $1F801DE0..$1F801DE3 SPU Echo/Reverb Configuration Area: Same Side Reflection Address 2 Left/Right 4B/RW
SPUMDIFF equ 0x1DE4 ; $1F801DE4..$1F801DE7 SPU Echo/Reverb Configuration Area: Diff Side Reflection Address 1 Left/Right 4B/RW
SPUMCOMB3 equ 0x1DE8 ; $1F801DE8..$1F801DEB SPU Echo/Reverb Configuration Area: Comb Address 3 Left/Right 4B/RW
SPUMCOMB4 equ 0x1DEC ; $1F801DEC..$1F801DEF SPU Echo/Reverb Configuration Area: Comb Address 4 Left/Right 4B/RW
SPUDDIFF equ 0x1DF0 ; $1F801DF0..$1F801DF3 SPU Echo/Reverb Configuration Area: Diff Side Reflection Address 2 Left/Right 4B/RW
SPUMAPF1 equ 0x1DF4 ; $1F801DF4..$1F801DF7 SPU Echo/Reverb Configuration Area: APF Address 1 Left/Right 4B/RW
SPUMAPF2 equ 0x1DF8 ; $1F801DF8..$1F801DFB SPU Echo/Reverb Configuration Area: APF Address 2 Left/Right 4B/RW
SPUVIN equ 0x1DFC ; $1F801DFC..$1F801DFF SPU Echo/Reverb Configuration Area: Input Volume Left/Right 4B/RW
; SPU Internal Registers
SPUCVOL0 equ 0x1E00 ; $1F801E00..$1F801E03 SPU Internal Registers: Voice 0 Current Volume Left/Right 4B/RW
SPUCVOL1 equ 0x1E04 ; $1F801E04..$1F801E07 SPU Internal Registers: Voice 1 Current Volume Left/Right 4B/RW
SPUCVOL2 equ 0x1E08 ; $1F801E08..$1F801E0B SPU Internal Registers: Voice 2 Current Volume Left/Right 4B/RW
SPUCVOL3 equ 0x1E0C ; $1F801E0C..$1F801E0F SPU Internal Registers: Voice 3 Current Volume Left/Right 4B/RW
SPUCVOL4 equ 0x1E10 ; $1F801E10..$1F801E13 SPU Internal Registers: Voice 4 Current Volume Left/Right 4B/RW
SPUCVOL5 equ 0x1E14 ; $1F801E14..$1F801E17 SPU Internal Registers: Voice 5 Current Volume Left/Right 4B/RW
SPUCVOL6 equ 0x1E18 ; $1F801E18..$1F801E1B SPU Internal Registers: Voice 6 Current Volume Left/Right 4B/RW
SPUCVOL7 equ 0x1E1C ; $1F801E1C..$1F801E1F SPU Internal Registers: Voice 7 Current Volume Left/Right 4B/RW
SPUCVOL8 equ 0x1E20 ; $1F801E20..$1F801E23 SPU Internal Registers: Voice 8 Current Volume Left/Right 4B/RW
SPUCVOL9 equ 0x1E24 ; $1F801E24..$1F801E27 SPU Internal Registers: Voice 9 Current Volume Left/Right 4B/RW
SPUCVOL10 equ 0x1E28 ; $1F801E28..$1F801E2B SPU Internal Registers: Voice 10 Current Volume Left/Right 4B/RW
SPUCVOL11 equ 0x1E2C ; $1F801E2C..$1F801E2F SPU Internal Registers: Voice 11 Current Volume Left/Right 4B/RW
SPUCVOL12 equ 0x1E30 ; $1F801E30..$1F801E33 SPU Internal Registers: Voice 12 Current Volume Left/Right 4B/RW
SPUCVOL13 equ 0x1E34 ; $1F801E34..$1F801E37 SPU Internal Registers: Voice 13 Current Volume Left/Right 4B/RW
SPUCVOL14 equ 0x1E38 ; $1F801E38..$1F801E3B SPU Internal Registers: Voice 14 Current Volume Left/Right 4B/RW
SPUCVOL15 equ 0x1E3C ; $1F801E3C..$1F801E3F SPU Internal Registers: Voice 15 Current Volume Left/Right 4B/RW
SPUCVOL16 equ 0x1E40 ; $1F801E40..$1F801E43 SPU Internal Registers: Voice 16 Current Volume Left/Right 4B/RW
SPUCVOL17 equ 0x1E44 ; $1F801E44..$1F801E47 SPU Internal Registers: Voice 17 Current Volume Left/Right 4B/RW
SPUCVOL18 equ 0x1E48 ; $1F801E48..$1F801E4B SPU Internal Registers: Voice 18 Current Volume Left/Right 4B/RW
SPUCVOL19 equ 0x1E4C ; $1F801E4C..$1F801E4F SPU Internal Registers: Voice 19 Current Volume Left/Right 4B/RW
SPUCVOL20 equ 0x1E50 ; $1F801E50..$1F801E53 SPU Internal Registers: Voice 20 Current Volume Left/Right 4B/RW
SPUCVOL21 equ 0x1E54 ; $1F801E54..$1F801E57 SPU Internal Registers: Voice 21 Current Volume Left/Right 4B/RW
SPUCVOL22 equ 0x1E58 ; $1F801E58..$1F801E5B SPU Internal Registers: Voice 22 Current Volume Left/Right 4B/RW
SPUCVOL23 equ 0x1E5C ; $1F801E5C..$1F801E5F SPU Internal Registers: Voice 23 Current Volume Left/Right 4B/RW
SPUUNK3 equ 0x1E60 ; $1F801E60..$1F801E7F SPU Internal Registers: Unknown/Unused 32B/RW
SPUUNK4 equ 0x1E80 ; $1F801E80..$1F801FFF SPU Internal Registers: Unknown/Unused (Read: $FF Filled) 384B/RW
; Expansion Region 2 (Default 128B, Max 8KB)
EXP2_BASE equ 0x1F802000 ; $1F802000..$1F80207F Expansion Region 2: Expansion Region (8-Bit Data BUS) 128B/RW
; Expansion Region 3 (Default 1B, Max 2MB)
EXP3_BASE equ 0x1FA00000 ; $1FA00000..$1FA00000 Expansion Region 3: Expansion Region (Not Used By BIOS Or Any PSX Games) 1B/RW
; BIOS Region (Default 512KB, Max 4MB)
BIOS_BASE equ 0x1FC00000 ; $1FC00000..$1FC001FF BIOS Region: BIOS ROM (Reset Entrypoint At $BFC00000) 512KB/R
; Memory Control 3 (Cache Control)
CACHE_CTRL equ 0xFFFE0130 ; $FFFE0130..$FFFE0133 Memory Control 3: Cache Control 4B/RW
; Macros
.macro CLIOH,IOREG ; Clear I/O Port Register Half (A0 = IO_BASE 0x1F800000)
sh r0,IOREG(a0) ; I/O Port Register Half = 0
.endmacro
.macro CLIOW,IOREG ; Clear I/O Port Register Word (A0 = IO_BASE 0x1F800000)
sw r0,IOREG(a0) ; I/O Port Register Word = 0
.endmacro
.macro RDIOH,IOREG,REG ; Read I/O Port Register Half (A0 = IO_BASE 0x1F800000)
lhu REG,IOREG(a0) ; Register = I/O Port Register Half
nop ; Delay Slot
.endmacro
.macro RDIOW,IOREG,REG ; Read I/O Port Register Word (A0 = IO_BASE 0x1F800000)
lw REG,IOREG(a0) ; Register = I/O Port Register Word
nop ; Delay Slot
.endmacro
.macro WRIOH,IOREG,DATA ; Write I/O Port Register Half (A0 = IO_BASE 0x1F800000)
li t0,DATA ; T0 = DATA Half
sh t0,IOREG(a0) ; I/O Port Register Half = T0
.endmacro
.macro WRIOW,IOREG,DATA ; Write I/O Port Register Word (A0 = IO_BASE 0x1F800000)
li t0,DATA ; T0 = DATA Word
sw t0,IOREG(a0) ; I/O Port Register Word = T0
.endmacro

2297
BouncyCubePs1.asm/LIB/PSX_GPU.INC Normal file
View File

File diff suppressed because it is too large Load Diff

211
BouncyCubePs1.asm/LIB/PSX_GTE.INC Normal file
View File

@ -0,0 +1,211 @@
;================
; PSX GTE (COP2)
;================
;========================================================================================
; GTE Registers (Use: Data (R0..R31) lwc2,swc2,mfc2,mtc2 / Control (R32..R63) cfc2,ctc2)
;========================================================================================
; GTE Registers - 16-Bit Vectors
; VXY0 equ r0 ; GTE R0 - 16-Bit Vectors: Vector XY 0 (V0) - Bit 0..15 = VX0 (S.15.0), Bit 16..31 VY0 (S.15.0)
; VZ0 equ r1 ; GTE R1 - 16-Bit Vectors: Vector Z 0 (V0) - Bit 0..15 = VZ0 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; VXY1 equ r2 ; GTE R2 - 16-Bit Vectors: Vector XY 1 (V1) - Bit 0..15 = VX1 (S.15.0), Bit 16..31 VY1 (S.15.0)
; VZ1 equ r3 ; GTE R3 - 16-Bit Vectors: Vector Z 1 (V1) - Bit 0..15 = VZ1 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; VXY2 equ r4 ; GTE R4 - 16-Bit Vectors: Vector XY 2 (V2) - Bit 0..15 = VX2 (S.15.0), Bit 16..31 VY2 (S.15.0)
; VZ2 equ r5 ; GTE R5 - 16-Bit Vectors: Vector Z 2 (V2) - Bit 0..15 = VZ2 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; IR1 equ r9 ; GTE R9 - 16-Bit Vectors: Vector 3 (IR) - Bit 0..15 = IR1 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; IR2 equ r10 ; GTE R10 - 16-Bit Vectors: Vector 3 (IR) - Bit 0..15 = IR2 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; IR3 equ r11 ; GTE R11 - 16-Bit Vectors: Vector 3 (IR) - Bit 0..15 = IR3 (S.15.0) (Returns Sign-Expanded 32-Bit Value)
; GTE Registers - Interpolation Factor
; IR0 equ r8 ; GTE R8 - Interpolation Factor: Intermediate Value 0 (IR0) - Bit 0..15 = IR0 (S.3.12) (Returns Sign-Expanded 32-Bit Value)
; GTE Registers - Screen XYZ Coordinate FIFO
; SXY0 equ r12 ; GTE R12 - Screen XYZ Coordinate FIFO: Screen XY 0 FIFO (Older) - Bit 0..15 = SX0 (S.15.0), Bit 16..31 SY0 (S.15.0)
; SXY1 equ r13 ; GTE R13 - Screen XYZ Coordinate FIFO: Screen XY 1 FIFO (Old) - Bit 0..15 = SX1 (S.15.0), Bit 16..31 SY1 (S.15.0)
; SXY2 equ r14 ; GTE R14 - Screen XYZ Coordinate FIFO: Screen XY 2 FIFO (New) - Bit 0..15 = SX2 (S.15.0), Bit 16..31 SY2 (S.15.0)
; SXYP equ r15 ; GTE R15 - Screen XYZ Coordinate FIFO: Screen XY 2 FIFO (Mirror) - Bit 0..15 = SXP (S.15.0), Bit 16..31 SYP (S.15.0) (Move-On-Write)
; SZ0 equ r16 ; GTE R16 - Screen XYZ Coordinate FIFO: Screen Z 0 FIFO (Oldest) - Bit 0..15 = SZ0 (16.0)
; SZ1 equ r17 ; GTE R17 - Screen XYZ Coordinate FIFO: Screen Z 1 FIFO (Older) - Bit 0..15 = SZ1 (16.0)
; SZ2 equ r18 ; GTE R18 - Screen XYZ Coordinate FIFO: Screen Z 2 FIFO (Old) - Bit 0..15 = SZ2 (16.0)
; SZ3 equ r19 ; GTE R19 - Screen XYZ Coordinate FIFO: Screen Z 3 FIFO (New) - Bit 0..15 = SZ3 (16.0)
; GTE Registers - Color Register & Color FIFO
; RGBC equ r6 ; GTE R6 - Color Register & Color FIFO: Color/Code Value (RGBC) - Bit 0..7 = R, Bit 8..15 = G, Bit 16..23 = B, Bit 24..31 = CODE
; RGB0 equ r20 ; GTE R20 - Color Register & Color FIFO: Characteristic Color FIFO 0 (RGB0) - Bit 0..7 = R0, Bit 8..15 = G0, Bit 16..23 = B0, Bit 24..31 = CD0
; RGB1 equ r21 ; GTE R21 - Color Register & Color FIFO: Characteristic Color FIFO 1 (RGB1) - Bit 0..7 = R1, Bit 8..15 = G1, Bit 16..23 = B1, Bit 24..31 = CD1
; RGB2 equ r22 ; GTE R22 - Color Register & Color FIFO: Characteristic Color FIFO 2 (RGB2) - Bit 0..7 = R2, Bit 8..15 = G2, Bit 16..23 = B2, Bit 24..31 = CD2
; RES1 equ r23 ; GTE R23 - Color Register and Color FIFO: Reserved (R/W)
; GTE Registers - 32-Bit Maths Accumulator/Sum Of Product
; MAC0 equ r24 ; GTE R24 - Maths Accumulator/Sum Of Product: Value 0 (MAC0) - Bit 0..31 = MAC0 (S.31.0)
; MAC1 equ r25 ; GTE R25 - Maths Accumulator/Sum Of Product: Vector 1 (MAC1) - Bit 0..31 = MAC1 (S.31.0)
; MAC2 equ r26 ; GTE R26 - Maths Accumulator/Sum Of Product: Vector 2 (MAC2) - Bit 0..31 = MAC2 (S.31.0)
; MAC3 equ r27 ; GTE R27 - Maths Accumulator/Sum Of Product: Vector 3 (MAC3) - Bit 0..31 = MAC3 (S.31.0)
; GTE Registers - Color Conversion R,G,B (48-Bit/15-Bit)
; IRGB equ r28 ; GTE R28 - Color Conversion: Input (IRGB) - Bit 0..4 = Red, Bit 5..9 = Green, Bit 10..14 = Blue, Bit 15-31 = Zero (Not Used)
; ORGB equ r29 ; GTE R29 - Color Conversion: Output (IRGB) - Bit 0..4 = Red, Bit 5..9 = Green, Bit 10..14 = Blue, Bit 15-31 = Zero (Not Used)
; GTE Registers - Count Leading-Zero/One (Sign Bits)
; LZCS equ r30 ; GTE R30 - Count Leading-Zero/One: Source (LZCS) - Bit 0..31 = LZCS
; LZCR equ r31 ; GTE R31 - Count Leading-Zero/One: Result (LZCR) - Bit 0..31 = LZCR
; GTE Registers - Matrix (3x3)
; RT0 equ r0 ; GTE R32 - Matrix: Rotation (RT/CNT00) - Bit 0..15 = RT11 (S.3.12), Bit 16..31 RT12 (S.3.12)
; RT1 equ r1 ; GTE R33 - Matrix: Rotation (RT/CNT01) - Bit 0..15 = RT13 (S.3.12), Bit 16..31 RT21 (S.3.12)
; RT2 equ r2 ; GTE R34 - Matrix: Rotation (RT/CNT02) - Bit 0..15 = RT22 (S.3.12), Bit 16..31 RT23 (S.3.12)
; RT3 equ r3 ; GTE R35 - Matrix: Rotation (RT/CNT03) - Bit 0..15 = RT31 (S.3.12), Bit 16..31 RT32 (S.3.12)
; RT4 equ r4 ; GTE R36 - Matrix: Rotation (RT/CNT04) - Bit 0..15 = RT33 (S.3.12) (Returns Sign-Expanded 32-Bit Value)
; LLM0 equ r8 ; GTE R40 - Matrix: Light Source (LLM/CNT08) - Bit 0..15 = L11 (S.3.12), Bit 16..31 L12 (S.3.12)
; LLM1 equ r9 ; GTE R41 - Matrix: Light Source (LLM/CNT09) - Bit 0..15 = L13 (S.3.12), Bit 16..31 L21 (S.3.12)
; LLM2 equ r10 ; GTE R42 - Matrix: Light Source (LLM/CNT10) - Bit 0..15 = L22 (S.3.12), Bit 16..31 L23 (S.3.12)
; LLM3 equ r11 ; GTE R43 - Matrix: Light Source (LLM/CNT11) - Bit 0..15 = L31 (S.3.12), Bit 16..31 L32 (S.3.12)
; LLM4 equ r12 ; GTE R44 - Matrix: Light Source (LLM/CNT12) - Bit 0..15 = L33 (S.3.12) (Returns Sign-Expanded 32-Bit Value)
; LCM0 equ r16 ; GTE R48 - Matrix: Light Color (LCM/CNT16) - Bit 0..15 = LR1 (S.3.12), Bit 16..31 LR2 (S.3.12)
; LCM1 equ r17 ; GTE R49 - Matrix: Light Color (LCM/CNT17) - Bit 0..15 = LR3 (S.3.12), Bit 16..31 LG1 (S.3.12)
; LCM2 equ r18 ; GTE R50 - Matrix: Light Color (LCM/CNT18) - Bit 0..15 = LG2 (S.3.12), Bit 16..31 LG3 (S.3.12)
; LCM3 equ r19 ; GTE R51 - Matrix: Light Color (LCM/CNT19) - Bit 0..15 = LB1 (S.3.12), Bit 16..31 LB2 (S.3.12)
; LCM4 equ r20 ; GTE R52 - Matrix: Light Color (LCM/CNT20) - Bit 0..15 = LB3 (S.3.12) (Returns Sign-Expanded 32-Bit Value)
; GTE Registers - Translation Vector X,Y,Z (TR)
; TRX equ r5 ; GTE R37 - Translation Vector: X (TRX/CNT05) - Bit 0..31 = TRX (S.31.0)
; TRY equ r6 ; GTE R38 - Translation Vector: Y (TRY/CNT06) - Bit 0..31 = TRY (S.31.0)
; TRZ equ r7 ; GTE R39 - Translation Vector: Z (TRZ/CNT07) - Bit 0..31 = TRZ (S.31.0)
; GTE Registers - Background Color R,G,B (BK)
; RBK equ r13 ; GTE R45 - Background Color: Red Component (RBK/CNT13) - Bit 0..31 = RBK (S.19.12)
; GBK equ r14 ; GTE R46 - Background Color: Green Component (GBK/CNT14) - Bit 0..31 = GBK (S.19.12)
; BBK equ r15 ; GTE R47 - Background Color: Blue Component (BBK/CNT15) - Bit 0..31 = BBK (S.19.12)
; GTE Registers - Far Color R,G,B (FC)
; RFC equ r21 ; GTE R53 - Far Color: Red Component (RFC/CNT21) - Bit 0..31 = RFC (S.27.4)
; GFC equ r22 ; GTE R54 - Far Color: Green Component (GFC/CNT22) - Bit 0..31 = GFC (S.27.4)
; BFC equ r23 ; GTE R55 - Far Color: Blue Component (BFC/CNT23) - Bit 0..31 = BFC (S.27.4)
; GTE Registers - Screen Offset & Distance
; OFX equ r24 ; GTE R56 - Screen Offset & Distance: Screen Offset X (OFX/CNT24) - Bit 0..31 = OFX (S.15.16)
; OFY equ r25 ; GTE R57 - Screen Offset & Distance: Screen Offset Y (OFY/CNT25) - Bit 0..31 = OFY (S.15.16)
; H equ r26 ; GTE R58 - Screen Offset & Distance: Projection Plane Distance (H/CNT26) - Bit 0..15 = H (16.0) (Returns Sign-Expanded 32-Bit Value)
; DQA equ r27 ; GTE R59 - Screen Offset & Distance: Depth Queing Parameter A. (Coefficient) (DQA/CNT27) - Bit 0..15 = DQA (S.7.8)
; DQB equ r28 ; GTE R60 - Screen Offset & Distance: Depth Queing Parameter A. (Offset) (DQB/CNT28) - Bit 0..31 = DQB (S.7.24)
; GTE Registers - Average Z Factors
; ZSF3 equ r29 ; GTE R61 - Average Z: Z3 Average Scale Factor (Normally 1/3) (ZSF3/CNT29) - Bit 0..15 = ZSF3 (S.3.12)
; ZSF4 equ r30 ; GTE R62 - Average Z: Z4 Average Scale Factor (Normally 1/4) (ZSF4/CNT30) - Bit 0..15 = ZSF4 (S.3.12)
; OTZ equ r7 ; GTE R7 - Average Z Registers: Average Z Value (Ordering Table) (OTZ) - Bit 0..15 = OTZ (16.0)
; GTE Registers - Error Flag
; FLAG equ r31 ; GTE R63 - Error Flag: Returns Calculation Errors (FLAG/CNT31) - Bit 0..31 = FLAG
;====================================
; GTE Commands (Use: "cop2 command")
;====================================
; GTE Coordinate Calculation Commands
RTPS equ 0x0180001 ; GTE Coordinate Calculation Commands: Perspective Transformation (Single) - 15 Cycles
RTPT equ 0x0280030 ; GTE Coordinate Calculation Commands: Perspective Transformation (Triple) - 23 Cycles
NCLIP equ 0x1400006 ; GTE Coordinate Calculation Commands: Normal Clipping - 8 Cycles
AVSZ3 equ 0x158002D ; GTE Coordinate Calculation Commands: Average Three Z Values (Triangle) - 5 Cycles
AVSZ4 equ 0x168002E ; GTE Coordinate Calculation Commands: Average Four Z Values (Quad) - 6 Cycles
; GTE General Purpose Calculation Commands
MVMVA equ 0x0400012 ; GTE General Purpose Calculation Commands: Multiply Vector By Matrix With Vector Addition - 8 Cycles
SQR equ 0x0A00428 ; GTE General Purpose Calculation Commands: Calculate Square Of Vector (Result Always Positive) - 5 Cycles
OP equ 0x170000C ; GTE General Purpose Calculation Commands: Calculate Outer Product Of Two Signed 16-Bit Vectors - 6 Cycles
; GTE Color Calculation Commands
NCS equ 0x0C8041E ; GTE Color Calculation Commands: Normal Color (Single) - 14 Cycles
NCT equ 0x0D80420 ; GTE Color Calculation Commands: Normal Color (Triple) - 30 Cycles
NCCS equ 0x108041B ; GTE Color Calculation Commands: Normal Color Color (Single Vector) - 17 Cycles
NCCT equ 0x118043F ; GTE Color Calculation Commands: Normal Color Color (Triple Vector) - 39 Cycles
NCDS equ 0x0E80413 ; GTE Color Calculation Commands: Normal Color Depth Cue (Single Vector) - 19 Cycles
NCDT equ 0x0F80416 ; GTE Color Calculation Commands: Normal Color Depth Cue (Triple Vector) - 44 Cycles
CC equ 0x138041C ; GTE Color Calculation Commands: Color Color - 11 Cycles
CDP equ 0x1280414 ; GTE Color Calculation Commands: Color Depth Cue - 13 Cycles
DCPL equ 0x0680029 ; GTE Color Calculation Commands: Depth Cue Color Light - 8 Cycles
DPCS equ 0x0780010 ; GTE Color Calculation Commands: Depth Cueing (Single) - 8 Cycles
DPCT equ 0x088002A ; GTE Color Calculation Commands: Depth Cueing (Triple) - 17 Cycles
INTPL equ 0x0980011 ; GTE Color Calculation Commands: Interpolation Of Vector & Far Color - 8 Cycles
GPF equ 0x190003D ; GTE Color Calculation Commands: General Purpose Interpolation - 5 Cycles
GPL equ 0x1A0003E ; GTE Color Calculation Commands: General Purpose Interpolation With Base - 5 Cycles
; GTE MVMVA (Multiply Vector By Matrix With Vector Addition) Command Instructions
RTV0 equ 0x0486012 ; GTE MVMVA Command: Vector 0 (V0) * Rotation Matrix (RT) - 8 Cycles
RTV1 equ 0x048E012 ; GTE MVMVA Command: Vector 1 (V1) * Rotation Matrix (RT) - 8 Cycles
RTV2 equ 0x0496012 ; GTE MVMVA Command: Vector 2 (V2) * Rotation Matrix (RT) - 8 Cycles
RTIR12 equ 0x049E012 ; GTE MVMVA Command: Vector 3 (IR) * Rotation Matrix (RT) - 8 Cycles
RTIR0 equ 0x041E012 ; GTE MVMVA Command: Intermediate Value 0 (IR0) * Rotation Matrix (RT) - 8 Cycles
RTV0TR equ 0x0480012 ; GTE MVMVA Command: Vector 0 (V0) * Rotation Matrix (RT) + Translation Vector (TR) - 8 Cycles
RTV1TR equ 0x0488012 ; GTE MVMVA Command: Vector 1 (V1) * Rotation Matrix (RT) + Translation Vector (TR) - 8 Cycles
RTV2TR equ 0x0490012 ; GTE MVMVA Command: Vector 2 (V2) * Rotation Matrix (RT) + Translation Vector (TR) - 8 Cycles
RTIRTR equ 0x0498012 ; GTE MVMVA Command: Vector 3 (IR) * Rotation Matrix (RT) + Translation Vector (TR) - 8 Cycles
RTV0BK equ 0x0482012 ; GTE MVMVA Command: Vector 0 (V0) * Rotation Matrix (RT) + Background Color Vector (BK) - 8 Cycles
RTV1BK equ 0x048A012 ; GTE MVMVA Command: Vector 1 (V1) * Rotation Matrix (RT) + Background Color Vector (BK) - 8 Cycles
RTV2BK equ 0x0492012 ; GTE MVMVA Command: Vector 2 (V2) * Rotation Matrix (RT) + Background Color Vector (BK) - 8 Cycles
RTIRBK equ 0x049A012 ; GTE MVMVA Command: Vector 3 (IR) * Rotation Matrix (RT) + Background Color Vector (BK) - 8 Cycles
LL equ 0x04A6412 ; GTE MVMVA Command: Vector 0 (V0) * Light Source Matrix (LLM) (Lower Limit Result 0) - 8 Cycles
LLV0 equ 0x04A6012 ; GTE MVMVA Command: Vector 0 (V0) * Light Source Matrix (LLM) - 8 Cycles
LLV1 equ 0x04AE012 ; GTE MVMVA Command: Vector 1 (V1) * Light Source Matrix (LLM) - 8 Cycles
LLV2 equ 0x04B6012 ; GTE MVMVA Command: Vector 2 (V2) * Light Source Matrix (LLM) - 8 Cycles
LLIR equ 0x04BE012 ; GTE MVMVA Command: Vector 3 (IR) * Light Source Matrix (LLM) - 8 Cycles
LLV0TR equ 0x04A0012 ; GTE MVMVA Command: Vector 0 (V0) * Light Source Matrix (LLM) + Translation Vector (TR) - 8 Cycles
LLV1TR equ 0x04A8012 ; GTE MVMVA Command: Vector 1 (V1) * Light Source Matrix (LLM) + Translation Vector (TR) - 8 Cycles
LLV2TR equ 0x04B0012 ; GTE MVMVA Command: Vector 2 (V2) * Light Source Matrix (LLM) + Translation Vector (TR) - 8 Cycles
LLIRTR equ 0x04B8012 ; GTE MVMVA Command: Vector 3 (IR) * Light Source Matrix (LLM) + Translation Vector (TR) - 8 Cycles
LLV0BK equ 0x04A2012 ; GTE MVMVA Command: Vector 0 (V0) * Light Source Matrix (LLM) + Background Color Vector (BK) - 8 Cycles
LLV1BK equ 0x04AA012 ; GTE MVMVA Command: Vector 1 (V1) * Light Source Matrix (LLM) + Background Color Vector (BK) - 8 Cycles
LLV2BK equ 0x04B2012 ; GTE MVMVA Command: Vector 2 (V2) * Light Source Matrix (LLM) + Background Color Vector (BK) - 8 Cycles
LLIRBK equ 0x04BA012 ; GTE MVMVA Command: Vector 3 (IR) * Light Source Matrix (LLM) + Background Color Vector (BK) - 8 Cycles
LC equ 0x04DA412 ; GTE MVMVA Command: Vector 0 (V0) * Light Color Matrix (LCM) (Lower Limit Result 0) - 8 Cycles
LCV0 equ 0x04C6012 ; GTE MVMVA Command: Vector 0 (V0) * Light Color Matrix (LCM) - 8 Cycles
LCV1 equ 0x04CE012 ; GTE MVMVA Command: Vector 1 (V1) * Light Color Matrix (LCM) - 8 Cycles
LCV2 equ 0x04D6012 ; GTE MVMVA Command: Vector 2 (V2) * Light Color Matrix (LCM) - 8 Cycles
LCIR equ 0x04DE012 ; GTE MVMVA Command: Vector 3 (IR) * Light Color Matrix (LCM) - 8 Cycles
LCV0TR equ 0x04C0012 ; GTE MVMVA Command: Vector 0 (V0) * Light Color Matrix (LCM) + Translation Vector (TR) - 8 Cycles
LCV1TR equ 0x04C8012 ; GTE MVMVA Command: Vector 1 (V1) * Light Color Matrix (LCM) + Translation Vector (TR) - 8 Cycles
LCV2TR equ 0x04D0012 ; GTE MVMVA Command: Vector 2 (V2) * Light Color Matrix (LCM) + Translation Vector (TR) - 8 Cycles
LCIRTR equ 0x04D8012 ; GTE MVMVA Command: Vector 3 (IR) * Light Color Matrix (LCM) + Translation Vector (TR) - 8 Cycles
LCV0BK equ 0x04C2012 ; GTE MVMVA Command: Vector 0 (V0) * Light Color Matrix (LCM) + Background Color Vector (BK) - 8 Cycles
LCV1BK equ 0x04CA012 ; GTE MVMVA Command: Vector 1 (V1) * Light Color Matrix (LCM) + Background Color Vector (BK) - 8 Cycles
LCV2BK equ 0x04D2012 ; GTE MVMVA Command: Vector 2 (V2) * Light Color Matrix (LCM) + Background Color Vector (BK) - 8 Cycles
LCIRBK equ 0x04DA012 ; GTE MVMVA Command: Vector 3 (IR) * Light Color Matrix (LCM) + Background Color Vector (BK) - 8 Cycles
; GTE SQR (Calculate Square Of Vector) Command Instructions
SQR12 equ 0x0A80428 ; GTE SQR Command: Calculate Square Of Vector 3 (IR) (S.19.12) - 5 Cycles
SQR0 equ 0x0A00428 ; GTE SQR Command: Calculate Square Of Intermediate Value 0 (IR0) (S.31.0) - 5 Cycles
; GTE OP (Calculate Outer Product Of Two Signed 16-Bit Vectors) Command Instructions
OP12 equ 0x178000C ; GTE OP Command: Calculate Outer Product Of Vector 3 (IR) (S.19.12) - 6 Cycles
OP0 equ 0x170000C ; GTE OP Command: Calculate Outer Product Of Intermediate Value 0 (IR0) (S.31.0) - 6 Cycles
; GTE GPF (General Purpose Interpolation) Command Instructions
GPF12 equ 0x198003D ; GTE OP Command: General Purpose Interpolation Of Vector 3 (IR) (S.19.12) - 5 Cycles
GPF0 equ 0x190003D ; GTE OP Command: General Purpose Interpolation Of Intermediate Value 0 (IR0) (S.31.0) - 5 Cycles
; GTE GPL (General Purpose Interpolation With Base) Command Instructions
GPL12 equ 0x1A8003E ; GTE OP Command: General Purpose Interpolation With Base Of Vector 3 (IR) (S.19.12) - 6 Cycles
GPL0 equ 0x1A0003E ; GTE OP Command: General Purpose Interpolation With Base Of Intermediate Value 0 (IR0) (S.31.0) - 5 Cycles

53
BouncyCubePs1.asm/LIB/PSX_INPUT.INC Normal file
View File

@ -0,0 +1,53 @@
;===========
; PSX INPUT
;===========
;=================
; Digital Buttons
;=================
JOY_L2 equ 0x0001 ; Joypad Input: L2 (Bit 0)
JOY_R2 equ 0x0002 ; Joypad Input: R2 (Bit 1)
JOY_L1 equ 0x0004 ; Joypad Input: L1 (Bit 2)
JOY_R1 equ 0x0008 ; Joypad Input: R1 (Bit 3)
JOY_T equ 0x0010 ; Joypad Input: Triangle (Bit 4)
JOY_C equ 0x0020 ; Joypad Input: Circle (Bit 5)
JOY_X equ 0x0040 ; Joypad Input: X (Bit 6)
JOY_S equ 0x0080 ; Joypad Input: Square (Bit 7)
JOY_SELECT equ 0x0100 ; Joypad Input: Select (Bit 8)
JOY_L3 equ 0x0200 ; Joypad Input: L3 (Bit 9) (Analog Mode Only)
JOY_R3 equ 0x0400 ; Joypad Input: R3 (Bit 10) (Analog Mode Only)
JOY_START equ 0x0800 ; Joypad Input: Start (Bit 11)
JOY_UP equ 0x1000 ; Joypad Input: Up (Bit 12)
JOY_RIGHT equ 0x2000 ; Joypad Input: Right (Bit 13)
JOY_DOWN equ 0x4000 ; Joypad Input: Down (Bit 14)
JOY_LEFT equ 0x8000 ; Joypad Input: Left (Bit 15)
;==============
; Input Macros
;==============
.macro InitJoy,BUFFER ; Initialise Joypads & Setup VSync Wait Routine Using BIOS: Buffer Address
li t1,0x15
li a0,0x20000001
li t2,0xB0
la a1,BUFFER ; Set Pad Buffer Address To Automatically Update Each Frame
jalr t2 ; Jump To BIOS Routine
nop ; Delay Slot
.endmacro
.macro WaitVSync,BUFFER,DATA ; Wait For Vertical Retrace Period & Store XOR Pad Data: Buffer Address, Data Address
la a1,BUFFER ; Load Pad Buffer Address
Wait: ; Wait For Vertical Retrace Period & Store XOR Pad Data
lw t0,0(a1) ; Load Pad Buffer
nop ; Delay Slot
beqz t0,Wait ; IF (Pad Buffer == 0) Wait
nor t0,r0 ; NOR Compliment Pad Data Bits (Delay Slot)
sw r0,0(a1) ; Store Zero To Pad Buffer
la a1,DATA ; Load Pad Data Address
sw t0,0(a1) ; Store Pad Data
.endmacro
.macro IsJoyDown,INPUT,DATA ; Is Joypad Digital Button Pressed Down: Input, Input Data Address
la a1,DATA ; Load Input Data Address
lw t0,0(a1) ; Load Input Data Word
nop ; Delay Slot
andi t0,INPUT ; T0 = Input Status
.endmacro

69
BouncyCubePs1.asm/bin2exe.py Normal file
View File

@ -0,0 +1,69 @@
#!/usr/bin/env python
from __future__ import print_function
import os
import sys
import struct
import math
usage = '''
python bin2exe.py infile outfile
'''
def main(argv):
if len(argv) != 2:
print(usage, file=sys.stderr)
sys.exit(1)
max_size = 0x200000
infile_size = os.path.getsize(argv[0])
if infile_size > max_size:
print("Error: Input file %s longer than %d bytes" % (argv[0], max_size), file=sys.stderr)
sys.exit(1)
ofile = open(argv[1], 'wb')
with open(argv[0], 'rb') as ifile:
# Write header
if sys.version_info >= (3, 0):
ofile.write(bytes('PS-X EXE', 'ascii'))
else:
ofile.write('PS-X EXE')
# Entry point
ofile.seek(0x10)
ofile.write(struct.pack('<I',0x80010000))
# Initial GP/R28 (crt0.S currently sets this)
ofile.write(struct.pack('<I',0xFFFFFFFF))
# Destination address in RAM
ofile.write(struct.pack('<I',0x80010000))
# Initial SP/R29 & FP/R30
ofile.seek(0x30)
ofile.write(struct.pack('<I',0x801FFF00))
# SP & FP offset added to ^^^^^^^^^^ just use 0
#ofile.write(struct.pack('<I',0x00000000))
# Zero fill rest of the header
ofile.seek(0x800)
# Copy input to output
buffer_size = 0x2000
for i in range(0,int(math.ceil(float(infile_size)/buffer_size))):
buffer = ifile.read(buffer_size)
ofile.write(buffer)
# ofile.write(ifile.read())
# Pad binary to 0x800 boundary
exe_size = ofile.tell()
if exe_size % 0x800 != 0:
exe_size += (0x800 - (exe_size % 0x800))
ofile.seek(exe_size-1)
ofile.write(struct.pack('B',0))
# Filesize excluding 0x800 byte header
ofile.seek(0x1C)
ofile.write(struct.pack('<I', exe_size - 0x800))
ofile.close()
if __name__ == '__main__':
main(sys.argv[1:])
sys.exit(0)

2
BouncyCubePs1.asm/make.bat Normal file
View File

@ -0,0 +1,2 @@
armips Cube.asm
python3 bin2exe.py Cube.ps1.bin Cube.exe

103
BouncyCubePs1.asm/objects.asm Normal file
View File

@ -0,0 +1,103 @@
ShadeTexCubeQuad: ; X1,Y1,Z1,X2,Y2,Z2,X3,Y3,Z3,X4,Y4,Z4,COMMAND+COLOR1,COLOR2,COLOR3,COLOR4,U1,V1,PAL,U2,V2,TEX,U3,V3,U4,V4
dw -2560, -2560, -2560 ; X1,Y1,Z1: Quad 1 Front Top Left
dw 2560, -2560, -2560 ; X2,Y2,Z2: Quad 1 Front Top Right
dw -2560, 2560, -2560 ; X3,Y3,Z3: Quad 1 Front Bottom Left
dw 2560, 2560, -2560 ; X4,Y4,Z4: Quad 1 Front Bottom Right
dw 0x3C808080 ; Quad 1 Command+Color1: ShadeTexQuad+B,G,R
dw 0x808080 ; Quad 1 Color2: B,G,R
dw 0x808080 ; Quad 1 Color3: B,G,R
dw 0x808080 ; Quad 1 Color4: B,G,R
db 0,0 ; U1,V1: Quad 1 Front Top Left
dh 0x000 ; PAL: Quad 1 Front
db 255,0 ; U2,V2: Quad 1 Front Top Right
dh 0x108 ; TEX: Quad 1 Front
db 0,255 ; U3,V3: Quad 1 Front Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 1 Front Bottom Right
dh 0 ; Padding
dw 2560, -2560, -2560 ; X1,Y1,Z1: Quad 2 Right Top Left
dw 2560, -2560, 2560 ; X2,Y2,Z2: Quad 2 Right Top Right
dw 2560, 2560, -2560 ; X3,Y3,Z3: Quad 2 Right Bottom Left
dw 2560, 2560, 2560 ; X4,Y4,Z4: Quad 2 Right Bottom Right
dw 0x3C808080 ; Quad 2 Command+Color1: ShadeTexQuad+B,G,R
dw 0x202020 ; Quad 2 Color2: B,G,R
dw 0x808080 ; Quad 2 Color3: B,G,R
dw 0x202020 ; Quad 2 Color4: B,G,R
db 0,0 ; U1,V1: Quad 2 Right Top Left
dh 0x000 ; PAL: Quad 2 Right
db 255,0 ; U2,V2: Quad 2 Right Top Right
dh 0x10C ; TEX: Quad 2 Right
db 0,255 ; U3,V3: Quad 2 Right Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 2 Right Bottom Right
dh 0 ; Padding
dw 2560, -2560, 2560 ; X1,Y1,Z1: Quad 3 Back Top Left
dw -2560, -2560, 2560 ; X2,Y2,Z2: Quad 3 Back Top Right
dw 2560, 2560, 2560 ; X3,Y3,Z3: Quad 3 Back Bottom Left
dw -2560, 2560, 2560 ; X4,Y4,Z4: Quad 3 Back Bottom Right
dw 0x3C202020 ; Quad 3 Command+Color1: ShadeTexQuad+B,G,R
dw 0x202020 ; Quad 3 Color2: B,G,R
dw 0x202020 ; Quad 3 Color3: B,G,R
dw 0x202020 ; Quad 3 Color4: B,G,R
db 0,0 ; U1,V1: Quad 3 Back Top Left
dh 0x000 ; PAL: Quad 3 Back
db 255,0 ; U2,V2: Quad 3 Back Top Right
dh 0x110 ; TEX: Quad 3 Back
db 0,255 ; U3,V3: Quad 3 Back Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 3 Back Bottom Right
dh 0 ; Padding
dw -2560, -2560, 2560 ; X1,Y1,Z1: Quad 4 Left Top Left
dw -2560, -2560, -2560 ; X2,Y2,Z2: Quad 4 Left Top Right
dw -2560, 2560, 2560 ; X3,Y3,Z3: Quad 4 Left Bottom Left
dw -2560, 2560, -2560 ; X4,Y4,Z4: Quad 4 Left Bottom Right
dw 0x3C202020 ; Quad 4 Command+Color1: ShadeTexQuad+B,G,R
dw 0x808080 ; Quad 4 Color2: B,G,R
dw 0x202020 ; Quad 4 Color3: B,G,R
dw 0x808080 ; Quad 4 Color4: B,G,R
db 0,0 ; U1,V1: Quad 4 Left Top Left
dh 0x000 ; PAL: Quad 4 Left
db 255,0 ; U2,V2: Quad 4 Left Top Right
dh 0x114 ; TEX: Quad 4 Left
db 0,255 ; U3,V3: Quad 4 Left Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 4 Left Bottom Right
dh 0 ; Padding
dw -2560, -2560, 2560 ; X1,Y1,Z1: Quad 5 Top Top Left
dw 2560, -2560, 2560 ; X2,Y2,Z2: Quad 5 Top Top Right
dw -2560, -2560, -2560 ; X3,Y3,Z3: Quad 5 Top Bottom Left
dw 2560, -2560, -2560 ; X4,Y4,Z4: Quad 5 Top Bottom Right
dw 0x3C202020 ; Quad 5 Command+Color1: ShadeTexQuad+B,G,R
dw 0x202020 ; Quad 5 Color2: B,G,R
dw 0x808080 ; Quad 5 Color3: B,G,R
dw 0x808080 ; Quad 5 Color4: B,G,R
db 0,0 ; U1,V1: Quad 5 Top Top Left
dh 0x000 ; PAL: Quad 5 Top
db 255,0 ; U2,V2: Quad 5 Top Top Right
dh 0x118 ; TEX: Quad 5 Top
db 0,255 ; U3,V3: Quad 5 Top Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 5 Top Bottom Right
dh 0 ; Padding
dw -2560, 2560, -2560 ; X1,Y1,Z1: Quad 6 Bottom Top Left
dw 2560, 2560, -2560 ; X2,Y2,Z2: Quad 6 Bottom Top Right
dw -2560, 2560, 2560 ; X3,Y3,Z3: Quad 6 Bottom Bottom Left
dw 2560, 2560, 2560 ; X4,Y4,Z4: Quad 6 Bottom Bottom Right
dw 0x3C808080 ; Quad 6 Command+Color1: ShadeTexQuad+B,G,R
dw 0x808080 ; Quad 6 Color2: B,G,R
dw 0x202020 ; Quad 6 Color3: B,G,R
dw 0x202020 ; Quad 6 Color4: B,G,R
db 0,0 ; U1,V1: Quad 6 Bottom Top Left
dh 0x000 ; PAL: Quad 6 Bottom
db 255,0 ; U2,V2: Quad 6 Bottom Top Right
dh 0x11C ; TEX: Quad 6 Bottom
db 0,255 ; U3,V3: Quad 6 Bottom Bottom Left
dh 0 ; Padding
db 255,255 ; U4,V4: Quad 6 Bottom Bottom Right
dh 0 ; Padding
ShadeTexCubeQuadEnd:

257
BouncyCubePs1.asm/sincos256.asm Normal file
View File

@ -0,0 +1,257 @@
SinCos256: ; 256 Rotations (Cos, -Sin, Sin, -Cos)
dw 256, -0, 0, -256
dw 256, -6, 6, -256
dw 256, -13, 13, -256
dw 255, -19, 19, -255
dw 255, -25, 25, -255
dw 254, -31, 31, -254
dw 253, -38, 38, -253
dw 252, -44, 44, -252
dw 251, -50, 50, -251
dw 250, -56, 56, -250
dw 248, -62, 62, -248
dw 247, -68, 68, -247
dw 245, -74, 74, -245
dw 243, -80, 80, -243
dw 241, -86, 86, -241
dw 239, -92, 92, -239
dw 237, -98, 98, -237
dw 234, -104, 104, -234
dw 231, -109, 109, -231
dw 229, -115, 115, -229
dw 226, -121, 121, -226
dw 223, -126, 126, -223
dw 220, -132, 132, -220
dw 216, -137, 137, -216
dw 213, -142, 142, -213
dw 209, -147, 147, -209
dw 206, -152, 152, -206
dw 202, -157, 157, -202
dw 198, -162, 162, -198
dw 194, -167, 167, -194
dw 190, -172, 172, -190
dw 185, -177, 177, -185
dw 181, -181, 181, -181
dw 177, -185, 185, -177
dw 172, -190, 190, -172
dw 167, -194, 194, -167
dw 162, -198, 198, -162
dw 157, -202, 202, -157
dw 152, -206, 206, -152
dw 147, -209, 209, -147
dw 142, -213, 213, -142
dw 137, -216, 216, -137
dw 132, -220, 220, -132
dw 126, -223, 223, -126
dw 121, -226, 226, -121
dw 115, -229, 229, -115
dw 109, -231, 231, -109
dw 104, -234, 234, -104
dw 98, -237, 237, -98
dw 92, -239, 239, -92
dw 86, -241, 241, -86
dw 80, -243, 243, -80
dw 74, -245, 245, -74
dw 68, -247, 247, -68
dw 62, -248, 248, -62
dw 56, -250, 250, -56
dw 50, -251, 251, -50
dw 44, -252, 252, -44
dw 38, -253, 253, -38
dw 31, -254, 254, -31
dw 25, -255, 255, -25
dw 19, -255, 255, -19
dw 13, -256, 256, -13
dw 6, -256, 256, -6
dw 0, -256, 256, -0
dw -6, -256, 256, 6
dw -13, -256, 256, 13
dw -19, -255, 255, 19
dw -25, -255, 255, 25
dw -31, -254, 254, 31
dw -38, -253, 253, 38
dw -44, -252, 252, 44
dw -50, -251, 251, 50
dw -56, -250, 250, 56
dw -62, -248, 248, 62
dw -68, -247, 247, 68
dw -74, -245, 245, 74
dw -80, -243, 243, 80
dw -86, -241, 241, 86
dw -92, -239, 239, 92
dw -98, -237, 237, 98
dw -104, -234, 234, 104
dw -109, -231, 231, 109
dw -115, -229, 229, 115
dw -121, -226, 226, 121
dw -126, -223, 223, 126
dw -132, -220, 220, 132
dw -137, -216, 216, 137
dw -142, -213, 213, 142
dw -147, -209, 209, 147
dw -152, -206, 206, 152
dw -157, -202, 202, 157
dw -162, -198, 198, 162
dw -167, -194, 194, 167
dw -172, -190, 190, 172
dw -177, -185, 185, 177
dw -181, -181, 181, 181
dw -185, -177, 177, 185
dw -190, -172, 172, 190
dw -194, -167, 167, 194
dw -198, -162, 162, 198
dw -202, -157, 157, 202
dw -206, -152, 152, 206
dw -209, -147, 147, 209
dw -213, -142, 142, 213
dw -216, -137, 137, 216
dw -220, -132, 132, 220
dw -223, -126, 126, 223
dw -226, -121, 121, 226
dw -229, -115, 115, 229
dw -231, -109, 109, 231
dw -234, -104, 104, 234
dw -237, -98, 98, 237
dw -239, -92, 92, 239
dw -241, -86, 86, 241
dw -243, -80, 80, 243
dw -245, -74, 74, 245
dw -247, -68, 68, 247
dw -248, -62, 62, 248
dw -250, -56, 56, 250
dw -251, -50, 50, 251
dw -252, -44, 44, 252
dw -253, -38, 38, 253
dw -254, -31, 31, 254
dw -255, -25, 25, 255
dw -255, -19, 19, 255
dw -256, -13, 13, 256
dw -256, -6, 6, 256
dw -256, -0, 0, 256
dw -256, 6, -6, 256
dw -256, 13, -13, 256
dw -255, 19, -19, 255
dw -255, 25, -25, 255
dw -254, 31, -31, 254
dw -253, 38, -38, 253
dw -252, 44, -44, 252
dw -251, 50, -50, 251
dw -250, 56, -56, 250
dw -248, 62, -62, 248
dw -247, 68, -68, 247
dw -245, 74, -74, 245
dw -243, 80, -80, 243
dw -241, 86, -86, 241
dw -239, 92, -92, 239
dw -237, 98, -98, 237
dw -234, 104, -104, 234
dw -231, 109, -109, 231
dw -229, 115, -115, 229
dw -226, 121, -121, 226
dw -223, 126, -126, 223
dw -220, 132, -132, 220
dw -216, 137, -137, 216
dw -213, 142, -142, 213
dw -209, 147, -147, 209
dw -206, 152, -152, 206
dw -202, 157, -157, 202
dw -198, 162, -162, 198
dw -194, 167, -167, 194
dw -190, 172, -172, 190
dw -185, 177, -177, 185
dw -181, 181, -181, 181
dw -177, 185, -185, 177
dw -172, 190, -190, 172
dw -167, 194, -194, 167
dw -162, 198, -198, 162
dw -157, 202, -202, 157
dw -152, 206, -206, 152
dw -147, 209, -209, 147
dw -142, 213, -213, 142
dw -137, 216, -216, 137
dw -132, 220, -220, 132
dw -126, 223, -223, 126
dw -121, 226, -226, 121
dw -115, 229, -229, 115
dw -109, 231, -231, 109
dw -104, 234, -234, 104
dw -98, 237, -237, 98
dw -92, 239, -239, 92
dw -86, 241, -241, 86
dw -80, 243, -243, 80
dw -74, 245, -245, 74
dw -68, 247, -247, 68
dw -62, 248, -248, 62
dw -56, 250, -250, 56
dw -50, 251, -251, 50
dw -44, 252, -252, 44
dw -38, 253, -253, 38
dw -31, 254, -254, 31
dw -25, 255, -255, 25
dw -19, 255, -255, 19
dw -13, 256, -256, 13
dw -6, 256, -256, 6
dw -0, 256, -256, 0
dw 6, 256, -256, -6
dw 13, 256, -256, -13
dw 19, 255, -255, -19
dw 25, 255, -255, -25
dw 31, 254, -254, -31
dw 38, 253, -253, -38
dw 44, 252, -252, -44
dw 50, 251, -251, -50
dw 56, 250, -250, -56
dw 62, 248, -248, -62
dw 68, 247, -247, -68
dw 74, 245, -245, -74
dw 80, 243, -243, -80
dw 86, 241, -241, -86
dw 92, 239, -239, -92
dw 98, 237, -237, -98
dw 104, 234, -234, -104
dw 109, 231, -231, -109
dw 115, 229, -229, -115
dw 121, 226, -226, -121
dw 126, 223, -223, -126
dw 132, 220, -220, -132
dw 137, 216, -216, -137
dw 142, 213, -213, -142
dw 147, 209, -209, -147
dw 152, 206, -206, -152
dw 157, 202, -202, -157
dw 162, 198, -198, -162
dw 167, 194, -194, -167
dw 172, 190, -190, -172
dw 177, 185, -185, -177
dw 181, 181, -181, -181
dw 185, 177, -177, -185
dw 190, 172, -172, -190
dw 194, 167, -167, -194
dw 198, 162, -162, -198
dw 202, 157, -157, -202
dw 206, 152, -152, -206
dw 209, 147, -147, -209
dw 213, 142, -142, -213
dw 216, 137, -137, -216
dw 220, 132, -132, -220
dw 223, 126, -126, -223
dw 226, 121, -121, -226
dw 229, 115, -115, -229
dw 231, 109, -109, -231
dw 234, 104, -104, -234
dw 237, 98, -98, -237
dw 239, 92, -92, -239
dw 241, 86, -86, -241
dw 243, 80, -80, -243
dw 245, 74, -74, -245
dw 247, 68, -68, -247
dw 248, 62, -62, -248
dw 250, 56, -56, -250
dw 251, 50, -50, -251
dw 252, 44, -44, -252
dw 253, 38, -38, -253
dw 254, 31, -31, -254
dw 255, 25, -25, -255
dw 255, 19, -19, -255
dw 256, 13, -13, -256
dw 256, 6, -6, -256