Rasterizer: Setup skeleton for Host Conditional rendering
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		| @@ -16,7 +16,6 @@ | |||||||
| #include "video_core/rasterizer_interface.h" | #include "video_core/rasterizer_interface.h" | ||||||
| #include "video_core/textures/texture.h" | #include "video_core/textures/texture.h" | ||||||
|  |  | ||||||
|  |  | ||||||
| namespace Tegra::Engines { | namespace Tegra::Engines { | ||||||
|  |  | ||||||
| using VideoCore::QueryType; | using VideoCore::QueryType; | ||||||
| @@ -538,13 +537,17 @@ void Maxwell3D::ProcessQueryGet() { | |||||||
| void Maxwell3D::ProcessQueryCondition() { | void Maxwell3D::ProcessQueryCondition() { | ||||||
|     const GPUVAddr condition_address{regs.render_enable.Address()}; |     const GPUVAddr condition_address{regs.render_enable.Address()}; | ||||||
|     switch (regs.render_enable_override) { |     switch (regs.render_enable_override) { | ||||||
|     case Regs::RenderEnable::Override::AlwaysRender: |     case Regs::RenderEnable::Override::AlwaysRender: { | ||||||
|         execute_on = true; |         execute_on = true; | ||||||
|         break; |         break; | ||||||
|     case Regs::RenderEnable::Override::NeverRender: |     case Regs::RenderEnable::Override::NeverRender: | ||||||
|         execute_on = false; |         execute_on = false; | ||||||
|         break; |         break; | ||||||
|     case Regs::RenderEnable::Override::UseRenderEnable: |     case Regs::RenderEnable::Override::UseRenderEnable: { | ||||||
|  |         if (rasterizer->AccelerateConditionalRendering()) { | ||||||
|  |             execute_on = true; | ||||||
|  |             return; | ||||||
|  |         } | ||||||
|         switch (regs.render_enable.mode) { |         switch (regs.render_enable.mode) { | ||||||
|         case Regs::RenderEnable::Mode::True: { |         case Regs::RenderEnable::Mode::True: { | ||||||
|             execute_on = true; |             execute_on = true; | ||||||
| @@ -582,6 +585,8 @@ void Maxwell3D::ProcessQueryCondition() { | |||||||
|         } |         } | ||||||
|         break; |         break; | ||||||
|     } |     } | ||||||
|  |     } | ||||||
|  |     } | ||||||
| } | } | ||||||
|  |  | ||||||
| void Maxwell3D::ProcessCounterReset() { | void Maxwell3D::ProcessCounterReset() { | ||||||
| @@ -618,7 +623,8 @@ std::optional<u64> Maxwell3D::GetQueryResult() { | |||||||
| } | } | ||||||
|  |  | ||||||
| void Maxwell3D::ProcessCBBind(size_t stage_index) { | void Maxwell3D::ProcessCBBind(size_t stage_index) { | ||||||
|     // Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage. |     // Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader | ||||||
|  |     // stage. | ||||||
|     const auto& bind_data = regs.bind_groups[stage_index]; |     const auto& bind_data = regs.bind_groups[stage_index]; | ||||||
|     auto& buffer = state.shader_stages[stage_index].const_buffers[bind_data.shader_slot]; |     auto& buffer = state.shader_stages[stage_index].const_buffers[bind_data.shader_slot]; | ||||||
|     buffer.enabled = bind_data.valid.Value() != 0; |     buffer.enabled = bind_data.valid.Value() != 0; | ||||||
|   | |||||||
| @@ -127,6 +127,10 @@ public: | |||||||
|     /// Notify rasterizer that a frame is about to finish |     /// Notify rasterizer that a frame is about to finish | ||||||
|     virtual void TickFrame() = 0; |     virtual void TickFrame() = 0; | ||||||
|  |  | ||||||
|  |     virtual bool AccelerateConditionalRendering() { | ||||||
|  |         return false; | ||||||
|  |     } | ||||||
|  |  | ||||||
|     /// Attempt to use a faster method to perform a surface copy |     /// Attempt to use a faster method to perform a surface copy | ||||||
|     [[nodiscard]] virtual bool AccelerateSurfaceCopy( |     [[nodiscard]] virtual bool AccelerateSurfaceCopy( | ||||||
|         const Tegra::Engines::Fermi2D::Surface& src, const Tegra::Engines::Fermi2D::Surface& dst, |         const Tegra::Engines::Fermi2D::Surface& src, const Tegra::Engines::Fermi2D::Surface& dst, | ||||||
|   | |||||||
| @@ -525,6 +525,21 @@ void RasterizerOpenGL::TickFrame() { | |||||||
|     } |     } | ||||||
| } | } | ||||||
|  |  | ||||||
|  | bool RasterizerOpenGL::AccelerateConditionalRendering() { | ||||||
|  |     if (Settings::IsGPULevelHigh()) { | ||||||
|  |         // Reimplement Host conditional rendering. | ||||||
|  |         return false; | ||||||
|  |     } | ||||||
|  |     // Medium / Low Hack: stub any checks on queries writen into the buffer cache. | ||||||
|  |     const GPUVAddr condition_address{maxwell3d->regs.render_enable.Address()}; | ||||||
|  |     Maxwell::ReportSemaphore::Compare cmp; | ||||||
|  |     if (gpu_memory->IsMemoryDirty(condition_address, sizeof(cmp), | ||||||
|  |                                   VideoCommon::CacheType::BufferCache)) { | ||||||
|  |         return true; | ||||||
|  |     } | ||||||
|  |     return false; | ||||||
|  | } | ||||||
|  |  | ||||||
| bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | ||||||
|                                              const Tegra::Engines::Fermi2D::Surface& dst, |                                              const Tegra::Engines::Fermi2D::Surface& dst, | ||||||
|                                              const Tegra::Engines::Fermi2D::Config& copy_config) { |                                              const Tegra::Engines::Fermi2D::Config& copy_config) { | ||||||
|   | |||||||
| @@ -100,6 +100,7 @@ public: | |||||||
|     void TiledCacheBarrier() override; |     void TiledCacheBarrier() override; | ||||||
|     void FlushCommands() override; |     void FlushCommands() override; | ||||||
|     void TickFrame() override; |     void TickFrame() override; | ||||||
|  |     bool AccelerateConditionalRendering() override; | ||||||
|     bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, |     bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | ||||||
|                                const Tegra::Engines::Fermi2D::Surface& dst, |                                const Tegra::Engines::Fermi2D::Surface& dst, | ||||||
|                                const Tegra::Engines::Fermi2D::Config& copy_config) override; |                                const Tegra::Engines::Fermi2D::Config& copy_config) override; | ||||||
|   | |||||||
| @@ -600,6 +600,21 @@ void RasterizerVulkan::TickFrame() { | |||||||
|     } |     } | ||||||
| } | } | ||||||
|  |  | ||||||
|  | bool RasterizerVulkan::AccelerateConditionalRendering() { | ||||||
|  |     if (Settings::IsGPULevelHigh()) { | ||||||
|  |         // TODO(Blinkhawk): Reimplement Host conditional rendering. | ||||||
|  |         return false; | ||||||
|  |     } | ||||||
|  |     // Medium / Low Hack: stub any checks on queries writen into the buffer cache. | ||||||
|  |     const GPUVAddr condition_address{maxwell3d->regs.render_enable.Address()}; | ||||||
|  |     Maxwell::ReportSemaphore::Compare cmp; | ||||||
|  |     if (gpu_memory->IsMemoryDirty(condition_address, sizeof(cmp), | ||||||
|  |                                   VideoCommon::CacheType::BufferCache)) { | ||||||
|  |         return true; | ||||||
|  |     } | ||||||
|  |     return false; | ||||||
|  | } | ||||||
|  |  | ||||||
| bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | ||||||
|                                              const Tegra::Engines::Fermi2D::Surface& dst, |                                              const Tegra::Engines::Fermi2D::Surface& dst, | ||||||
|                                              const Tegra::Engines::Fermi2D::Config& copy_config) { |                                              const Tegra::Engines::Fermi2D::Config& copy_config) { | ||||||
| @@ -995,7 +1010,8 @@ void RasterizerVulkan::UpdateDepthBiasEnable(Tegra::Engines::Maxwell3D::Regs& re | |||||||
|     }; |     }; | ||||||
|     const u32 topology_index = static_cast<u32>(maxwell3d->draw_manager->GetDrawState().topology); |     const u32 topology_index = static_cast<u32>(maxwell3d->draw_manager->GetDrawState().topology); | ||||||
|     const u32 enable = enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]]; |     const u32 enable = enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]]; | ||||||
|     scheduler.Record([enable](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthBiasEnableEXT(enable != 0); }); |     scheduler.Record( | ||||||
|  |         [enable](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthBiasEnableEXT(enable != 0); }); | ||||||
| } | } | ||||||
|  |  | ||||||
| void RasterizerVulkan::UpdateLogicOpEnable(Tegra::Engines::Maxwell3D::Regs& regs) { | void RasterizerVulkan::UpdateLogicOpEnable(Tegra::Engines::Maxwell3D::Regs& regs) { | ||||||
| @@ -1012,11 +1028,11 @@ void RasterizerVulkan::UpdateDepthClampEnable(Tegra::Engines::Maxwell3D::Regs& r | |||||||
|         return; |         return; | ||||||
|     } |     } | ||||||
|     bool is_enabled = !(regs.viewport_clip_control.geometry_clip == |     bool is_enabled = !(regs.viewport_clip_control.geometry_clip == | ||||||
|                                  Maxwell::ViewportClipControl::GeometryClip::Passthrough || |                             Maxwell::ViewportClipControl::GeometryClip::Passthrough || | ||||||
|                              regs.viewport_clip_control.geometry_clip == |                         regs.viewport_clip_control.geometry_clip == | ||||||
|                                  Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ || |                             Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ || | ||||||
|                              regs.viewport_clip_control.geometry_clip == |                         regs.viewport_clip_control.geometry_clip == | ||||||
|                                  Maxwell::ViewportClipControl::GeometryClip::FrustumZ); |                             Maxwell::ViewportClipControl::GeometryClip::FrustumZ); | ||||||
|     scheduler.Record( |     scheduler.Record( | ||||||
|         [is_enabled](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthClampEnableEXT(is_enabled); }); |         [is_enabled](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthClampEnableEXT(is_enabled); }); | ||||||
| } | } | ||||||
|   | |||||||
| @@ -96,6 +96,7 @@ public: | |||||||
|     void TiledCacheBarrier() override; |     void TiledCacheBarrier() override; | ||||||
|     void FlushCommands() override; |     void FlushCommands() override; | ||||||
|     void TickFrame() override; |     void TickFrame() override; | ||||||
|  |     bool AccelerateConditionalRendering() override; | ||||||
|     bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, |     bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src, | ||||||
|                                const Tegra::Engines::Fermi2D::Surface& dst, |                                const Tegra::Engines::Fermi2D::Surface& dst, | ||||||
|                                const Tegra::Engines::Fermi2D::Config& copy_config) override; |                                const Tegra::Engines::Fermi2D::Config& copy_config) override; | ||||||
|   | |||||||
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