99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
324 lines
12 KiB
C++
324 lines
12 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <algorithm>
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#include <memory>
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#include <vector>
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#include <queue>
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#include "common/settings.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/post_order.h"
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#include "shader_recompiler/frontend/maxwell/structured_control_flow.h"
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#include "shader_recompiler/frontend/maxwell/translate/translate.h"
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#include "shader_recompiler/frontend/maxwell/translate_program.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Maxwell {
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namespace {
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IR::BlockList GenerateBlocks(const IR::AbstractSyntaxList& syntax_list) {
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size_t num_syntax_blocks{};
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for (const auto& node : syntax_list) {
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if (node.type == IR::AbstractSyntaxNode::Type::Block) {
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++num_syntax_blocks;
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}
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}
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IR::BlockList blocks;
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blocks.reserve(num_syntax_blocks);
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u32 order_index{};
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for (const auto& node : syntax_list) {
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if (node.type == IR::AbstractSyntaxNode::Type::Block) {
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blocks.push_back(node.data.block);
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blocks.back()->SetOrder(order_index++);
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}
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}
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return blocks;
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}
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void RemoveUnreachableBlocks(IR::Program& program) {
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// Some blocks might be unreachable if a function call exists unconditionally
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// If this happens the number of blocks and post order blocks will mismatch
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if (program.blocks.size() == program.post_order_blocks.size()) {
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return;
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}
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const auto begin{program.blocks.begin() + 1};
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const auto end{program.blocks.end()};
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const auto pred{[](IR::Block* block) { return block->ImmPredecessors().empty(); }};
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program.blocks.erase(std::remove_if(begin, end, pred), end);
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}
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void CollectInterpolationInfo(Environment& env, IR::Program& program) {
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if (program.stage != Stage::Fragment) {
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return;
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}
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const ProgramHeader& sph{env.SPH()};
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for (size_t index = 0; index < IR::NUM_GENERICS; ++index) {
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std::optional<PixelImap> imap;
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for (const PixelImap value : sph.ps.GenericInputMap(static_cast<u32>(index))) {
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if (value == PixelImap::Unused) {
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continue;
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}
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if (imap && imap != value) {
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throw NotImplementedException("Per component interpolation");
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}
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imap = value;
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}
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if (!imap) {
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continue;
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}
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program.info.interpolation[index] = [&] {
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switch (*imap) {
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case PixelImap::Unused:
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case PixelImap::Perspective:
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return Interpolation::Smooth;
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case PixelImap::Constant:
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return Interpolation::Flat;
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case PixelImap::ScreenLinear:
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return Interpolation::NoPerspective;
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}
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throw NotImplementedException("Unknown interpolation {}", *imap);
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}();
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}
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}
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void AddNVNStorageBuffers(IR::Program& program) {
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if (!program.info.uses_global_memory) {
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return;
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}
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const u32 driver_cbuf{0};
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const u32 descriptor_size{0x10};
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const u32 num_buffers{16};
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const u32 base{[&] {
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switch (program.stage) {
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case Stage::VertexA:
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case Stage::VertexB:
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return 0x110u;
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case Stage::TessellationControl:
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return 0x210u;
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case Stage::TessellationEval:
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return 0x310u;
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case Stage::Geometry:
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return 0x410u;
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case Stage::Fragment:
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return 0x510u;
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case Stage::Compute:
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return 0x310u;
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}
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throw InvalidArgument("Invalid stage {}", program.stage);
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}()};
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auto& descs{program.info.storage_buffers_descriptors};
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for (u32 index = 0; index < num_buffers; ++index) {
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if (!program.info.nvn_buffer_used[index]) {
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continue;
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}
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const u32 offset{base + index * descriptor_size};
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const auto it{std::ranges::find(descs, offset, &StorageBufferDescriptor::cbuf_offset)};
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if (it != descs.end()) {
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it->is_written |= program.info.stores_global_memory;
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continue;
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}
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descs.push_back({
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.cbuf_index = driver_cbuf,
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.cbuf_offset = offset,
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.count = 1,
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.is_written = program.info.stores_global_memory,
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});
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}
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}
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bool IsLegacyAttribute(IR::Attribute attribute) {
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return (attribute >= IR::Attribute::ColorFrontDiffuseR &&
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attribute <= IR::Attribute::ColorBackSpecularA) ||
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attribute == IR::Attribute::FogCoordinate ||
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(attribute >= IR::Attribute::FixedFncTexture0S &&
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attribute <= IR::Attribute::FixedFncTexture9Q);
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}
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std::map<IR::Attribute, IR::Attribute> GenerateLegacyToGenericMappings(
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const VaryingState& state, std::queue<IR::Attribute> ununsed_generics) {
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std::map<IR::Attribute, IR::Attribute> mapping;
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for (size_t index = 0; index < 4; ++index) {
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auto attr = IR::Attribute::ColorFrontDiffuseR + index * 4;
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if (state.AnyComponent(attr)) {
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for (size_t i = 0; i < 4; ++i) {
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mapping.insert({attr + i, ununsed_generics.front() + i});
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}
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ununsed_generics.pop();
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}
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}
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if (state[IR::Attribute::FogCoordinate]) {
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mapping.insert({IR::Attribute::FogCoordinate, ununsed_generics.front()});
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ununsed_generics.pop();
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}
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for (size_t index = 0; index < IR::NUM_FIXEDFNCTEXTURE; ++index) {
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auto attr = IR::Attribute::FixedFncTexture0S + index * 4;
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if (state.AnyComponent(attr)) {
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for (size_t i = 0; i < 4; ++i) {
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mapping.insert({attr + i, ununsed_generics.front() + i});
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}
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ununsed_generics.pop();
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}
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}
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return mapping;
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}
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} // Anonymous namespace
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IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Environment& env, Flow::CFG& cfg, const HostTranslateInfo& host_info) {
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IR::Program program;
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program.syntax_list = BuildASL(inst_pool, block_pool, env, cfg, host_info);
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program.blocks = GenerateBlocks(program.syntax_list);
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program.post_order_blocks = PostOrder(program.syntax_list.front());
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program.stage = env.ShaderStage();
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program.local_memory_size = env.LocalMemorySize();
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switch (program.stage) {
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case Stage::TessellationControl: {
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const ProgramHeader& sph{env.SPH()};
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program.invocations = sph.common2.threads_per_input_primitive;
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break;
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}
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case Stage::Geometry: {
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const ProgramHeader& sph{env.SPH()};
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program.output_topology = sph.common3.output_topology;
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program.output_vertices = sph.common4.max_output_vertices;
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program.invocations = sph.common2.threads_per_input_primitive;
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program.is_geometry_passthrough = sph.common0.geometry_passthrough != 0;
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if (program.is_geometry_passthrough) {
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const auto& mask{env.GpPassthroughMask()};
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for (size_t i = 0; i < program.info.passthrough.mask.size(); ++i) {
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program.info.passthrough.mask[i] = ((mask[i / 32] >> (i % 32)) & 1) == 0;
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}
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}
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break;
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}
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case Stage::Compute:
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program.workgroup_size = env.WorkgroupSize();
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program.shared_memory_size = env.SharedMemorySize();
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break;
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default:
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break;
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}
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RemoveUnreachableBlocks(program);
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// Replace instructions before the SSA rewrite
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if (!host_info.support_float16) {
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Optimization::LowerFp16ToFp32(program);
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}
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if (!host_info.support_int64) {
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Optimization::LowerInt64ToInt32(program);
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}
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Optimization::SsaRewritePass(program);
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Optimization::ConstantPropagationPass(program);
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Optimization::GlobalMemoryToStorageBufferPass(program);
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Optimization::TexturePass(env, program);
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if (Settings::values.resolution_info.active) {
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Optimization::RescalingPass(program);
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}
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Optimization::DeadCodeEliminationPass(program);
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if (Settings::values.renderer_debug) {
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Optimization::VerificationPass(program);
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}
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Optimization::CollectShaderInfoPass(env, program);
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CollectInterpolationInfo(env, program);
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AddNVNStorageBuffers(program);
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return program;
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}
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IR::Program MergeDualVertexPrograms(IR::Program& vertex_a, IR::Program& vertex_b,
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Environment& env_vertex_b) {
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IR::Program result{};
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Optimization::VertexATransformPass(vertex_a);
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Optimization::VertexBTransformPass(vertex_b);
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for (const auto& term : vertex_a.syntax_list) {
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if (term.type != IR::AbstractSyntaxNode::Type::Return) {
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result.syntax_list.push_back(term);
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}
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}
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result.syntax_list.insert(result.syntax_list.end(), vertex_b.syntax_list.begin(),
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vertex_b.syntax_list.end());
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result.blocks = GenerateBlocks(result.syntax_list);
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result.post_order_blocks = vertex_b.post_order_blocks;
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for (const auto& block : vertex_a.post_order_blocks) {
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result.post_order_blocks.push_back(block);
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}
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result.stage = Stage::VertexB;
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result.info = vertex_a.info;
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result.local_memory_size = std::max(vertex_a.local_memory_size, vertex_b.local_memory_size);
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result.info.loads.mask |= vertex_b.info.loads.mask;
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result.info.stores.mask |= vertex_b.info.stores.mask;
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Optimization::JoinTextureInfo(result.info, vertex_b.info);
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Optimization::JoinStorageInfo(result.info, vertex_b.info);
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Optimization::DeadCodeEliminationPass(result);
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if (Settings::values.renderer_debug) {
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Optimization::VerificationPass(result);
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}
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Optimization::CollectShaderInfoPass(env_vertex_b, result);
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return result;
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}
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void ConvertLegacyToGeneric(IR::Program& program, const Shader::RuntimeInfo& runtime_info) {
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auto& stores = program.info.stores;
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if (stores.Legacy()) {
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std::queue<IR::Attribute> ununsed_output_generics{};
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for (size_t index = 0; index < IR::NUM_GENERICS; ++index) {
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if (!stores.Generic(index)) {
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ununsed_output_generics.push(IR::Attribute::Generic0X + index * 4);
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}
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}
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auto mappings = GenerateLegacyToGenericMappings(stores, ununsed_output_generics);
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::SetAttribute: {
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const auto attr = inst.Arg(0).Attribute();
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if (IsLegacyAttribute(attr)) {
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stores.Set(mappings[attr], true);
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inst.SetArg(0, Shader::IR::Value(mappings[attr]));
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}
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break;
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}
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default:
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break;
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}
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}
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}
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}
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auto& loads = program.info.loads;
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if (loads.Legacy()) {
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std::queue<IR::Attribute> ununsed_input_generics{};
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for (size_t index = 0; index < IR::NUM_GENERICS; ++index) {
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const AttributeType input_type{runtime_info.generic_input_types[index]};
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if (!runtime_info.previous_stage_stores.Generic(index) || !loads.Generic(index) ||
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input_type == AttributeType::Disabled) {
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ununsed_input_generics.push(IR::Attribute::Generic0X + index * 4);
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}
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}
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auto mappings = GenerateLegacyToGenericMappings(loads, ununsed_input_generics);
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetAttribute: {
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const auto attr = inst.Arg(0).Attribute();
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if (IsLegacyAttribute(attr)) {
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loads.Set(mappings[attr], true);
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inst.SetArg(0, Shader::IR::Value(mappings[attr]));
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}
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break;
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}
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default:
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break;
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}
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}
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}
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}
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}
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} // namespace Shader::Maxwell
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