maxwell3d: HLE multi-layer clear macro
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@ -1129,6 +1129,7 @@ public:
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Tegra::RenderTargetFormat format;
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Tegra::RenderTargetFormat format;
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TileMode tile_mode;
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TileMode tile_mode;
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union {
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union {
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u32 depth_volume;
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BitField<0, 16, u32> depth;
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BitField<0, 16, u32> depth;
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BitField<16, 1, u32> volume;
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BitField<16, 1, u32> volume;
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};
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};
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@ -126,11 +126,31 @@ void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
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}
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}
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}
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}
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constexpr std::array<std::pair<u64, HLEFunction>, 4> hle_funcs{{
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// Multi-layer Clear
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void HLE_EAD26C3E2109B06B(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
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ASSERT(parameters.size() == 1);
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Engines::Maxwell3D::Regs::ClearSurface clear_params{parameters[0]};
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const u32 rt_index = clear_params.RT;
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const u32 num_layers = maxwell3d.regs.rt[rt_index].depth_volume;
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for (u32 i = 0; i < num_layers; i++) {
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// 0x674 = regs.clear_surface
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maxwell3d.CallMethod(0x674, clear_params.raw, true);
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clear_params.layer.Assign(clear_params.layer + 1);
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// FIXME: remove this when amdvlk can clear multiple layers without crashing
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break;
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}
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}
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constexpr std::array<std::pair<u64, HLEFunction>, 5> hle_funcs{{
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{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
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{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
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{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
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{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
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{0x0217920100488FF7, &HLE_0217920100488FF7},
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{0x0217920100488FF7, &HLE_0217920100488FF7},
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{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
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{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
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{0xEAD26C3E2109B06B, &HLE_EAD26C3E2109B06B},
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}};
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}};
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class HLEMacroImpl final : public CachedMacro {
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class HLEMacroImpl final : public CachedMacro {
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