gl_shader_decompiler: Implement BFE_IMM instruction.
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0cb7ce71e0
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@ -265,6 +265,17 @@ union Instruction {
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BitField<49, 1, u64> negate_a;
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BitField<49, 1, u64> negate_a;
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} iscadd;
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} iscadd;
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union {
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BitField<20, 8, u64> shift_position;
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BitField<28, 8, u64> shift_length;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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u64 GetLeftShiftValue() const {
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return 32 - (shift_position + shift_length);
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}
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} bfe;
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union {
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union {
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BitField<48, 1, u64> negate_b;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_c;
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BitField<49, 1, u64> negate_c;
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@ -478,6 +489,7 @@ public:
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enum class Type {
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enum class Type {
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Trivial,
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Trivial,
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Arithmetic,
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Arithmetic,
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Bfe,
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Logic,
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Logic,
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Shift,
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Shift,
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ScaledAdd,
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ScaledAdd,
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@ -584,9 +596,6 @@ private:
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std::vector<Matcher> table = {
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std::vector<Matcher> table = {
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("0100110000000---", Id::BFE_C, Type::Flow, "BFE_C"),
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INST("0101110000000---", Id::BFE_R, Type::Flow, "BFE_R"),
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INST("0011100-00000---", Id::BFE_IMM, Type::Flow, "BFE_IMM"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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@ -631,6 +640,9 @@ private:
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INST("0100110000100---", Id::IMNMX_C, Type::Arithmetic, "FMNMX_IMM"),
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INST("0100110000100---", Id::IMNMX_C, Type::Arithmetic, "FMNMX_IMM"),
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INST("0101110000100---", Id::IMNMX_R, Type::Arithmetic, "FMNMX_IMM"),
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INST("0101110000100---", Id::IMNMX_R, Type::Arithmetic, "FMNMX_IMM"),
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INST("0011100-00100---", Id::IMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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INST("0011100-00100---", Id::IMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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INST("0100110000000---", Id::BFE_C, Type::Bfe, "BFE_C"),
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INST("0101110000000---", Id::BFE_R, Type::Bfe, "BFE_R"),
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INST("0011100-00000---", Id::BFE_IMM, Type::Bfe, "BFE_IMM"),
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INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
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INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
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INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
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INST("0100110001001---", Id::SHL_C, Type::Shift, "SHL_C"),
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INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
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INST("0101110001001---", Id::SHL_R, Type::Shift, "SHL_R"),
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@ -888,8 +888,33 @@ private:
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}
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}
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break;
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break;
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}
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}
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case OpCode::Type::Bfe: {
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ASSERT_MSG(!instr.bfe.negate_b, "Unimplemented");
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std::string op_a = instr.bfe.negate_a ? "-" : "";
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op_a += regs.GetRegisterAsInteger(instr.gpr8);
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switch (opcode->GetId()) {
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case OpCode::Id::BFE_IMM: {
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std::string inner_shift =
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'(' + op_a + " << " + std::to_string(instr.bfe.GetLeftShiftValue()) + ')';
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std::string outer_shift =
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'(' + inner_shift + " >> " +
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std::to_string(instr.bfe.GetLeftShiftValue() + instr.bfe.shift_position) + ')';
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regs.SetRegisterToInteger(instr.gpr0, true, 0, outer_shift, 1, 1);
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break;
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}
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled BFE instruction: {}", opcode->GetName());
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UNREACHABLE();
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}
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}
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break;
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}
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case OpCode::Type::Logic: {
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case OpCode::Type::Logic: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, false);
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, true);
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if (instr.alu.lop.invert_a)
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if (instr.alu.lop.invert_a)
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op_a = "~(" + op_a + ')';
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op_a = "~(" + op_a + ')';
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@ -903,17 +928,17 @@ private:
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switch (instr.alu.lop.operation) {
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switch (instr.alu.lop.operation) {
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case Tegra::Shader::LogicOperation::And: {
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case Tegra::Shader::LogicOperation::And: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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'(' + op_a + " & " + std::to_string(imm) + ')', 1, 1);
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'(' + op_a + " & " + std::to_string(imm) + ')', 1, 1);
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break;
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break;
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}
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}
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case Tegra::Shader::LogicOperation::Or: {
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case Tegra::Shader::LogicOperation::Or: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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'(' + op_a + " | " + std::to_string(imm) + ')', 1, 1);
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'(' + op_a + " | " + std::to_string(imm) + ')', 1, 1);
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break;
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break;
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}
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}
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case Tegra::Shader::LogicOperation::Xor: {
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case Tegra::Shader::LogicOperation::Xor: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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'(' + op_a + " ^ " + std::to_string(imm) + ')', 1, 1);
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'(' + op_a + " ^ " + std::to_string(imm) + ')', 1, 1);
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break;
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break;
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}
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}
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