From 6085d32cf5d5ca4f9a5c0dc2f261505ed86c6539 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Mon, 12 Feb 2018 21:53:32 +0000 Subject: [PATCH] arm_dynarmic: Support direct page table access --- externals/catch | 2 +- externals/dynarmic | 2 +- src/core/arm/dynarmic/arm_dynarmic.cpp | 20 ++++++++++++++------ src/core/memory.h | 9 +++++---- 4 files changed, 21 insertions(+), 12 deletions(-) diff --git a/externals/catch b/externals/catch index 62dae592c..cd76f5730 160000 --- a/externals/catch +++ b/externals/catch @@ -1 +1 @@ -Subproject commit 62dae592c330ab74cea30c897255ee9518639c3f +Subproject commit cd76f5730c9a3afa19f3b9c83608d9c7ab325a19 diff --git a/externals/dynarmic b/externals/dynarmic index 406c07100..d7323d679 160000 --- a/externals/dynarmic +++ b/externals/dynarmic @@ -1 +1 @@ -Subproject commit 406c07100890e0463bd3b44ff6857501cd714a93 +Subproject commit d7323d6799f0845b8c3214d624efce7a3094a657 diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp index 302bae569..283d20831 100644 --- a/src/core/arm/dynarmic/arm_dynarmic.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic.cpp @@ -85,11 +85,19 @@ public: ARM_Dynarmic& parent; size_t ticks_remaining = 0; size_t num_interpreted_instructions = 0; - u64 tpidrr0_el0 = 0; + u64 tpidrro_el0 = 0; }; std::unique_ptr MakeJit(const std::unique_ptr& cb) { - Dynarmic::A64::UserConfig config{cb.get()}; + const auto page_table = Kernel::g_current_process->vm_manager.page_table.pointers.data(); + + Dynarmic::A64::UserConfig config; + config.callbacks = cb.get(); + config.tpidrro_el0 = &cb->tpidrro_el0; + config.dczid_el0 = 4; + config.page_table = reinterpret_cast(page_table); + config.page_table_address_space_bits = Memory::ADDRESS_SPACE_BITS; + config.silently_mirror_page_table = false; return std::make_unique(config); } @@ -149,11 +157,11 @@ void ARM_Dynarmic::SetCPSR(u32 cpsr) { } u64 ARM_Dynarmic::GetTlsAddress() const { - return cb->tpidrr0_el0; + return cb->tpidrro_el0; } void ARM_Dynarmic::SetTlsAddress(u64 address) { - cb->tpidrr0_el0 = address; + cb->tpidrro_el0 = address; } void ARM_Dynarmic::ExecuteInstructions(int num_instructions) { @@ -170,7 +178,7 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) { ctx.cpsr = jit->GetPstate(); ctx.fpu_registers = jit->GetVectors(); ctx.fpscr = jit->GetFpcr(); - ctx.tls_address = cb->tpidrr0_el0; + ctx.tls_address = cb->tpidrro_el0; } void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) { @@ -180,7 +188,7 @@ void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) { jit->SetPstate(static_cast(ctx.cpsr)); jit->SetVectors(ctx.fpu_registers); jit->SetFpcr(static_cast(ctx.fpscr)); - cb->tpidrr0_el0 = ctx.tls_address; + cb->tpidrro_el0 = ctx.tls_address; } void ARM_Dynarmic::PrepareReschedule() { diff --git a/src/core/memory.h b/src/core/memory.h index b2158ca46..f3ace7a98 100644 --- a/src/core/memory.h +++ b/src/core/memory.h @@ -25,10 +25,11 @@ namespace Memory { * Page size used by the ARM architecture. This is the smallest granularity with which memory can * be mapped. */ -const int PAGE_BITS = 12; -const u64 PAGE_SIZE = 1 << PAGE_BITS; -const u64 PAGE_MASK = PAGE_SIZE - 1; -const size_t PAGE_TABLE_NUM_ENTRIES = 1ULL << (36 - PAGE_BITS); +constexpr size_t PAGE_BITS = 12; +constexpr u64 PAGE_SIZE = 1 << PAGE_BITS; +constexpr u64 PAGE_MASK = PAGE_SIZE - 1; +constexpr size_t ADDRESS_SPACE_BITS = 36; +constexpr size_t PAGE_TABLE_NUM_ENTRIES = 1ULL << (ADDRESS_SPACE_BITS - PAGE_BITS); enum class PageType : u8 { /// Page is unmapped and should cause an access error.