Merge pull request #230 from Subv/gpu_draw
GPU: Intercept writes to the VERTEX_END_GL register.
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commit
5750f6f046
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@ -19,6 +19,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value) {
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#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
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#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
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switch (method) {
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switch (method) {
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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break;
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}
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case MAXWELL3D_REG_INDEX(query.query_get): {
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case MAXWELL3D_REG_INDEX(query.query_get): {
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ProcessQueryGet();
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ProcessQueryGet();
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break;
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break;
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@ -47,5 +51,10 @@ void Maxwell3D::ProcessQueryGet() {
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UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
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UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
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}
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}
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}
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}
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void Maxwell3D::DrawArrays() {
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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}
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} // namespace Engines
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} // namespace Engines
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} // namespace Tegra
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} // namespace Tegra
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@ -32,7 +32,12 @@ public:
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union {
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union {
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struct {
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struct {
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INSERT_PADDING_WORDS(0x6C0);
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INSERT_PADDING_WORDS(0x585);
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struct {
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u32 vertex_end_gl;
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u32 vertex_begin_gl;
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} draw;
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INSERT_PADDING_WORDS(0x139);
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struct {
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struct {
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u32 query_address_high;
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u32 query_address_high;
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u32 query_address_low;
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u32 query_address_low;
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@ -61,6 +66,9 @@ private:
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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};
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};
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