diff --git a/src/core/hid/irs_types.h b/src/core/hid/irs_types.h
index 88c5b016d..0d1bfe53f 100644
--- a/src/core/hid/irs_types.h
+++ b/src/core/hid/irs_types.h
@@ -14,7 +14,7 @@ enum class CameraAmbientNoiseLevel : u32 {
     Low,
     Medium,
     High,
-    Unkown3, // This level can't be reached
+    Unknown3, // This level can't be reached
 };
 
 // This is nn::irsensor::CameraLightTarget
@@ -75,9 +75,9 @@ enum class IrCameraStatus : u32 {
 enum class IrCameraInternalStatus : u32 {
     Stopped,
     FirmwareUpdateNeeded,
-    Unkown2,
-    Unkown3,
-    Unkown4,
+    Unknown2,
+    Unknown3,
+    Unknown4,
     FirmwareVersionRequested,
     FirmwareVersionIsInvalid,
     Ready,
@@ -121,20 +121,20 @@ enum class IrSensorFunctionLevel : u8 {
 
 // This is nn::irsensor::MomentProcessorPreprocess
 enum class MomentProcessorPreprocess : u32 {
-    Unkown0,
-    Unkown1,
+    Unknown0,
+    Unknown1,
 };
 
 // This is nn::irsensor::PackedMomentProcessorPreprocess
 enum class PackedMomentProcessorPreprocess : u8 {
-    Unkown0,
-    Unkown1,
+    Unknown0,
+    Unknown1,
 };
 
 // This is nn::irsensor::PointingStatus
 enum class PointingStatus : u32 {
-    Unkown0,
-    Unkown1,
+    Unknown0,
+    Unknown1,
 };
 
 struct IrsRect {
diff --git a/src/core/hle/service/hid/hid.cpp b/src/core/hle/service/hid/hid.cpp
index 46bad7871..79375bd2f 100644
--- a/src/core/hle/service/hid/hid.cpp
+++ b/src/core/hle/service/hid/hid.cpp
@@ -2118,7 +2118,7 @@ void Hid::WritePalmaWaveEntry(Kernel::HLERequestContext& ctx) {
     ASSERT_MSG(t_mem->GetSize() == 0x3000, "t_mem has incorrect size");
 
     LOG_WARNING(Service_HID,
-                "(STUBBED) called, connection_handle={}, wave_set={}, unkown={}, "
+                "(STUBBED) called, connection_handle={}, wave_set={}, unknown={}, "
                 "t_mem_handle=0x{:08X}, t_mem_size={}, size={}",
                 connection_handle.npad_id, wave_set, unknown, t_mem_handle, t_mem_size, size);
 
diff --git a/src/core/hle/service/hid/irsensor/pointing_processor.h b/src/core/hle/service/hid/irsensor/pointing_processor.h
index cf4930794..d63423aff 100644
--- a/src/core/hle/service/hid/irsensor/pointing_processor.h
+++ b/src/core/hle/service/hid/irsensor/pointing_processor.h
@@ -37,10 +37,10 @@ private:
         u8 pointing_status;
         INSERT_PADDING_BYTES(3);
         u32 unknown;
-        float unkown_float1;
+        float unknown_float1;
         float position_x;
         float position_y;
-        float unkown_float2;
+        float unknown_float2;
         Core::IrSensor::IrsRect window_of_interest;
     };
     static_assert(sizeof(PointingProcessorMarkerData) == 0x20,
diff --git a/src/video_core/texture_cache/descriptor_table.h b/src/video_core/texture_cache/descriptor_table.h
index b18e3838f..ee4240288 100644
--- a/src/video_core/texture_cache/descriptor_table.h
+++ b/src/video_core/texture_cache/descriptor_table.h
@@ -18,7 +18,7 @@ class DescriptorTable {
 public:
     explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {}
 
-    [[nodiscard]] bool Synchornize(GPUVAddr gpu_addr, u32 limit) {
+    [[nodiscard]] bool Synchronize(GPUVAddr gpu_addr, u32 limit) {
         [[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) {
             return false;
         }
diff --git a/src/video_core/texture_cache/texture_cache.h b/src/video_core/texture_cache/texture_cache.h
index 413baf730..0e0fd410f 100644
--- a/src/video_core/texture_cache/texture_cache.h
+++ b/src/video_core/texture_cache/texture_cache.h
@@ -193,11 +193,11 @@ void TextureCache<P>::SynchronizeGraphicsDescriptors() {
     const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding;
     const u32 tic_limit = maxwell3d->regs.tex_header.limit;
     const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit;
-    if (channel_state->graphics_sampler_table.Synchornize(maxwell3d->regs.tex_sampler.Address(),
+    if (channel_state->graphics_sampler_table.Synchronize(maxwell3d->regs.tex_sampler.Address(),
                                                           tsc_limit)) {
         channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
     }
-    if (channel_state->graphics_image_table.Synchornize(maxwell3d->regs.tex_header.Address(),
+    if (channel_state->graphics_image_table.Synchronize(maxwell3d->regs.tex_header.Address(),
                                                         tic_limit)) {
         channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
     }
@@ -209,10 +209,10 @@ void TextureCache<P>::SynchronizeComputeDescriptors() {
     const u32 tic_limit = kepler_compute->regs.tic.limit;
     const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit;
     const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address();
-    if (channel_state->compute_sampler_table.Synchornize(tsc_gpu_addr, tsc_limit)) {
+    if (channel_state->compute_sampler_table.Synchronize(tsc_gpu_addr, tsc_limit)) {
         channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
     }
-    if (channel_state->compute_image_table.Synchornize(kepler_compute->regs.tic.Address(),
+    if (channel_state->compute_image_table.Synchronize(kepler_compute->regs.tic.Address(),
                                                        tic_limit)) {
         channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
     }