Pica: Implement texture wrapping.
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@ -104,6 +104,11 @@ struct Regs {
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INSERT_PADDING_WORDS(0x17);
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struct TextureConfig {
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enum WrapMode : u32 {
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ClampToEdge = 0,
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Repeat = 2,
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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@ -111,7 +116,12 @@ struct Regs {
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BitField<16, 16, u32> width;
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};
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INSERT_PADDING_WORDS(0x2);
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union {
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BitField< 8, 2, WrapMode> wrap_s;
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BitField<11, 2, WrapMode> wrap_t;
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};
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INSERT_PADDING_WORDS(0x1);
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u32 address;
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@ -181,7 +181,7 @@ void ProcessTriangle(const VertexShader::OutputVertex& v0,
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if (!texture.enabled)
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continue;
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_dbg_assert_(GPU, 0 != texture.config.address);
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_dbg_assert_(HW_GPU, 0 != texture.config.address);
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// Images are split into 8x8 tiles. Each tile is composed of four 4x4 subtiles each
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// of which is composed of four 2x2 subtiles each of which is composed of four texels.
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@ -206,6 +206,25 @@ void ProcessTriangle(const VertexShader::OutputVertex& v0,
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// somewhat inefficient code around for now.
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int s = (int)(uv[i].u() * float24::FromFloat32(static_cast<float>(texture.config.width))).ToFloat32();
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int t = (int)(uv[i].v() * float24::FromFloat32(static_cast<float>(texture.config.height))).ToFloat32();
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auto GetWrappedTexCoord = [](Regs::TextureConfig::WrapMode mode, int val, unsigned size) {
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switch (mode) {
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case Regs::TextureConfig::ClampToEdge:
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val = std::max(val, 0);
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val = std::min(val, (int)size - 1);
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return val;
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case Regs::TextureConfig::Repeat:
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return (int)(((unsigned)val) % size);
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default:
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LOG_ERROR(HW_GPU, "Unknown texture coordinate wrapping mode %x\n", (int)mode);
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_dbg_assert_(HW_GPU, 0);
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return 0;
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}
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};
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s = GetWrappedTexCoord(registers.texture0.wrap_s, s, registers.texture0.width);
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t = GetWrappedTexCoord(registers.texture0.wrap_t, t, registers.texture0.height);
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int texel_index_within_tile = 0;
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for (int block_size_index = 0; block_size_index < 3; ++block_size_index) {
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int sub_tile_width = 1 << block_size_index;
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