Merge pull request #12237 from liamwhite/nce-sigtrap
nce: implement instruction emulation for misaligned memory accesses
This commit is contained in:
liamwhite
GitHub
commit
4f600f746a
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@ -174,7 +174,8 @@ android {
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"-DANDROID_ARM_NEON=true", // cryptopp requires Neon to work
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"-DYUZU_USE_BUNDLED_VCPKG=ON",
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"-DYUZU_USE_BUNDLED_FFMPEG=ON",
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"-DYUZU_ENABLE_LTO=ON"
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"-DYUZU_ENABLE_LTO=ON",
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"-DCMAKE_EXPORT_COMPILE_COMMANDS=ON"
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)
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abiFilters("arm64-v8a", "x86_64")
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@ -953,15 +953,19 @@ if (HAS_NCE)
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set(CMAKE_ASM_FLAGS "${CFLAGS} -x assembler-with-cpp")
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target_sources(core PRIVATE
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arm/nce/arm_nce_asm_definitions.h
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arm/nce/arm_nce.cpp
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arm/nce/arm_nce.h
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arm/nce/arm_nce.s
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arm/nce/guest_context.h
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arm/nce/instructions.h
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arm/nce/interpreter_visitor.cpp
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arm/nce/interpreter_visitor.h
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arm/nce/patcher.cpp
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arm/nce/patcher.h
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arm/nce/instructions.h
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arm/nce/visitor_base.h
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)
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target_link_libraries(core PRIVATE merry::oaknut)
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target_link_libraries(core PRIVATE merry::mcl merry::oaknut)
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endif()
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if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64)
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@ -6,7 +6,7 @@
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#include "common/signal_chain.h"
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#include "core/arm/nce/arm_nce.h"
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#include "core/arm/nce/guest_context.h"
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#include "core/arm/nce/interpreter_visitor.h"
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#include "core/arm/nce/patcher.h"
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#include "core/core.h"
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#include "core/memory.h"
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@ -21,7 +21,8 @@ namespace Core {
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namespace {
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struct sigaction g_orig_action;
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struct sigaction g_orig_bus_action;
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struct sigaction g_orig_segv_action;
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// Verify assembly offsets.
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using NativeExecutionParameters = Kernel::KThread::NativeExecutionParameters;
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@ -37,6 +38,9 @@ fpsimd_context* GetFloatingPointState(mcontext_t& host_ctx) {
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return reinterpret_cast<fpsimd_context*>(header);
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}
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using namespace Common::Literals;
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constexpr u32 StackSize = 32_KiB;
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} // namespace
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void* ArmNce::RestoreGuestContext(void* raw_context) {
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@ -104,19 +108,10 @@ void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
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host_ctx.regs[0] = guest_ctx->esr_el1.exchange(0);
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}
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bool ArmNce::HandleGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
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auto* info = static_cast<siginfo_t*>(raw_info);
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// Try to handle an invalid access.
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// TODO: handle accesses which split a page?
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const Common::ProcessAddress addr =
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(reinterpret_cast<u64>(info->si_addr) & ~Memory::YUZU_PAGEMASK);
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if (guest_ctx->system->ApplicationMemory().InvalidateNCE(addr, Memory::YUZU_PAGESIZE)) {
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// We handled the access successfully and are returning to guest code.
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return true;
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}
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// We can't handle the access, so determine why we crashed.
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const bool is_prefetch_abort = host_ctx.pc == reinterpret_cast<u64>(info->si_addr);
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@ -143,8 +138,44 @@ bool ArmNce::HandleGuestFault(GuestContext* guest_ctx, void* raw_info, void* raw
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return false;
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}
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void ArmNce::HandleHostFault(int sig, void* raw_info, void* raw_context) {
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return g_orig_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context);
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bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
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auto* fpctx = GetFloatingPointState(host_ctx);
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auto& memory = guest_ctx->system->ApplicationMemory();
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// Match and execute an instruction.
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auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx, fpctx);
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if (next_pc) {
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host_ctx.pc = *next_pc;
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return true;
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}
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// We couldn't handle the access.
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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bool ArmNce::HandleGuestAccessFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
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auto* info = static_cast<siginfo_t*>(raw_info);
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// Try to handle an invalid access.
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// TODO: handle accesses which split a page?
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const Common::ProcessAddress addr =
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(reinterpret_cast<u64>(info->si_addr) & ~Memory::YUZU_PAGEMASK);
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if (guest_ctx->system->ApplicationMemory().InvalidateNCE(addr, Memory::YUZU_PAGESIZE)) {
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// We handled the access successfully and are returning to guest code.
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return true;
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}
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// We couldn't handle the access.
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return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
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}
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void ArmNce::HandleHostAlignmentFault(int sig, void* raw_info, void* raw_context) {
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return g_orig_bus_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context);
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}
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void ArmNce::HandleHostAccessFault(int sig, void* raw_info, void* raw_context) {
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return g_orig_segv_action.sa_sigaction(sig, static_cast<siginfo_t*>(raw_info), raw_context);
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}
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void ArmNce::LockThread(Kernel::KThread* thread) {
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@ -225,18 +256,31 @@ ArmNce::ArmNce(System& system, bool uses_wall_clock, std::size_t core_index)
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ArmNce::~ArmNce() = default;
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void ArmNce::Initialize() {
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if (m_thread_id == -1) {
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m_thread_id = gettid();
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}
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// Setup our signals
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static std::once_flag signals;
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std::call_once(signals, [] {
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// Configure signal stack.
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if (!m_stack) {
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m_stack = std::make_unique<u8[]>(StackSize);
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stack_t ss{};
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ss.ss_sp = m_stack.get();
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ss.ss_size = StackSize;
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sigaltstack(&ss, nullptr);
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}
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// Set up signals.
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static std::once_flag flag;
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std::call_once(flag, [] {
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using HandlerType = decltype(sigaction::sa_sigaction);
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sigset_t signal_mask;
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sigemptyset(&signal_mask);
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sigaddset(&signal_mask, ReturnToRunCodeByExceptionLevelChangeSignal);
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sigaddset(&signal_mask, BreakFromRunCodeSignal);
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sigaddset(&signal_mask, GuestFaultSignal);
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sigaddset(&signal_mask, GuestAlignmentFaultSignal);
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sigaddset(&signal_mask, GuestAccessFaultSignal);
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struct sigaction return_to_run_code_action {};
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return_to_run_code_action.sa_flags = SA_SIGINFO | SA_ONSTACK;
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@ -253,18 +297,19 @@ void ArmNce::Initialize() {
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break_from_run_code_action.sa_mask = signal_mask;
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Common::SigAction(BreakFromRunCodeSignal, &break_from_run_code_action, nullptr);
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struct sigaction fault_action {};
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fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK | SA_RESTART;
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fault_action.sa_sigaction = reinterpret_cast<HandlerType>(&ArmNce::GuestFaultSignalHandler);
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fault_action.sa_mask = signal_mask;
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Common::SigAction(GuestFaultSignal, &fault_action, &g_orig_action);
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struct sigaction alignment_fault_action {};
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alignment_fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK;
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alignment_fault_action.sa_sigaction =
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reinterpret_cast<HandlerType>(&ArmNce::GuestAlignmentFaultSignalHandler);
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alignment_fault_action.sa_mask = signal_mask;
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Common::SigAction(GuestAlignmentFaultSignal, &alignment_fault_action, nullptr);
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// Simplify call for g_orig_action.
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// These fields occupy the same space in memory, so this should be a no-op in practice.
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if (!(g_orig_action.sa_flags & SA_SIGINFO)) {
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g_orig_action.sa_sigaction =
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reinterpret_cast<decltype(g_orig_action.sa_sigaction)>(g_orig_action.sa_handler);
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}
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struct sigaction access_fault_action {};
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access_fault_action.sa_flags = SA_SIGINFO | SA_ONSTACK | SA_RESTART;
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access_fault_action.sa_sigaction =
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reinterpret_cast<HandlerType>(&ArmNce::GuestAccessFaultSignalHandler);
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access_fault_action.sa_mask = signal_mask;
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Common::SigAction(GuestAccessFaultSignal, &access_fault_action, &g_orig_segv_action);
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});
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}
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@ -61,7 +61,8 @@ private:
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static void ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info,
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void* raw_context);
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static void BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context);
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static void GuestFaultSignalHandler(int sig, void* info, void* raw_context);
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static void GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context);
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static void GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context);
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static void LockThreadParameters(void* tpidr);
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static void UnlockThreadParameters(void* tpidr);
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@ -70,8 +71,11 @@ private:
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// C++ implementation functions for assembly definitions.
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static void* RestoreGuestContext(void* raw_context);
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static void SaveGuestContext(GuestContext* ctx, void* raw_context);
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static bool HandleGuestFault(GuestContext* ctx, void* info, void* raw_context);
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static void HandleHostFault(int sig, void* info, void* raw_context);
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static bool HandleFailedGuestFault(GuestContext* ctx, void* info, void* raw_context);
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static bool HandleGuestAlignmentFault(GuestContext* ctx, void* info, void* raw_context);
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static bool HandleGuestAccessFault(GuestContext* ctx, void* info, void* raw_context);
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static void HandleHostAlignmentFault(int sig, void* info, void* raw_context);
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static void HandleHostAccessFault(int sig, void* info, void* raw_context);
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public:
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Core::System& m_system;
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@ -83,6 +87,9 @@ public:
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// Core context.
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GuestContext m_guest_ctx{};
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Kernel::KThread* m_running_thread{};
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// Stack for signal processing.
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std::unique_ptr<u8[]> m_stack{};
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};
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} // namespace Core
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@ -130,11 +130,11 @@ _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
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ret
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/* static void Core::ArmNce::GuestFaultSignalHandler(int sig, void* info, void* raw_context) */
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.section .text._ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_, %function
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_ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_:
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/* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */
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.section .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function
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_ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
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/* Check to see if we have the correct TLS magic. */
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mrs x8, tpidr_el0
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ldr w9, [x8, #(TpidrEl0TlsMagic)]
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@ -146,7 +146,7 @@ _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_:
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/* Incorrect TLS magic, so this is a host fault. */
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/* Tail call the handler. */
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b _ZN4Core6ArmNce15HandleHostFaultEiPvS1_
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b _ZN4Core6ArmNce24HandleHostAlignmentFaultEiPvS1_
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1:
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/* Correct TLS magic, so this is a guest fault. */
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@ -163,7 +163,53 @@ _ZN4Core6ArmNce23GuestFaultSignalHandlerEiPvS1_:
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msr tpidr_el0, x3
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/* Call the handler. */
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bl _ZN4Core6ArmNce16HandleGuestFaultEPNS_12GuestContextEPvS3_
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bl _ZN4Core6ArmNce25HandleGuestAlignmentFaultEPNS_12GuestContextEPvS3_
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/* If the handler returned false, we want to preserve the host tpidr_el0. */
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cbz x0, 2f
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/* Otherwise, restore guest tpidr_el0. */
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msr tpidr_el0, x19
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2:
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ldr x19, [sp, #0x10]
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ldp x29, x30, [sp], #0x20
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ret
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/* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */
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.section .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits
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.global _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
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.type _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function
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_ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
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/* Check to see if we have the correct TLS magic. */
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mrs x8, tpidr_el0
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ldr w9, [x8, #(TpidrEl0TlsMagic)]
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LOAD_IMMEDIATE_32(w10, TlsMagic)
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cmp w9, w10
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b.eq 1f
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/* Incorrect TLS magic, so this is a host fault. */
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/* Tail call the handler. */
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b _ZN4Core6ArmNce21HandleHostAccessFaultEiPvS1_
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1:
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/* Correct TLS magic, so this is a guest fault. */
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stp x29, x30, [sp, #-0x20]!
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str x19, [sp, #0x10]
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mov x29, sp
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/* Save the old tpidr_el0. */
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mov x19, x8
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/* Restore host tpidr_el0. */
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ldr x0, [x8, #(TpidrEl0NativeContext)]
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ldr x3, [x0, #(GuestContextHostContext + HostContextTpidrEl0)]
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msr tpidr_el0, x3
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/* Call the handler. */
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bl _ZN4Core6ArmNce22HandleGuestAccessFaultEPNS_12GuestContextEPvS3_
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/* If the handler returned false, we want to preserve the host tpidr_el0. */
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cbz x0, 2f
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@ -10,7 +10,8 @@
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#define ReturnToRunCodeByExceptionLevelChangeSignal SIGUSR2
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#define BreakFromRunCodeSignal SIGURG
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#define GuestFaultSignal SIGSEGV
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#define GuestAccessFaultSignal SIGSEGV
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#define GuestAlignmentFaultSignal SIGBUS
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#define GuestContextSp 0xF8
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#define GuestContextHostContext 0x320
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@ -0,0 +1,825 @@
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/bit_cast.h"
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#include "core/arm/nce/interpreter_visitor.h"
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#include <dynarmic/frontend/A64/decoder/a64.h>
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namespace Core {
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template <u32 BitSize>
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u64 SignExtendToLong(u64 value) {
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u64 mask = 1ULL << (BitSize - 1);
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value &= (1ULL << BitSize) - 1;
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return (value ^ mask) - mask;
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}
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static u64 SignExtendToLong(u64 value, u64 bitsize) {
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switch (bitsize) {
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case 8:
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return SignExtendToLong<8>(value);
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case 16:
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return SignExtendToLong<16>(value);
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case 32:
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return SignExtendToLong<32>(value);
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default:
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return value;
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}
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}
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template <u64 BitSize>
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u32 SignExtendToWord(u32 value) {
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u32 mask = 1ULL << (BitSize - 1);
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value &= (1ULL << BitSize) - 1;
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return (value ^ mask) - mask;
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}
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static u32 SignExtendToWord(u32 value, u64 bitsize) {
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switch (bitsize) {
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case 8:
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return SignExtendToWord<8>(value);
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case 16:
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return SignExtendToWord<16>(value);
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default:
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return value;
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}
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}
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static u64 SignExtend(u64 value, u64 bitsize, u64 regsize) {
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if (regsize == 64) {
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return SignExtendToLong(value, bitsize);
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} else {
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return SignExtendToWord(static_cast<u32>(value), bitsize);
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}
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}
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static u128 VectorGetElement(u128 value, u64 bitsize) {
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switch (bitsize) {
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case 8:
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return {value[0] & ((1ULL << 8) - 1), 0};
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case 16:
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return {value[0] & ((1ULL << 16) - 1), 0};
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case 32:
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return {value[0] & ((1ULL << 32) - 1), 0};
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case 64:
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return {value[0], 0};
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default:
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return value;
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}
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}
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u64 InterpreterVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {
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ASSERT(shift <= 4);
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ASSERT(bitsize == 32 || bitsize == 64);
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u64 val = this->GetReg(reg);
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size_t len;
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||||
u64 extended;
|
||||
bool signed_extend;
|
||||
|
||||
switch (option.ZeroExtend()) {
|
||||
case 0b000: { // UXTB
|
||||
val &= ((1ULL << 8) - 1);
|
||||
len = 8;
|
||||
signed_extend = false;
|
||||
break;
|
||||
}
|
||||
case 0b001: { // UXTH
|
||||
val &= ((1ULL << 16) - 1);
|
||||
len = 16;
|
||||
signed_extend = false;
|
||||
break;
|
||||
}
|
||||
case 0b010: { // UXTW
|
||||
val &= ((1ULL << 32) - 1);
|
||||
len = 32;
|
||||
signed_extend = false;
|
||||
break;
|
||||
}
|
||||
case 0b011: { // UXTX
|
||||
len = 64;
|
||||
signed_extend = false;
|
||||
break;
|
||||
}
|
||||
case 0b100: { // SXTB
|
||||
val &= ((1ULL << 8) - 1);
|
||||
len = 8;
|
||||
signed_extend = true;
|
||||
break;
|
||||
}
|
||||
case 0b101: { // SXTH
|
||||
val &= ((1ULL << 16) - 1);
|
||||
len = 16;
|
||||
signed_extend = true;
|
||||
break;
|
||||
}
|
||||
case 0b110: { // SXTW
|
||||
val &= ((1ULL << 32) - 1);
|
||||
len = 32;
|
||||
signed_extend = true;
|
||||
break;
|
||||
}
|
||||
case 0b111: { // SXTX
|
||||
len = 64;
|
||||
signed_extend = true;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
if (len < bitsize && signed_extend) {
|
||||
extended = SignExtend(val, len, bitsize);
|
||||
} else {
|
||||
extended = val;
|
||||
}
|
||||
|
||||
return extended << shift;
|
||||
}
|
||||
|
||||
u128 InterpreterVisitor::GetVec(Vec v) {
|
||||
return m_fpsimd_regs[static_cast<u32>(v)];
|
||||
}
|
||||
|
||||
u64 InterpreterVisitor::GetReg(Reg r) {
|
||||
return m_regs[static_cast<u32>(r)];
|
||||
}
|
||||
|
||||
u64 InterpreterVisitor::GetSp() {
|
||||
return m_sp;
|
||||
}
|
||||
|
||||
u64 InterpreterVisitor::GetPc() {
|
||||
return m_pc;
|
||||
}
|
||||
|
||||
void InterpreterVisitor::SetVec(Vec v, u128 value) {
|
||||
m_fpsimd_regs[static_cast<u32>(v)] = value;
|
||||
}
|
||||
|
||||
void InterpreterVisitor::SetReg(Reg r, u64 value) {
|
||||
m_regs[static_cast<u32>(r)] = value;
|
||||
}
|
||||
|
||||
void InterpreterVisitor::SetSp(u64 value) {
|
||||
m_sp = value;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt) {
|
||||
const auto memop = L ? MemOp::Load : MemOp::Store;
|
||||
const size_t elsize = 8 << size;
|
||||
const size_t datasize = elsize;
|
||||
|
||||
// Operation
|
||||
const size_t dbytes = datasize / 8;
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
std::atomic_thread_fence(std::memory_order_seq_cst);
|
||||
u64 value = this->GetReg(Rt);
|
||||
m_memory.WriteBlock(address, &value, dbytes);
|
||||
std::atomic_thread_fence(std::memory_order_seq_cst);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u64 value = 0;
|
||||
m_memory.ReadBlock(address, &value, dbytes);
|
||||
this->SetReg(Rt, value);
|
||||
std::atomic_thread_fence(std::memory_order_seq_cst);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) {
|
||||
const size_t size = sz.ZeroExtend<size_t>();
|
||||
const bool L = 0;
|
||||
const bool o0 = 0;
|
||||
return this->Ordered(size, L, o0, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
|
||||
const size_t size = sz.ZeroExtend<size_t>();
|
||||
const bool L = 0;
|
||||
const bool o0 = 1;
|
||||
return this->Ordered(size, L, o0, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) {
|
||||
const size_t size = sz.ZeroExtend<size_t>();
|
||||
const bool L = 1;
|
||||
const bool o0 = 0;
|
||||
return this->Ordered(size, L, o0, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) {
|
||||
const size_t size = sz.ZeroExtend<size_t>();
|
||||
const bool L = 1;
|
||||
const bool o0 = 1;
|
||||
return this->Ordered(size, L, o0, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
|
||||
const size_t size = opc_0 == 0 ? 4 : 8;
|
||||
const s64 offset = Dynarmic::concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
|
||||
const u64 address = this->GetPc() + offset;
|
||||
|
||||
u64 data = 0;
|
||||
m_memory.ReadBlock(address, &data, size);
|
||||
|
||||
this->SetReg(Rt, data);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
|
||||
if (opc == 0b11) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const u64 size = 4 << opc.ZeroExtend();
|
||||
const u64 offset = imm19.SignExtend<u64>() << 2;
|
||||
const u64 address = this->GetPc() + offset;
|
||||
|
||||
u128 data{};
|
||||
m_memory.ReadBlock(address, &data, size);
|
||||
this->SetVec(Vt, data);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L,
|
||||
Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
|
||||
if ((L == 0 && opc.Bit<0>() == 1) || opc == 0b11) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto memop = L == 1 ? MemOp::Load : MemOp::Store;
|
||||
if (memop == MemOp::Load && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
if (memop == MemOp::Store && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
if (memop == MemOp::Load && Rt == Rt2) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
|
||||
const bool postindex = !not_postindex;
|
||||
const bool signed_ = opc.Bit<0>() != 0;
|
||||
const size_t scale = 2 + opc.Bit<1>();
|
||||
const size_t datasize = 8 << scale;
|
||||
const u64 offset = imm7.SignExtend<u64>() << scale;
|
||||
|
||||
if (!postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
const size_t dbytes = datasize / 8;
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u64 data1 = this->GetReg(Rt);
|
||||
u64 data2 = this->GetReg(Rt2);
|
||||
m_memory.WriteBlock(address, &data1, dbytes);
|
||||
m_memory.WriteBlock(address + dbytes, &data2, dbytes);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u64 data1 = 0, data2 = 0;
|
||||
m_memory.ReadBlock(address, &data1, dbytes);
|
||||
m_memory.ReadBlock(address + dbytes, &data2, dbytes);
|
||||
if (signed_) {
|
||||
this->SetReg(Rt, SignExtend(data1, datasize, 64));
|
||||
this->SetReg(Rt2, SignExtend(data2, datasize, 64));
|
||||
} else {
|
||||
this->SetReg(Rt, data1);
|
||||
this->SetReg(Rt2, data2);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
if (wback) {
|
||||
if (postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
if (Rn == Reg::SP) {
|
||||
this->SetSp(address);
|
||||
} else {
|
||||
this->SetReg(Rn, address);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L,
|
||||
Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) {
|
||||
if (opc == 0b11) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto memop = L == 1 ? MemOp::Load : MemOp::Store;
|
||||
if (memop == MemOp::Load && Vt == Vt2) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
|
||||
const bool postindex = !not_postindex;
|
||||
const size_t scale = 2 + opc.ZeroExtend<size_t>();
|
||||
const size_t datasize = 8 << scale;
|
||||
const u64 offset = imm7.SignExtend<u64>() << scale;
|
||||
const size_t dbytes = datasize / 8;
|
||||
|
||||
if (!postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u128 data1 = VectorGetElement(this->GetVec(Vt), datasize);
|
||||
u128 data2 = VectorGetElement(this->GetVec(Vt2), datasize);
|
||||
m_memory.WriteBlock(address, &data1, dbytes);
|
||||
m_memory.WriteBlock(address + dbytes, &data2, dbytes);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u128 data1{}, data2{};
|
||||
m_memory.ReadBlock(address, &data1, dbytes);
|
||||
m_memory.ReadBlock(address + dbytes, &data2, dbytes);
|
||||
this->SetVec(Vt, data1);
|
||||
this->SetVec(Vt2, data2);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
if (wback) {
|
||||
if (postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
if (Rn == Reg::SP) {
|
||||
this->SetSp(address);
|
||||
} else {
|
||||
this->SetReg(Rn, address);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset,
|
||||
Imm<2> size, Imm<2> opc, Reg Rn, Reg Rt) {
|
||||
MemOp memop;
|
||||
bool signed_ = false;
|
||||
size_t regsize = 0;
|
||||
|
||||
if (opc.Bit<1>() == 0) {
|
||||
memop = opc.Bit<0>() ? MemOp::Load : MemOp::Store;
|
||||
regsize = size == 0b11 ? 64 : 32;
|
||||
signed_ = false;
|
||||
} else if (size == 0b11) {
|
||||
memop = MemOp::Prefetch;
|
||||
ASSERT(!opc.Bit<0>());
|
||||
} else {
|
||||
memop = MemOp::Load;
|
||||
ASSERT(!(size == 0b10 && opc.Bit<0>() == 1));
|
||||
regsize = opc.Bit<0>() ? 32 : 64;
|
||||
signed_ = true;
|
||||
}
|
||||
|
||||
if (memop == MemOp::Load && wback && Rn == Rt && Rn != Reg::R31) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
if (memop == MemOp::Store && wback && Rn == Rt && Rn != Reg::R31) {
|
||||
// Unpredictable instruction
|
||||
return false;
|
||||
}
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
if (!postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
const size_t datasize = 8 << scale;
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u64 data = this->GetReg(Rt);
|
||||
m_memory.WriteBlock(address, &data, datasize / 8);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u64 data = 0;
|
||||
m_memory.ReadBlock(address, &data, datasize / 8);
|
||||
if (signed_) {
|
||||
this->SetReg(Rt, SignExtend(data, datasize, regsize));
|
||||
} else {
|
||||
this->SetReg(Rt, data);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MemOp::Prefetch:
|
||||
// this->Prefetch(address, Rt)
|
||||
break;
|
||||
}
|
||||
|
||||
if (wback) {
|
||||
if (postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
if (Rn == Reg::SP) {
|
||||
this->SetSp(address);
|
||||
} else {
|
||||
this->SetReg(Rn, address);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex,
|
||||
Reg Rn, Reg Rt) {
|
||||
const bool wback = true;
|
||||
const bool postindex = !not_postindex;
|
||||
const size_t scale = size.ZeroExtend<size_t>();
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) {
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const size_t scale = size.ZeroExtend<size_t>();
|
||||
const u64 offset = imm12.ZeroExtend<u64>() << scale;
|
||||
|
||||
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const size_t scale = size.ZeroExtend<size_t>();
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset,
|
||||
MemOp memop, Reg Rn, Vec Vt) {
|
||||
const size_t datasize = 8 << scale;
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
|
||||
if (!postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u128 data = VectorGetElement(this->GetVec(Vt), datasize);
|
||||
m_memory.WriteBlock(address, &data, datasize / 8);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u128 data{};
|
||||
m_memory.ReadBlock(address, &data, datasize);
|
||||
this->SetVec(Vt, data);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
if (wback) {
|
||||
if (postindex) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
if (Rn == Reg::SP) {
|
||||
this->SetSp(address);
|
||||
} else {
|
||||
this->SetReg(Rn, address);
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9,
|
||||
bool not_postindex, Reg Rn, Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = true;
|
||||
const bool postindex = !not_postindex;
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn,
|
||||
Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const u64 offset = imm12.ZeroExtend<u64>() << scale;
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9,
|
||||
bool not_postindex, Reg Rn, Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = true;
|
||||
const bool postindex = !not_postindex;
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn,
|
||||
Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const u64 offset = imm12.ZeroExtend<u64>() << scale;
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
|
||||
const bool wback = false;
|
||||
const bool postindex = false;
|
||||
const u64 offset = imm9.SignExtend<u64>();
|
||||
|
||||
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1,
|
||||
Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Reg Rt) {
|
||||
MemOp memop;
|
||||
size_t regsize = 64;
|
||||
bool signed_ = false;
|
||||
|
||||
if (opc_1 == 0) {
|
||||
memop = opc_0 == 1 ? MemOp::Load : MemOp::Store;
|
||||
regsize = size == 0b11 ? 64 : 32;
|
||||
signed_ = false;
|
||||
} else if (size == 0b11) {
|
||||
memop = MemOp::Prefetch;
|
||||
if (opc_0 == 1) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
memop = MemOp::Load;
|
||||
if (size == 0b10 && opc_0 == 1) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
regsize = opc_0 == 1 ? 32 : 64;
|
||||
signed_ = true;
|
||||
}
|
||||
|
||||
const size_t datasize = 8 << scale;
|
||||
|
||||
// Operation
|
||||
const u64 offset = this->ExtendReg(64, Rm, option, shift);
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
address += offset;
|
||||
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u64 data = this->GetReg(Rt);
|
||||
m_memory.WriteBlock(address, &data, datasize / 8);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u64 data = 0;
|
||||
m_memory.ReadBlock(address, &data, datasize / 8);
|
||||
if (signed_) {
|
||||
this->SetReg(Rt, SignExtend(data, datasize, regsize));
|
||||
} else {
|
||||
this->SetReg(Rt, data);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MemOp::Prefetch:
|
||||
break;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Reg Rt) {
|
||||
const Imm<1> opc_0{0};
|
||||
const size_t scale = size.ZeroExtend<size_t>();
|
||||
const u8 shift = S ? static_cast<u8>(scale) : 0;
|
||||
if (!option.Bit<1>()) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Reg Rt) {
|
||||
const Imm<1> opc_0{1};
|
||||
const size_t scale = size.ZeroExtend<size_t>();
|
||||
const u8 shift = S ? static_cast<u8>(scale) : 0;
|
||||
if (!option.Bit<1>()) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option,
|
||||
Reg Rn, Vec Vt) {
|
||||
const auto memop = opc_0 == 1 ? MemOp::Load : MemOp::Store;
|
||||
const size_t datasize = 8 << scale;
|
||||
|
||||
// Operation
|
||||
const u64 offset = this->ExtendReg(64, Rm, option, shift);
|
||||
|
||||
u64 address;
|
||||
if (Rn == Reg::SP) {
|
||||
address = this->GetSp();
|
||||
} else {
|
||||
address = this->GetReg(Rn);
|
||||
}
|
||||
address += offset;
|
||||
|
||||
switch (memop) {
|
||||
case MemOp::Store: {
|
||||
u128 data = VectorGetElement(this->GetVec(Vt), datasize);
|
||||
m_memory.WriteBlock(address, &data, datasize / 8);
|
||||
break;
|
||||
}
|
||||
case MemOp::Load: {
|
||||
u128 data{};
|
||||
m_memory.ReadBlock(address, &data, datasize / 8);
|
||||
this->SetVec(Vt, data);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S,
|
||||
Reg Rn, Vec Vt) {
|
||||
const Imm<1> opc_0{0};
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
const u8 shift = S ? static_cast<u8>(scale) : 0;
|
||||
if (!option.Bit<1>()) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
|
||||
}
|
||||
|
||||
bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S,
|
||||
Reg Rn, Vec Vt) {
|
||||
const Imm<1> opc_0{1};
|
||||
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>();
|
||||
if (scale > 4) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
const u8 shift = S ? static_cast<u8>(scale) : 0;
|
||||
if (!option.Bit<1>()) {
|
||||
// Unallocated encoding
|
||||
return false;
|
||||
}
|
||||
return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
|
||||
}
|
||||
|
||||
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
|
||||
fpsimd_context* fpsimd_context) {
|
||||
// Construct the interpreter.
|
||||
std::span<u64, 31> regs(reinterpret_cast<u64*>(context->regs), 31);
|
||||
std::span<u128, 32> vregs(reinterpret_cast<u128*>(fpsimd_context->vregs), 32);
|
||||
u64& sp = *reinterpret_cast<u64*>(&context->sp);
|
||||
const u64& pc = *reinterpret_cast<u64*>(&context->pc);
|
||||
|
||||
InterpreterVisitor visitor(memory, regs, vregs, sp, pc);
|
||||
|
||||
// Read the instruction at the program counter.
|
||||
u32 instruction = memory.Read32(pc);
|
||||
bool was_executed = false;
|
||||
|
||||
// Interpret the instruction.
|
||||
if (auto decoder = Dynarmic::A64::Decode<VisitorBase>(instruction)) {
|
||||
was_executed = decoder->get().call(visitor, instruction);
|
||||
} else {
|
||||
LOG_ERROR(Core_ARM, "Unallocated encoding: {:#x}", instruction);
|
||||
}
|
||||
|
||||
if (was_executed) {
|
||||
return pc + 4;
|
||||
}
|
||||
|
||||
return std::nullopt;
|
||||
}
|
||||
|
||||
} // namespace Core
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
|
||||
// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <signal.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "core/arm/nce/visitor_base.h"
|
||||
|
||||
namespace Core {
|
||||
|
||||
namespace Memory {
|
||||
class Memory;
|
||||
}
|
||||
|
||||
class InterpreterVisitor final : public VisitorBase {
|
||||
public:
|
||||
explicit InterpreterVisitor(Core::Memory::Memory& memory, std::span<u64, 31> regs,
|
||||
std::span<u128, 32> fpsimd_regs, u64& sp, const u64& pc)
|
||||
: m_memory(memory), m_regs(regs), m_fpsimd_regs(fpsimd_regs), m_sp(sp), m_pc(pc) {}
|
||||
~InterpreterVisitor() override = default;
|
||||
|
||||
enum class MemOp {
|
||||
Load,
|
||||
Store,
|
||||
Prefetch,
|
||||
};
|
||||
|
||||
u128 GetVec(Vec v);
|
||||
u64 GetReg(Reg r);
|
||||
u64 GetSp();
|
||||
u64 GetPc();
|
||||
|
||||
void SetVec(Vec v, u128 value);
|
||||
void SetReg(Reg r, u64 value);
|
||||
void SetSp(u64 value);
|
||||
|
||||
u64 ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift);
|
||||
|
||||
// Loads and stores - Load/Store Exclusive
|
||||
bool Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt);
|
||||
bool STLLR(Imm<2> size, Reg Rn, Reg Rt) override;
|
||||
bool STLR(Imm<2> size, Reg Rn, Reg Rt) override;
|
||||
bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) override;
|
||||
bool LDAR(Imm<2> size, Reg Rn, Reg Rt) override;
|
||||
|
||||
// Loads and stores - Load register (literal)
|
||||
bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) override;
|
||||
bool LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) override;
|
||||
|
||||
// Loads and stores - Load/Store register pair
|
||||
bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2,
|
||||
Reg Rn, Reg Rt) override;
|
||||
bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Vec Vt2,
|
||||
Reg Rn, Vec Vt) override;
|
||||
|
||||
// Loads and stores - Load/Store register (immediate)
|
||||
bool RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset, Imm<2> size,
|
||||
Imm<2> opc, Reg Rn, Reg Rt);
|
||||
bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn,
|
||||
Reg Rt) override;
|
||||
bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) override;
|
||||
bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override;
|
||||
|
||||
bool SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn,
|
||||
Vec Vt);
|
||||
bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn,
|
||||
Vec Vt) override;
|
||||
bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override;
|
||||
bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn,
|
||||
Vec Vt) override;
|
||||
bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override;
|
||||
bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override;
|
||||
bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override;
|
||||
|
||||
// Loads and stores - Load/Store register (register offset)
|
||||
bool RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1, Imm<1> opc_0, Reg Rm,
|
||||
Imm<3> option, Reg Rn, Reg Rt);
|
||||
bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Reg Rt) override;
|
||||
bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Reg Rt) override;
|
||||
|
||||
bool SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Vec Vt);
|
||||
bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Vec Vt) override;
|
||||
bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn,
|
||||
Vec Vt) override;
|
||||
|
||||
private:
|
||||
Core::Memory::Memory& m_memory;
|
||||
std::span<u64, 31> m_regs;
|
||||
std::span<u128, 32> m_fpsimd_regs;
|
||||
u64& m_sp;
|
||||
const u64& m_pc;
|
||||
};
|
||||
|
||||
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context,
|
||||
fpsimd_context* fpsimd_context);
|
||||
|
||||
} // namespace Core
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue