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shader: Implement FLO

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This commit is contained in:
ameerj
2021-03-01 15:58:16 -05:00
parent e038928616
commit 103b9da4f7
8 changed files with 75 additions and 18 deletions
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1
src/shader_recompiler/CMakeLists.txt
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@@ -64,6 +64,7 @@ add_library(shader_recompiler STATIC
frontend/maxwell/translate/impl/common_encoding.h
frontend/maxwell/translate/impl/common_funcs.cpp
frontend/maxwell/translate/impl/common_funcs.h
frontend/maxwell/translate/impl/find_leading_one.cpp
frontend/maxwell/translate/impl/floating_point_add.cpp
frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp

4
src/shader_recompiler/backend/spirv/emit_spirv.h
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@@ -229,7 +229,9 @@ Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
Id EmitBitReverse32(EmitContext& ctx, Id value);
Id EmitBitCount32(EmitContext& ctx, Id value);
Id EmitBitwiseNot32(EmitContext& ctx, Id a);
Id EmitBitwiseNot32(EmitContext& ctx, Id value);
Id EmitFindSMsb32(EmitContext& ctx, Id value);
Id EmitFindUMsb32(EmitContext& ctx, Id value);
Id EmitSMin32(EmitContext& ctx, Id a, Id b);
Id EmitUMin32(EmitContext& ctx, Id a, Id b);
Id EmitSMax32(EmitContext& ctx, Id a, Id b);

12
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
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@@ -110,8 +110,16 @@ Id EmitBitCount32(EmitContext& ctx, Id value) {
return ctx.OpBitCount(ctx.U32[1], value);
}
Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
return ctx.OpNot(ctx.U32[1], a);
Id EmitBitwiseNot32(EmitContext& ctx, Id value) {
return ctx.OpNot(ctx.U32[1], value);
}
Id EmitFindSMsb32(EmitContext& ctx, Id value) {
return ctx.OpFindSMsb(ctx.U32[1], value);
}
Id EmitFindUMsb32(EmitContext& ctx, Id value) {
return ctx.OpFindUMsb(ctx.U32[1], value);
}
Id EmitSMin32(EmitContext& ctx, Id a, Id b) {

12
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@@ -812,8 +812,16 @@ U32 IREmitter::BitCount(const U32& value) {
return Inst<U32>(Opcode::BitCount32, value);
}
U32 IREmitter::BitwiseNot(const U32& a) {
return Inst<U32>(Opcode::BitwiseNot32, a);
U32 IREmitter::BitwiseNot(const U32& value) {
return Inst<U32>(Opcode::BitwiseNot32, value);
}
U32 IREmitter::FindSMsb(const U32& value) {
return Inst<U32>(Opcode::FindSMsb32, value);
}
U32 IREmitter::FindUMsb(const U32& value) {
return Inst<U32>(Opcode::FindUMsb32, value);
}
U32 IREmitter::SMin(const U32& a, const U32& b) {

4
src/shader_recompiler/frontend/ir/ir_emitter.h
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@@ -161,8 +161,10 @@ public:
bool is_signed);
[[nodiscard]] U32 BitReverse(const U32& value);
[[nodiscard]] U32 BitCount(const U32& value);
[[nodiscard]] U32 BitwiseNot(const U32& a);
[[nodiscard]] U32 BitwiseNot(const U32& value);
[[nodiscard]] U32 FindSMsb(const U32& value);
[[nodiscard]] U32 FindUMsb(const U32& value);
[[nodiscard]] U32 SMin(const U32& a, const U32& b);
[[nodiscard]] U32 UMin(const U32& a, const U32& b);
[[nodiscard]] U32 SMax(const U32& a, const U32& b);

2
src/shader_recompiler/frontend/ir/opcodes.inc
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@@ -235,6 +235,8 @@ OPCODE(BitReverse32, U32, U32,
OPCODE(BitCount32, U32, U32, )
OPCODE(BitwiseNot32, U32, U32, )
OPCODE(FindSMsb32, U32, U32, )
OPCODE(FindUMsb32, U32, U32, )
OPCODE(SMin32, U32, U32, U32, )
OPCODE(UMin32, U32, U32, U32, )
OPCODE(SMax32, U32, U32, U32, )

46
src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp Normal file
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@@ -0,0 +1,46 @@
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<40, 1, u64> tilde;
BitField<41, 1, u64> shift;
BitField<48, 1, u64> is_signed;
} const flo{insn};
const bool invert{flo.tilde != 0};
const bool is_signed{flo.is_signed != 0};
const bool shift_op{flo.shift != 0};
const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src};
const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)};
const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))};
const IR::U32 offset{v.ir.Imm32(31)};
const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result};
const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)};
v.X(flo.dest_reg, result);
}
} // Anonymous namespace
void TranslatorVisitor::FLO_reg(u64 insn) {
FLO(*this, insn, GetReg20(insn));
}
void TranslatorVisitor::FLO_cbuf(u64 insn) {
FLO(*this, insn, GetCbuf(insn));
}
void TranslatorVisitor::FLO_imm(u64 insn) {
FLO(*this, insn, GetImm20(insn));
}
} // namespace Shader::Maxwell

12
src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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@@ -217,18 +217,6 @@ void TranslatorVisitor::FCMP_imm(u64) {
ThrowNotImplemented(Opcode::FCMP_imm);
}
void TranslatorVisitor::FLO_reg(u64) {
ThrowNotImplemented(Opcode::FLO_reg);
}
void TranslatorVisitor::FLO_cbuf(u64) {
ThrowNotImplemented(Opcode::FLO_cbuf);
}
void TranslatorVisitor::FLO_imm(u64) {
ThrowNotImplemented(Opcode::FLO_imm);
}
void TranslatorVisitor::FMNMX_reg(u64) {
ThrowNotImplemented(Opcode::FMNMX_reg);
}