717 lines
18 KiB
C
717 lines
18 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <soc/clock.h>
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#include <soc/t210.h>
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#include <storage/sdmmc.h>
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#include <utils/util.h>
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/*
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* CLOCK Peripherals:
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* L 0 - 31
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* H 32 - 63
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* U 64 - 95
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* V 96 - 127
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* W 128 - 159
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* X 160 - 191
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* Y 192 - 223
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*/
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/* clock_t: reset, enable, source, index, clk_src, clk_div */
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static const clock_t _clock_uart[] = {
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/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 2 },
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/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 2 },
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/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 23, 0, 2 },
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/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, 1, 0, 2 },
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/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
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};
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//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
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static const clock_t _clock_i2c[] = {
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
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/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C4 */ { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, 7, 0, 19 }, //20.4MHz -> 100KHz
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C6 */ { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, 6, 0, 19 } //20.4MHz -> 100KHz
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};
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static clock_t _clock_se = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 31, 0, 0
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};
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static clock_t _clock_tzram = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 30, 0, 0
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};
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static clock_t _clock_host1x = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3
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};
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static clock_t _clock_tsec = {
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CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 19, 0, 2
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};
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static clock_t _clock_sor_safe = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 30, 0, 0
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};
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static clock_t _clock_sor0 = {
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CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 22, 0, 0
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};
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static clock_t _clock_sor1 = {
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CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 23, 0, 2
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};
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static clock_t _clock_kfuse = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0
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};
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static clock_t _clock_cl_dvfs = {
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CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 27, 0, 0
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};
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static clock_t _clock_coresight = {
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CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4
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};
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static clock_t _clock_pwm = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz.
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};
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static clock_t _clock_sdmmc_legacy_tm = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
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};
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void clock_enable(const clock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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// Configure clock source if required.
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if (clk->source)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
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usleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~(1 << clk->index);
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}
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void clock_disable(const clock_t *clk)
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{
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// Put clock into reset.
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CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
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// Disable.
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CLOCK(clk->enable) &= ~(1 << clk->index);
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}
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void clock_enable_fuse(bool enable)
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{
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CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
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}
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void clock_enable_uart(u32 idx)
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{
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clock_enable(&_clock_uart[idx]);
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}
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void clock_disable_uart(u32 idx)
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{
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clock_disable(&_clock_uart[idx]);
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}
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#define UART_SRC_CLK_DIV_EN (1 << 24)
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int clock_uart_use_src_div(u32 idx, u32 baud)
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{
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u32 clk_src_div = CLOCK(_clock_uart[idx].source) & 0xE0000000;
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if (baud == 1000000)
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CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 49;
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else
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{
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CLOCK(_clock_uart[idx].source) = clk_src_div | 2;
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return 1;
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}
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return 0;
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}
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void clock_enable_i2c(u32 idx)
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{
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clock_enable(&_clock_i2c[idx]);
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}
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void clock_disable_i2c(u32 idx)
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{
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clock_disable(&_clock_i2c[idx]);
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}
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void clock_enable_se()
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{
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clock_enable(&_clock_se);
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}
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void clock_enable_tzram()
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{
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clock_enable(&_clock_tzram);
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}
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void clock_enable_host1x()
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{
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clock_enable(&_clock_host1x);
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}
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void clock_disable_host1x()
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{
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clock_disable(&_clock_host1x);
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}
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void clock_enable_tsec()
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{
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clock_enable(&_clock_tsec);
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}
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void clock_disable_tsec()
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{
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clock_disable(&_clock_tsec);
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}
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void clock_enable_sor_safe()
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{
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clock_enable(&_clock_sor_safe);
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}
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void clock_disable_sor_safe()
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{
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clock_disable(&_clock_sor_safe);
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}
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void clock_enable_sor0()
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{
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clock_enable(&_clock_sor0);
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}
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void clock_disable_sor0()
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{
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clock_disable(&_clock_sor0);
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}
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void clock_enable_sor1()
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{
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clock_enable(&_clock_sor1);
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}
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void clock_disable_sor1()
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{
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clock_disable(&_clock_sor1);
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}
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void clock_enable_kfuse()
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{
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//clock_enable(&_clock_kfuse);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
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usleep(10);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
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usleep(20);
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}
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void clock_disable_kfuse()
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{
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clock_disable(&_clock_kfuse);
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}
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void clock_enable_cl_dvfs()
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{
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clock_enable(&_clock_cl_dvfs);
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}
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void clock_disable_cl_dvfs()
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{
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clock_disable(&_clock_cl_dvfs);
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}
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void clock_enable_coresight()
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{
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clock_enable(&_clock_coresight);
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}
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void clock_disable_coresight()
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{
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clock_disable(&_clock_coresight);
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}
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void clock_enable_pwm()
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{
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clock_enable(&_clock_pwm);
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}
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void clock_disable_pwm()
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{
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clock_disable(&_clock_pwm);
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}
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void clock_enable_pllc(u32 divn)
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{
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u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
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// Check if already enabled and configured.
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if ((CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_ENABLE) && (pll_divn_curr == divn))
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return;
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// Take PLLC out of reset and set basic misc parameters.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
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((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
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usleep(10);
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// Set PLLC dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = (divn << 10) | 4; // DIVM: 4, DIVP: 1.
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// Enable PLLC and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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msleep(1); // Wait a bit for PLL to stabilize.
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}
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void clock_disable_pllc()
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{
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// Disable PLLC and PLLC_OUT1.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
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usleep(10);
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}
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#define PLLC4_ENABLED (1 << 31)
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#define PLLC4_IN_USE (~PLLC4_ENABLED)
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u32 pllc4_enabled = 0;
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static void _clock_enable_pllc4(u32 mask)
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{
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pllc4_enabled |= mask;
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if (pllc4_enabled & PLLC4_ENABLED)
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return;
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// Enable Phase and Frequency lock detection.
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//CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET;
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// Disable PLL and IDDQ in case they are on.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLC4_BASE_IDDQ;
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usleep(10);
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// Set PLLC4 dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1.
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// Enable PLLC4 and wait for Phase and Frequency lock.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE;
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLCX_BASE_LOCK))
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;
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msleep(1); // Wait a bit for PLL to stabilize.
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pllc4_enabled |= PLLC4_ENABLED;
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}
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static void _clock_disable_pllc4(u32 mask)
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{
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pllc4_enabled &= ~mask;
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// Check if currently in use or disabled.
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if ((pllc4_enabled & PLLC4_IN_USE) || !(pllc4_enabled & PLLC4_ENABLED))
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return;
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// Disable PLLC4.
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msleep(1); // Wait at least 1ms to prevent glitching.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLC4_BASE_IDDQ;
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usleep(10);
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pllc4_enabled = 0;
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}
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#define L_SWR_SDMMC1_RST (1 << 14)
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#define L_SWR_SDMMC2_RST (1 << 9)
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#define L_SWR_SDMMC4_RST (1 << 15)
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#define U_SWR_SDMMC3_RST (1 << 5)
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#define L_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLK_ENB_SDMMC3 (1 << 5)
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#define L_SET_SDMMC1_RST (1 << 14)
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#define L_SET_SDMMC2_RST (1 << 9)
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#define L_SET_SDMMC4_RST (1 << 15)
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#define U_SET_SDMMC3_RST (1 << 5)
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#define L_CLR_SDMMC1_RST (1 << 14)
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#define L_CLR_SDMMC2_RST (1 << 9)
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#define L_CLR_SDMMC4_RST (1 << 15)
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#define U_CLR_SDMMC3_RST (1 << 5)
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#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
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#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
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#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
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#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
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#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
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#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
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#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
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#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
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static int _clock_sdmmc_is_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
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case SDMMC_2:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
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case SDMMC_3:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
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case SDMMC_4:
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return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
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}
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return 0;
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}
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static void _clock_sdmmc_set_reset(u32 id)
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{
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switch (id)
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{
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case SDMMC_1:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
|
|
break;
|
|
case SDMMC_2:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
|
|
break;
|
|
case SDMMC_3:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
|
|
break;
|
|
case SDMMC_4:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void _clock_sdmmc_clear_reset(u32 id)
|
|
{
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
|
|
break;
|
|
case SDMMC_2:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
|
|
break;
|
|
case SDMMC_3:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
|
|
break;
|
|
case SDMMC_4:
|
|
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int _clock_sdmmc_is_enabled(u32 id)
|
|
{
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
|
|
case SDMMC_2:
|
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
|
|
case SDMMC_3:
|
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
|
|
case SDMMC_4:
|
|
return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void _clock_sdmmc_set_enable(u32 id)
|
|
{
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
|
|
break;
|
|
case SDMMC_2:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
|
|
break;
|
|
case SDMMC_3:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
|
|
break;
|
|
case SDMMC_4:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void _clock_sdmmc_clear_enable(u32 id)
|
|
{
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
|
|
break;
|
|
case SDMMC_2:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
|
|
break;
|
|
case SDMMC_3:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
|
|
break;
|
|
case SDMMC_4:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void _clock_sdmmc_config_legacy_tm()
|
|
{
|
|
clock_t *clk = &_clock_sdmmc_legacy_tm;
|
|
if (!(CLOCK(clk->enable) & (1 << clk->index)))
|
|
clock_enable(clk);
|
|
}
|
|
|
|
typedef struct _clock_sdmmc_t
|
|
{
|
|
u32 clock;
|
|
u32 real_clock;
|
|
} clock_sdmmc_t;
|
|
|
|
static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
|
|
|
|
#define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0
|
|
#define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3
|
|
#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
|
|
|
|
static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
|
|
{
|
|
u32 divisor = 0;
|
|
u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
|
|
|
|
if (id > SDMMC_4)
|
|
return 0;
|
|
|
|
// Get IO clock divisor.
|
|
switch (val)
|
|
{
|
|
case 25000:
|
|
*pclock = 24728;
|
|
divisor = 31; // 16.5 div.
|
|
break;
|
|
case 26000:
|
|
*pclock = 25500;
|
|
divisor = 30; // 16 div.
|
|
break;
|
|
case 40800:
|
|
*pclock = 40800;
|
|
divisor = 18; // 10 div.
|
|
break;
|
|
case 50000:
|
|
*pclock = 48000;
|
|
divisor = 15; // 8.5 div.
|
|
break;
|
|
case 52000:
|
|
*pclock = 51000;
|
|
divisor = 14; // 8 div.
|
|
break;
|
|
case 100000:
|
|
source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
|
|
*pclock = 99840;
|
|
divisor = 2; // 2 div.
|
|
break;
|
|
case 164000:
|
|
*pclock = 163200;
|
|
divisor = 3; // 2.5 div.
|
|
break;
|
|
case 200000: // 240MHz evo+.
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
|
|
break;
|
|
case SDMMC_2:
|
|
source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
|
|
break;
|
|
case SDMMC_3:
|
|
source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
|
|
break;
|
|
case SDMMC_4:
|
|
source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
|
|
break;
|
|
}
|
|
*pclock = 199680;
|
|
divisor = 0; // 1 div.
|
|
break;
|
|
default:
|
|
*pclock = 24728;
|
|
divisor = 31; // 16.5 div.
|
|
}
|
|
|
|
_clock_sdmmc_table[id].clock = val;
|
|
_clock_sdmmc_table[id].real_clock = *pclock;
|
|
|
|
// Enable PLLC4 if in use by any SDMMC.
|
|
if (source)
|
|
_clock_enable_pllc4(1 << id);
|
|
|
|
// Set SDMMC legacy timeout clock.
|
|
_clock_sdmmc_config_legacy_tm();
|
|
|
|
// Set SDMMC clock.
|
|
switch (id)
|
|
{
|
|
case SDMMC_1:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor;
|
|
break;
|
|
case SDMMC_2:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor;
|
|
break;
|
|
case SDMMC_3:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor;
|
|
break;
|
|
case SDMMC_4:
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor;
|
|
break;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
|
|
{
|
|
if (_clock_sdmmc_table[id].clock == val)
|
|
{
|
|
*pclock = _clock_sdmmc_table[id].real_clock;
|
|
}
|
|
else
|
|
{
|
|
int is_enabled = _clock_sdmmc_is_enabled(id);
|
|
if (is_enabled)
|
|
_clock_sdmmc_clear_enable(id);
|
|
_clock_sdmmc_config_clock_host(pclock, id, val);
|
|
if (is_enabled)
|
|
_clock_sdmmc_set_enable(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
}
|
|
}
|
|
|
|
void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
|
|
{
|
|
// Get Card clock divisor.
|
|
switch (type)
|
|
{
|
|
case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
|
|
*pclock = 26000;
|
|
*pdivisor = 66;
|
|
break;
|
|
case SDHCI_TIMING_MMC_LS26:
|
|
*pclock = 26000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_MMC_HS52:
|
|
*pclock = 52000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_MMC_HS200:
|
|
case SDHCI_TIMING_MMC_HS400:
|
|
case SDHCI_TIMING_UHS_SDR104:
|
|
*pclock = 200000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
|
|
*pclock = 25000;
|
|
*pdivisor = 64;
|
|
break;
|
|
case SDHCI_TIMING_SD_DS12:
|
|
case SDHCI_TIMING_UHS_SDR12:
|
|
*pclock = 25000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_SD_HS25:
|
|
case SDHCI_TIMING_UHS_SDR25:
|
|
*pclock = 50000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_UHS_SDR50:
|
|
*pclock = 100000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_UHS_SDR82:
|
|
*pclock = 164000;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_UHS_DDR50:
|
|
*pclock = 40800;
|
|
*pdivisor = 1;
|
|
break;
|
|
case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
|
|
*pclock = 200000;
|
|
*pdivisor = 2;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int clock_sdmmc_is_not_reset_and_enabled(u32 id)
|
|
{
|
|
return !_clock_sdmmc_is_reset(id) && _clock_sdmmc_is_enabled(id);
|
|
}
|
|
|
|
void clock_sdmmc_enable(u32 id, u32 val)
|
|
{
|
|
u32 clock = 0;
|
|
|
|
if (_clock_sdmmc_is_enabled(id))
|
|
_clock_sdmmc_clear_enable(id);
|
|
_clock_sdmmc_set_reset(id);
|
|
_clock_sdmmc_config_clock_host(&clock, id, val);
|
|
_clock_sdmmc_set_enable(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
usleep((100000 + clock - 1) / clock);
|
|
_clock_sdmmc_clear_reset(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
}
|
|
|
|
void clock_sdmmc_disable(u32 id)
|
|
{
|
|
_clock_sdmmc_set_reset(id);
|
|
_clock_sdmmc_clear_enable(id);
|
|
_clock_sdmmc_is_reset(id);
|
|
_clock_disable_pllc4(1 << id);
|
|
}
|