Apply hekate 5.2.1 and gcc 10 changes, -fno-inline
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@@ -1,7 +1,7 @@
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/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -21,14 +21,24 @@
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#include "../utils/types.h"
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#define BPMP_MMU_MAINT_CLEAN_WAY 17
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#define BPMP_MMU_MAINT_INVALID_WAY 18
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#define BPMP_MMU_MAINT_CLN_INV_WAY 19
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typedef enum
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{
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BPMP_MMU_MAINT_NOP = 0,
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BPMP_MMU_MAINT_CLEAN_PHY = 1,
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BPMP_MMU_MAINT_INVALID_PHY = 2,
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BPMP_MMU_MAINT_CLEAN_INVALID_PHY = 3,
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BPMP_MMU_MAINT_CLEAN_LINE = 9,
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BPMP_MMU_MAINT_INVALID_LINE = 10,
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BPMP_MMU_MAINT_CLEAN_INVALID_LINE = 11,
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BPMP_MMU_MAINT_CLEAN_WAY = 17,
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BPMP_MMU_MAINT_INVALID_WAY = 18,
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BPMP_MMU_MAINT_CLN_INV_WAY = 19
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} bpmp_maintenance_t;
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typedef struct _bpmp_mmu_entry_t
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{
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u32 min_addr;
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u32 max_addr;
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u32 start_addr;
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u32 end_addr;
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u32 attr;
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u32 enable;
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} bpmp_mmu_entry_t;
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@@ -49,6 +59,7 @@ void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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void bpmp_clk_rate_get();
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void bpmp_clk_rate_set(bpmp_freq_t fid);
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void bpmp_usleep(u32 us);
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void bpmp_msleep(u32 ms);
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