336 lines
10 KiB
C++
336 lines
10 KiB
C++
// Copyright (c) 2012 Google Inc. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following disclaimer
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// in the documentation and/or other materials provided with the
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// distribution.
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// * Neither the name of Google Inc. nor the name Chromium Embedded
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// Framework nor the names of its contributors may be used to endorse
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// or promote products derived from this software without specific prior
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// written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Do not include this header file directly. Use base/cef_atomicops.h
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// instead.
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#ifndef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM64_GCC_H_
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#define CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM64_GCC_H_
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namespace base {
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namespace subtle {
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inline void MemoryBarrier() {
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__asm__ __volatile__ ("dmb ish" ::: "memory"); // NOLINT
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}
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// NoBarrier versions of the operation include "memory" in the clobber list.
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// This is not required for direct usage of the NoBarrier versions of the
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// operations. However this is required for correctness when they are used as
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// part of the Acquire or Release versions, to ensure that nothing from outside
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// the call is reordered between the operation and the memory barrier. This does
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// not change the code generated, so has no or minimal impact on the
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// NoBarrier operations.
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
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"cmp %w[prev], %w[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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"1: \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"IJr" (old_value),
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[new_value]"r" (new_value)
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: "cc", "memory"
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); // NOLINT
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return prev;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], %[ptr] \n\t" // Load the previous value.
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"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
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"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %w[result], %[ptr] \n\t" // Load the previous value.
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"add %w[result], %w[result], %w[increment]\n\t"
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"stxr %w[temp], %w[result], %[ptr] \n\t" // Try to store the result.
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"cbnz %w[temp], 0b \n\t" // Retry on failure.
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [increment]"IJr" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 result;
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MemoryBarrier();
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result = NoBarrier_AtomicIncrement(ptr, increment);
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MemoryBarrier();
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return result;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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MemoryBarrier();
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return prev;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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MemoryBarrier();
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prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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return prev;
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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__asm__ __volatile__ ( // NOLINT
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"stlr %w[value], %[ptr] \n\t"
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: [ptr]"=Q" (*ptr)
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: [value]"r" (value)
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: "memory"
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); // NOLINT
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value;
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__asm__ __volatile__ ( // NOLINT
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"ldar %w[value], %[ptr] \n\t"
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: [value]"=r" (value)
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: [ptr]"Q" (*ptr)
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: "memory"
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); // NOLINT
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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// 64-bit versions of the operations.
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// See the 32-bit versions for comments.
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[prev], %[ptr] \n\t"
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"cmp %[prev], %[old_value] \n\t"
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"bne 1f \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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"1: \n\t"
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: [prev]"=&r" (prev),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [old_value]"IJr" (old_value),
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[new_value]"r" (new_value)
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: "cc", "memory"
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); // NOLINT
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return prev;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], %[ptr] \n\t"
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"stxr %w[temp], %[new_value], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [new_value]"r" (new_value)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 result;
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int32_t temp;
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__asm__ __volatile__ ( // NOLINT
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"0: \n\t"
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"ldxr %[result], %[ptr] \n\t"
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"add %[result], %[result], %[increment] \n\t"
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"stxr %w[temp], %[result], %[ptr] \n\t"
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"cbnz %w[temp], 0b \n\t"
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: [result]"=&r" (result),
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[temp]"=&r" (temp),
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[ptr]"+Q" (*ptr)
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: [increment]"IJr" (increment)
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: "memory"
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); // NOLINT
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return result;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 result;
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MemoryBarrier();
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result = NoBarrier_AtomicIncrement(ptr, increment);
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MemoryBarrier();
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return result;
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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MemoryBarrier();
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return prev;
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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MemoryBarrier();
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prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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return prev;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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__asm__ __volatile__ ( // NOLINT
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"stlr %x[value], %[ptr] \n\t"
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: [ptr]"=Q" (*ptr)
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: [value]"r" (value)
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: "memory"
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); // NOLINT
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return *ptr;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value;
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__asm__ __volatile__ ( // NOLINT
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"ldar %x[value], %[ptr] \n\t"
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: [value]"=r" (value)
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: [ptr]"Q" (*ptr)
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: "memory"
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); // NOLINT
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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} } // namespace base::subtle
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#endif // CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM64_GCC_H_
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