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dc47bc006a
git-svn-id: https://chromiumembedded.googlecode.com/svn/branches/2272@1993 5089003a-bbd8-11dd-ad1f-f1f9622dbc98
225 lines
7.7 KiB
C++
225 lines
7.7 KiB
C++
// Copyright (c) 2008 Google Inc. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following disclaimer
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// in the documentation and/or other materials provided with the
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// distribution.
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// * Neither the name of Google Inc. nor the name Chromium Embedded
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// Framework nor the names of its contributors may be used to endorse
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// or promote products derived from this software without specific prior
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// written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Do not include this header file directly. Use base/cef_atomicops.h
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// instead.
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#ifndef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_
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#define CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_
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#include <windows.h>
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#include <intrin.h>
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#include "include/base/cef_macros.h"
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#if defined(ARCH_CPU_64_BITS)
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// windows.h #defines this (only on x64). This causes problems because the
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// public API also uses MemoryBarrier at the public name for this fence. So, on
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// X64, undef it, and call its documented
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// (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx)
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// implementation directly.
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#undef MemoryBarrier
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#endif
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namespace base {
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namespace subtle {
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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LONG result = _InterlockedCompareExchange(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(new_value),
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static_cast<LONG>(old_value));
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return static_cast<Atomic32>(result);
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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LONG result = _InterlockedExchange(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(new_value));
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return static_cast<Atomic32>(result);
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return _InterlockedExchangeAdd(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(increment)) + increment;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return Barrier_AtomicIncrement(ptr, increment);
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}
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#if !(defined(_MSC_VER) && _MSC_VER >= 1400)
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#error "We require at least vs2005 for MemoryBarrier"
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#endif
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inline void MemoryBarrier() {
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#if defined(ARCH_CPU_64_BITS)
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// See #undef and note at the top of this file.
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__faststorefence();
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#else
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// We use MemoryBarrier from WinNT.h
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::MemoryBarrier();
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#endif
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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NoBarrier_AtomicExchange(ptr, value);
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// acts as a barrier in this implementation
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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// See comments in Atomic64 version of Release_Store() below.
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr;
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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#if defined(_WIN64)
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// 64-bit low-level operations on 64-bit platform.
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COMPILE_ASSERT(sizeof(Atomic64) == sizeof(PVOID), atomic_word_is_atomic);
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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PVOID result = InterlockedCompareExchangePointer(
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reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value));
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return reinterpret_cast<Atomic64>(result);
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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PVOID result = InterlockedExchangePointer(
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reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value));
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return reinterpret_cast<Atomic64>(result);
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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return InterlockedExchangeAdd64(
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reinterpret_cast<volatile LONGLONG*>(ptr),
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static_cast<LONGLONG>(increment)) + increment;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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return Barrier_AtomicIncrement(ptr, increment);
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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NoBarrier_AtomicExchange(ptr, value);
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// acts as a barrier in this implementation
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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// When new chips come out, check:
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// IA-32 Intel Architecture Software Developer's Manual, Volume 3:
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// System Programming Guide, Chatper 7: Multiple-processor management,
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// Section 7.2, Memory Ordering.
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// Last seen at:
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// http://developer.intel.com/design/pentium4/manuals/index_new.htm
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return *ptr;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value = *ptr;
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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#endif // defined(_WIN64)
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} // namespace base::subtle
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} // namespace base
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#endif // CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_
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