mirror of
https://bitbucket.org/chromiumembedded/cef
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100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
// Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// This module gets enough CPU information to optimize the
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// atomicops module on x86.
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#include <stdint.h>
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#include <string.h>
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#include "include/base/cef_atomicops.h"
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// This file only makes sense with atomicops_internals_x86_gcc.h -- it
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// depends on structs that are defined in that file. If atomicops.h
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// doesn't sub-include that file, then we aren't needed, and shouldn't
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// try to do anything.
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#ifdef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_GCC_H_
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// Inline cpuid instruction. In PIC compilations, %ebx contains the address
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// of the global offset table. To avoid breaking such executables, this code
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// must preserve that register's value across cpuid instructions.
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#if defined(__i386__)
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#define cpuid(a, b, c, d, inp) \
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asm("mov %%ebx, %%edi\n" \
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"cpuid\n" \
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"xchg %%edi, %%ebx\n" \
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: "=a"(a), "=D"(b), "=c"(c), "=d"(d) \
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: "a"(inp))
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#elif defined(__x86_64__)
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#define cpuid(a, b, c, d, inp) \
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asm("mov %%rbx, %%rdi\n" \
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"cpuid\n" \
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"xchg %%rdi, %%rbx\n" \
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: "=a"(a), "=D"(b), "=c"(c), "=d"(d) \
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: "a"(inp))
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#endif
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#if defined(cpuid) // initialize the struct only on x86
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// Set the flags so that code will run correctly and conservatively, so even
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// if we haven't been initialized yet, we're probably single threaded, and our
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// default values should hopefully be pretty safe.
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struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
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false, // bug can't exist before process spawns multiple threads
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};
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namespace {
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// Initialize the AtomicOps_Internalx86CPUFeatures struct.
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void AtomicOps_Internalx86CPUFeaturesInit() {
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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// Get vendor string (issue CPUID with eax = 0)
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cpuid(eax, ebx, ecx, edx, 0);
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char vendor[13];
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memcpy(vendor, &ebx, 4);
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memcpy(vendor + 4, &edx, 4);
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memcpy(vendor + 8, &ecx, 4);
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vendor[12] = 0;
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// get feature flags in ecx/edx, and family/model in eax
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cpuid(eax, ebx, ecx, edx, 1);
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int family = (eax >> 8) & 0xf; // family and model fields
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int model = (eax >> 4) & 0xf;
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if (family == 0xf) { // use extended family and model fields
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family += (eax >> 20) & 0xff;
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model += ((eax >> 16) & 0xf) << 4;
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}
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// Opteron Rev E has a bug in which on very rare occasions a locked
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// instruction doesn't act as a read-acquire barrier if followed by a
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// non-locked read-modify-write instruction. Rev F has this bug in
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// pre-release versions, but not in versions released to customers,
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// so we test only for Rev E, which is family 15, model 32..63 inclusive.
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if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD
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family == 15 && 32 <= model && model <= 63) {
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AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
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} else {
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AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
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}
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}
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class AtomicOpsx86Initializer {
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public:
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AtomicOpsx86Initializer() { AtomicOps_Internalx86CPUFeaturesInit(); }
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};
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// A global to get use initialized on startup via static initialization :/
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AtomicOpsx86Initializer g_initer;
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} // namespace
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#endif // if x86
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#endif // ifdef CEF_INCLUDE_BASE_CEF_ATOMICOPS_INTERNALS_X86_GCC_H_
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