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Linux: Add ARM build support (issue #1990)
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Marshall Greenblatt
320
include/base/internal/cef_atomicops_arm_gcc.h
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320
include/base/internal/cef_atomicops_arm_gcc.h
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// Copyright (c) 2013 Google Inc. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following disclaimer
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// in the documentation and/or other materials provided with the
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// distribution.
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// * Neither the name of Google Inc. nor the name Chromium Embedded
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// Framework nor the names of its contributors may be used to endorse
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// or promote products derived from this software without specific prior
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// written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Do not include this header file directly. Use base/cef_atomicops.h
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// instead.
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//
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// LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.
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#ifndef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM_GCC_H_
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#define CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM_GCC_H_
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#if defined(OS_QNX)
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#include <sys/cpuinline.h>
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#endif
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namespace base {
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namespace subtle {
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// Memory barriers on ARM are funky, but the kernel is here to help:
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//
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// * ARMv5 didn't support SMP, there is no memory barrier instruction at
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// all on this architecture, or when targeting its machine code.
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//
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// * Some ARMv6 CPUs support SMP. A full memory barrier can be produced by
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// writing a random value to a very specific coprocessor register.
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//
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// * On ARMv7, the "dmb" instruction is used to perform a full memory
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// barrier (though writing to the co-processor will still work).
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// However, on single core devices (e.g. Nexus One, or Nexus S),
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// this instruction will take up to 200 ns, which is huge, even though
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// it's completely un-needed on these devices.
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//
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// * There is no easy way to determine at runtime if the device is
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// single or multi-core. However, the kernel provides a useful helper
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// function at a fixed memory address (0xffff0fa0), which will always
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// perform a memory barrier in the most efficient way. I.e. on single
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// core devices, this is an empty function that exits immediately.
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// On multi-core devices, it implements a full memory barrier.
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//
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// * This source could be compiled to ARMv5 machine code that runs on a
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// multi-core ARMv6 or ARMv7 device. In this case, memory barriers
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// are needed for correct execution. Always call the kernel helper, even
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// when targeting ARMv5TE.
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//
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inline void MemoryBarrier() {
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#if defined(OS_LINUX) || defined(OS_ANDROID)
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// Note: This is a function call, which is also an implicit compiler barrier.
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typedef void (*KernelMemoryBarrierFunc)();
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((KernelMemoryBarrierFunc)0xffff0fa0)();
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#elif defined(OS_QNX)
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__cpu_membarrier();
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#else
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#error MemoryBarrier() is not implemented on this platform.
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#endif
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}
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// An ARM toolchain would only define one of these depending on which
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// variant of the target architecture is being used. This tests against
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// any known ARMv6 or ARMv7 variant, where it is possible to directly
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// use ldrex/strex instructions to implement fast atomic operations.
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#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
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defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || \
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defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__)
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev_value;
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int reloop;
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do {
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// The following is equivalent to:
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//
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// prev_value = LDREX(ptr)
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// reloop = 0
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// if (prev_value != old_value)
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// reloop = STREX(ptr, new_value)
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__asm__ __volatile__(" ldrex %0, [%3]\n"
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" mov %1, #0\n"
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" cmp %0, %4\n"
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#ifdef __thumb2__
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" it eq\n"
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#endif
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" strexeq %1, %5, [%3]\n"
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: "=&r"(prev_value), "=&r"(reloop), "+m"(*ptr)
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: "r"(ptr), "r"(old_value), "r"(new_value)
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: "cc", "memory");
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} while (reloop != 0);
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return prev_value;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 result = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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MemoryBarrier();
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return result;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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MemoryBarrier();
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 value;
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int reloop;
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do {
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// Equivalent to:
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//
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// value = LDREX(ptr)
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// value += increment
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// reloop = STREX(ptr, value)
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//
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__asm__ __volatile__(" ldrex %0, [%3]\n"
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" add %0, %0, %4\n"
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" strex %1, %0, [%3]\n"
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: "=&r"(value), "=&r"(reloop), "+m"(*ptr)
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: "r"(ptr), "r"(increment)
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: "cc", "memory");
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} while (reloop);
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return value;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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// TODO(digit): Investigate if it's possible to implement this with
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// a single MemoryBarrier() operation between the LDREX and STREX.
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// See http://crbug.com/246514
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MemoryBarrier();
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Atomic32 result = NoBarrier_AtomicIncrement(ptr, increment);
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MemoryBarrier();
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return result;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 old_value;
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int reloop;
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do {
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// old_value = LDREX(ptr)
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// reloop = STREX(ptr, new_value)
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__asm__ __volatile__(" ldrex %0, [%3]\n"
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" strex %1, %4, [%3]\n"
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: "=&r"(old_value), "=&r"(reloop), "+m"(*ptr)
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: "r"(ptr), "r"(new_value)
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: "cc", "memory");
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} while (reloop != 0);
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return old_value;
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}
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// This tests against any known ARMv5 variant.
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#elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) || \
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defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
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// The kernel also provides a helper function to perform an atomic
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// compare-and-swap operation at the hard-wired address 0xffff0fc0.
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// On ARMv5, this is implemented by a special code path that the kernel
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// detects and treats specially when thread pre-emption happens.
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// On ARMv6 and higher, it uses LDREX/STREX instructions instead.
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//
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// Note that this always perform a full memory barrier, there is no
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// need to add calls MemoryBarrier() before or after it. It also
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// returns 0 on success, and 1 on exit.
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//
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// Available and reliable since Linux 2.6.24. Both Android and ChromeOS
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// use newer kernel revisions, so this should not be a concern.
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namespace {
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inline int LinuxKernelCmpxchg(Atomic32 old_value,
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Atomic32 new_value,
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volatile Atomic32* ptr) {
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typedef int (*KernelCmpxchgFunc)(Atomic32, Atomic32, volatile Atomic32*);
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return ((KernelCmpxchgFunc)0xffff0fc0)(old_value, new_value, ptr);
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}
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} // namespace
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev_value;
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for (;;) {
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prev_value = *ptr;
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if (prev_value != old_value)
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return prev_value;
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if (!LinuxKernelCmpxchg(old_value, new_value, ptr))
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return old_value;
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}
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 old_value;
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do {
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old_value = *ptr;
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} while (LinuxKernelCmpxchg(old_value, new_value, ptr));
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return old_value;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return Barrier_AtomicIncrement(ptr, increment);
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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for (;;) {
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// Atomic exchange the old value with an incremented one.
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Atomic32 old_value = *ptr;
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Atomic32 new_value = old_value + increment;
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if (!LinuxKernelCmpxchg(old_value, new_value, ptr)) {
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// The exchange took place as expected.
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return new_value;
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}
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// Otherwise, *ptr changed mid-loop and we need to retry.
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}
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev_value;
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for (;;) {
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prev_value = *ptr;
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if (prev_value != old_value) {
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// Always ensure acquire semantics.
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MemoryBarrier();
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return prev_value;
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}
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if (!LinuxKernelCmpxchg(old_value, new_value, ptr))
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return old_value;
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}
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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// This could be implemented as:
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// MemoryBarrier();
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// return NoBarrier_CompareAndSwap();
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//
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// But would use 3 barriers per succesful CAS. To save performance,
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// use Acquire_CompareAndSwap(). Its implementation guarantees that:
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// - A succesful swap uses only 2 barriers (in the kernel helper).
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// - An early return due to (prev_value != old_value) performs
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// a memory barrier with no store, which is equivalent to the
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// generic implementation above.
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return Acquire_CompareAndSwap(ptr, old_value, new_value);
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}
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#else
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# error "Your CPU's ARM architecture is not supported yet"
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#endif
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// NOTE: Atomicity of the following load and store operations is only
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// guaranteed in case of 32-bit alignement of |ptr| values.
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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MemoryBarrier();
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*ptr = value;
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) { return *ptr; }
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr;
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MemoryBarrier();
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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} // namespace base::subtle
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} // namespace base
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#endif // CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_ARM_GCC_H_
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