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https://bitbucket.org/chromiumembedded/cef
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Apply clang-format to all C, C++ and ObjC files (issue #2171)
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@ -55,25 +55,23 @@ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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LONG result = _InterlockedCompareExchange(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(new_value),
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reinterpret_cast<volatile LONG*>(ptr), static_cast<LONG>(new_value),
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static_cast<LONG>(old_value));
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return static_cast<Atomic32>(result);
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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LONG result = _InterlockedExchange(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(new_value));
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LONG result = _InterlockedExchange(reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(new_value));
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return static_cast<Atomic32>(result);
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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return _InterlockedExchangeAdd(
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reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(increment)) + increment;
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return _InterlockedExchangeAdd(reinterpret_cast<volatile LONG*>(ptr),
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static_cast<LONG>(increment)) +
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increment;
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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@ -112,11 +110,11 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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NoBarrier_AtomicExchange(ptr, value);
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// acts as a barrier in this implementation
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// acts as a barrier in this implementation
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}
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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// See comments in Atomic64 version of Release_Store() below.
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}
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@ -144,24 +142,24 @@ inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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PVOID result = InterlockedCompareExchangePointer(
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reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value));
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reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value));
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return reinterpret_cast<Atomic64>(result);
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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PVOID result = InterlockedExchangePointer(
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reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value));
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PVOID result =
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InterlockedExchangePointer(reinterpret_cast<volatile PVOID*>(ptr),
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reinterpret_cast<PVOID>(new_value));
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return reinterpret_cast<Atomic64>(result);
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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return InterlockedExchangeAdd64(
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reinterpret_cast<volatile LONGLONG*>(ptr),
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static_cast<LONGLONG>(increment)) + increment;
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return InterlockedExchangeAdd64(reinterpret_cast<volatile LONGLONG*>(ptr),
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static_cast<LONGLONG>(increment)) +
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increment;
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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@ -175,11 +173,11 @@ inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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NoBarrier_AtomicExchange(ptr, value);
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// acts as a barrier in this implementation
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// acts as a barrier in this implementation
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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*ptr = value; // works w/o barrier for current Intel chips as of June 2005
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// When new chips come out, check:
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// IA-32 Intel Architecture Software Developer's Manual, Volume 3:
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@ -215,7 +213,6 @@ inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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#endif // defined(_WIN64)
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} // namespace base::subtle
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