351 lines
8.5 KiB
Go
351 lines
8.5 KiB
Go
// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// This file encapsulates some of the odd characteristics of the ARM64
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// instruction set, to minimize its interaction with the core of the
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// assembler.
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package arch
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import (
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"github.com/twitchyliquid64/golang-asm/obj"
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"github.com/twitchyliquid64/golang-asm/obj/arm64"
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"errors"
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)
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var arm64LS = map[string]uint8{
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"P": arm64.C_XPOST,
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"W": arm64.C_XPRE,
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}
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var arm64Jump = map[string]bool{
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"B": true,
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"BL": true,
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"BEQ": true,
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"BNE": true,
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"BCS": true,
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"BHS": true,
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"BCC": true,
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"BLO": true,
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"BMI": true,
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"BPL": true,
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"BVS": true,
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"BVC": true,
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"BHI": true,
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"BLS": true,
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"BGE": true,
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"BLT": true,
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"BGT": true,
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"BLE": true,
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"CALL": true,
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"CBZ": true,
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"CBZW": true,
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"CBNZ": true,
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"CBNZW": true,
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"JMP": true,
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"TBNZ": true,
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"TBZ": true,
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}
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func jumpArm64(word string) bool {
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return arm64Jump[word]
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}
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// IsARM64CMP reports whether the op (as defined by an arm.A* constant) is
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// one of the comparison instructions that require special handling.
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func IsARM64CMP(op obj.As) bool {
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switch op {
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case arm64.ACMN, arm64.ACMP, arm64.ATST,
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arm64.ACMNW, arm64.ACMPW, arm64.ATSTW,
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arm64.AFCMPS, arm64.AFCMPD,
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arm64.AFCMPES, arm64.AFCMPED:
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return true
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}
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return false
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}
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// IsARM64STLXR reports whether the op (as defined by an arm64.A*
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// constant) is one of the STLXR-like instructions that require special
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// handling.
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func IsARM64STLXR(op obj.As) bool {
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switch op {
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case arm64.ASTLXRB, arm64.ASTLXRH, arm64.ASTLXRW, arm64.ASTLXR,
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arm64.ASTXRB, arm64.ASTXRH, arm64.ASTXRW, arm64.ASTXR,
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arm64.ASTXP, arm64.ASTXPW, arm64.ASTLXP, arm64.ASTLXPW:
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return true
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}
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// atomic instructions
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if arm64.IsAtomicInstruction(op) {
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return true
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}
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return false
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}
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// ARM64Suffix handles the special suffix for the ARM64.
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// It returns a boolean to indicate success; failure means
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// cond was unrecognized.
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func ARM64Suffix(prog *obj.Prog, cond string) bool {
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if cond == "" {
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return true
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}
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bits, ok := parseARM64Suffix(cond)
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if !ok {
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return false
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}
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prog.Scond = bits
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return true
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}
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// parseARM64Suffix parses the suffix attached to an ARM64 instruction.
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// The input is a single string consisting of period-separated condition
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// codes, such as ".P.W". An initial period is ignored.
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func parseARM64Suffix(cond string) (uint8, bool) {
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if cond == "" {
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return 0, true
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}
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return parseARMCondition(cond, arm64LS, nil)
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}
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func arm64RegisterNumber(name string, n int16) (int16, bool) {
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switch name {
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case "F":
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if 0 <= n && n <= 31 {
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return arm64.REG_F0 + n, true
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}
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case "R":
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if 0 <= n && n <= 30 { // not 31
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return arm64.REG_R0 + n, true
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}
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case "V":
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if 0 <= n && n <= 31 {
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return arm64.REG_V0 + n, true
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}
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}
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return 0, false
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}
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// IsARM64TBL reports whether the op (as defined by an arm64.A*
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// constant) is one of the table lookup instructions that require special
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// handling.
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func IsARM64TBL(op obj.As) bool {
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return op == arm64.AVTBL
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}
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// ARM64RegisterExtension parses an ARM64 register with extension or arrangement.
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func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
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Rnum := (reg & 31) + int16(num<<5)
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if isAmount {
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if num < 0 || num > 7 {
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return errors.New("index shift amount is out of range")
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}
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}
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switch ext {
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case "UXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTB + Rnum
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case "UXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTH + Rnum
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case "UXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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// effective address of memory is a base register value and an offset register value.
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_UXTW + Rnum
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} else {
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a.Reg = arm64.REG_UXTW + Rnum
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}
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case "UXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTX + Rnum
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case "SXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_SXTB + Rnum
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case "SXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_SXTH + Rnum
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case "SXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTW + Rnum
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} else {
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a.Reg = arm64.REG_SXTW + Rnum
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}
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case "SXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTX + Rnum
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} else {
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a.Reg = arm64.REG_SXTX + Rnum
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}
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case "LSL":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Index = arm64.REG_LSL + Rnum
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case "B8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
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case "B16":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
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case "H4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
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case "H8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
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case "S2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
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case "S4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
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case "D1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
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case "D2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
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case "Q1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
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case "B":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
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a.Index = num
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case "H":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
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a.Index = num
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case "S":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
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a.Index = num
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case "D":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
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a.Index = num
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default:
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return errors.New("unsupported register extension type: " + ext)
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}
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return nil
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}
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// ARM64RegisterArrangement parses an ARM64 vector register arrangement.
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func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
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var curQ, curSize uint16
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if name[0] != 'V' {
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return 0, errors.New("expect V0 through V31; found: " + name)
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}
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if reg < 0 {
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return 0, errors.New("invalid register number: " + name)
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}
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switch arng {
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case "B8":
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curSize = 0
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curQ = 0
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case "B16":
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curSize = 0
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curQ = 1
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case "H4":
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curSize = 1
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curQ = 0
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case "H8":
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curSize = 1
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curQ = 1
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case "S2":
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curSize = 2
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curQ = 0
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case "S4":
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curSize = 2
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curQ = 1
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case "D1":
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curSize = 3
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curQ = 0
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case "D2":
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curSize = 3
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curQ = 1
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default:
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return 0, errors.New("invalid arrangement in ARM64 register list")
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}
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return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
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}
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// ARM64RegisterListOffset generates offset encoding according to AArch64 specification.
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func ARM64RegisterListOffset(firstReg, regCnt int, arrangement int64) (int64, error) {
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offset := int64(firstReg)
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switch regCnt {
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case 1:
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offset |= 0x7 << 12
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case 2:
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offset |= 0xa << 12
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case 3:
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offset |= 0x6 << 12
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case 4:
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offset |= 0x2 << 12
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default:
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return 0, errors.New("invalid register numbers in ARM64 register list")
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}
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offset |= arrangement
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// arm64 uses the 60th bit to differentiate from other archs
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// For more details, refer to: obj/arm64/list7.go
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offset |= 1 << 60
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return offset, nil
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}
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