mirror of
https://github.com/superseriousbusiness/gotosocial
synced 2025-06-05 21:59:39 +02:00
[chore] Update gin to v1.9.0 (#1553)
This commit is contained in:
Daenney
GitHub
1033
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/a.out.go
generated
vendored
Normal file
1033
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/a.out.go
generated
vendored
Normal file
File diff suppressed because it is too large
Load Diff
512
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/anames.go
generated
vendored
Normal file
512
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/anames.go
generated
vendored
Normal file
@ -0,0 +1,512 @@
|
||||
// Code generated by stringer -i a.out.go -o anames.go -p arm64; DO NOT EDIT.
|
||||
|
||||
package arm64
|
||||
|
||||
import "github.com/twitchyliquid64/golang-asm/obj"
|
||||
|
||||
var Anames = []string{
|
||||
obj.A_ARCHSPECIFIC: "ADC",
|
||||
"ADCS",
|
||||
"ADCSW",
|
||||
"ADCW",
|
||||
"ADD",
|
||||
"ADDS",
|
||||
"ADDSW",
|
||||
"ADDW",
|
||||
"ADR",
|
||||
"ADRP",
|
||||
"AND",
|
||||
"ANDS",
|
||||
"ANDSW",
|
||||
"ANDW",
|
||||
"ASR",
|
||||
"ASRW",
|
||||
"AT",
|
||||
"BFI",
|
||||
"BFIW",
|
||||
"BFM",
|
||||
"BFMW",
|
||||
"BFXIL",
|
||||
"BFXILW",
|
||||
"BIC",
|
||||
"BICS",
|
||||
"BICSW",
|
||||
"BICW",
|
||||
"BRK",
|
||||
"CBNZ",
|
||||
"CBNZW",
|
||||
"CBZ",
|
||||
"CBZW",
|
||||
"CCMN",
|
||||
"CCMNW",
|
||||
"CCMP",
|
||||
"CCMPW",
|
||||
"CINC",
|
||||
"CINCW",
|
||||
"CINV",
|
||||
"CINVW",
|
||||
"CLREX",
|
||||
"CLS",
|
||||
"CLSW",
|
||||
"CLZ",
|
||||
"CLZW",
|
||||
"CMN",
|
||||
"CMNW",
|
||||
"CMP",
|
||||
"CMPW",
|
||||
"CNEG",
|
||||
"CNEGW",
|
||||
"CRC32B",
|
||||
"CRC32CB",
|
||||
"CRC32CH",
|
||||
"CRC32CW",
|
||||
"CRC32CX",
|
||||
"CRC32H",
|
||||
"CRC32W",
|
||||
"CRC32X",
|
||||
"CSEL",
|
||||
"CSELW",
|
||||
"CSET",
|
||||
"CSETM",
|
||||
"CSETMW",
|
||||
"CSETW",
|
||||
"CSINC",
|
||||
"CSINCW",
|
||||
"CSINV",
|
||||
"CSINVW",
|
||||
"CSNEG",
|
||||
"CSNEGW",
|
||||
"DC",
|
||||
"DCPS1",
|
||||
"DCPS2",
|
||||
"DCPS3",
|
||||
"DMB",
|
||||
"DRPS",
|
||||
"DSB",
|
||||
"EON",
|
||||
"EONW",
|
||||
"EOR",
|
||||
"EORW",
|
||||
"ERET",
|
||||
"EXTR",
|
||||
"EXTRW",
|
||||
"HINT",
|
||||
"HLT",
|
||||
"HVC",
|
||||
"IC",
|
||||
"ISB",
|
||||
"LDADDAB",
|
||||
"LDADDAD",
|
||||
"LDADDAH",
|
||||
"LDADDAW",
|
||||
"LDADDALB",
|
||||
"LDADDALD",
|
||||
"LDADDALH",
|
||||
"LDADDALW",
|
||||
"LDADDB",
|
||||
"LDADDD",
|
||||
"LDADDH",
|
||||
"LDADDW",
|
||||
"LDADDLB",
|
||||
"LDADDLD",
|
||||
"LDADDLH",
|
||||
"LDADDLW",
|
||||
"LDANDAB",
|
||||
"LDANDAD",
|
||||
"LDANDAH",
|
||||
"LDANDAW",
|
||||
"LDANDALB",
|
||||
"LDANDALD",
|
||||
"LDANDALH",
|
||||
"LDANDALW",
|
||||
"LDANDB",
|
||||
"LDANDD",
|
||||
"LDANDH",
|
||||
"LDANDW",
|
||||
"LDANDLB",
|
||||
"LDANDLD",
|
||||
"LDANDLH",
|
||||
"LDANDLW",
|
||||
"LDAR",
|
||||
"LDARB",
|
||||
"LDARH",
|
||||
"LDARW",
|
||||
"LDAXP",
|
||||
"LDAXPW",
|
||||
"LDAXR",
|
||||
"LDAXRB",
|
||||
"LDAXRH",
|
||||
"LDAXRW",
|
||||
"LDEORAB",
|
||||
"LDEORAD",
|
||||
"LDEORAH",
|
||||
"LDEORAW",
|
||||
"LDEORALB",
|
||||
"LDEORALD",
|
||||
"LDEORALH",
|
||||
"LDEORALW",
|
||||
"LDEORB",
|
||||
"LDEORD",
|
||||
"LDEORH",
|
||||
"LDEORW",
|
||||
"LDEORLB",
|
||||
"LDEORLD",
|
||||
"LDEORLH",
|
||||
"LDEORLW",
|
||||
"LDORAB",
|
||||
"LDORAD",
|
||||
"LDORAH",
|
||||
"LDORAW",
|
||||
"LDORALB",
|
||||
"LDORALD",
|
||||
"LDORALH",
|
||||
"LDORALW",
|
||||
"LDORB",
|
||||
"LDORD",
|
||||
"LDORH",
|
||||
"LDORW",
|
||||
"LDORLB",
|
||||
"LDORLD",
|
||||
"LDORLH",
|
||||
"LDORLW",
|
||||
"LDP",
|
||||
"LDPW",
|
||||
"LDPSW",
|
||||
"LDXR",
|
||||
"LDXRB",
|
||||
"LDXRH",
|
||||
"LDXRW",
|
||||
"LDXP",
|
||||
"LDXPW",
|
||||
"LSL",
|
||||
"LSLW",
|
||||
"LSR",
|
||||
"LSRW",
|
||||
"MADD",
|
||||
"MADDW",
|
||||
"MNEG",
|
||||
"MNEGW",
|
||||
"MOVK",
|
||||
"MOVKW",
|
||||
"MOVN",
|
||||
"MOVNW",
|
||||
"MOVZ",
|
||||
"MOVZW",
|
||||
"MRS",
|
||||
"MSR",
|
||||
"MSUB",
|
||||
"MSUBW",
|
||||
"MUL",
|
||||
"MULW",
|
||||
"MVN",
|
||||
"MVNW",
|
||||
"NEG",
|
||||
"NEGS",
|
||||
"NEGSW",
|
||||
"NEGW",
|
||||
"NGC",
|
||||
"NGCS",
|
||||
"NGCSW",
|
||||
"NGCW",
|
||||
"NOOP",
|
||||
"ORN",
|
||||
"ORNW",
|
||||
"ORR",
|
||||
"ORRW",
|
||||
"PRFM",
|
||||
"PRFUM",
|
||||
"RBIT",
|
||||
"RBITW",
|
||||
"REM",
|
||||
"REMW",
|
||||
"REV",
|
||||
"REV16",
|
||||
"REV16W",
|
||||
"REV32",
|
||||
"REVW",
|
||||
"ROR",
|
||||
"RORW",
|
||||
"SBC",
|
||||
"SBCS",
|
||||
"SBCSW",
|
||||
"SBCW",
|
||||
"SBFIZ",
|
||||
"SBFIZW",
|
||||
"SBFM",
|
||||
"SBFMW",
|
||||
"SBFX",
|
||||
"SBFXW",
|
||||
"SDIV",
|
||||
"SDIVW",
|
||||
"SEV",
|
||||
"SEVL",
|
||||
"SMADDL",
|
||||
"SMC",
|
||||
"SMNEGL",
|
||||
"SMSUBL",
|
||||
"SMULH",
|
||||
"SMULL",
|
||||
"STXR",
|
||||
"STXRB",
|
||||
"STXRH",
|
||||
"STXP",
|
||||
"STXPW",
|
||||
"STXRW",
|
||||
"STLP",
|
||||
"STLPW",
|
||||
"STLR",
|
||||
"STLRB",
|
||||
"STLRH",
|
||||
"STLRW",
|
||||
"STLXP",
|
||||
"STLXPW",
|
||||
"STLXR",
|
||||
"STLXRB",
|
||||
"STLXRH",
|
||||
"STLXRW",
|
||||
"STP",
|
||||
"STPW",
|
||||
"SUB",
|
||||
"SUBS",
|
||||
"SUBSW",
|
||||
"SUBW",
|
||||
"SVC",
|
||||
"SXTB",
|
||||
"SXTBW",
|
||||
"SXTH",
|
||||
"SXTHW",
|
||||
"SXTW",
|
||||
"SYS",
|
||||
"SYSL",
|
||||
"TBNZ",
|
||||
"TBZ",
|
||||
"TLBI",
|
||||
"TST",
|
||||
"TSTW",
|
||||
"UBFIZ",
|
||||
"UBFIZW",
|
||||
"UBFM",
|
||||
"UBFMW",
|
||||
"UBFX",
|
||||
"UBFXW",
|
||||
"UDIV",
|
||||
"UDIVW",
|
||||
"UMADDL",
|
||||
"UMNEGL",
|
||||
"UMSUBL",
|
||||
"UMULH",
|
||||
"UMULL",
|
||||
"UREM",
|
||||
"UREMW",
|
||||
"UXTB",
|
||||
"UXTH",
|
||||
"UXTW",
|
||||
"UXTBW",
|
||||
"UXTHW",
|
||||
"WFE",
|
||||
"WFI",
|
||||
"YIELD",
|
||||
"MOVB",
|
||||
"MOVBU",
|
||||
"MOVH",
|
||||
"MOVHU",
|
||||
"MOVW",
|
||||
"MOVWU",
|
||||
"MOVD",
|
||||
"MOVNP",
|
||||
"MOVNPW",
|
||||
"MOVP",
|
||||
"MOVPD",
|
||||
"MOVPQ",
|
||||
"MOVPS",
|
||||
"MOVPSW",
|
||||
"MOVPW",
|
||||
"SWPAD",
|
||||
"SWPAW",
|
||||
"SWPAH",
|
||||
"SWPAB",
|
||||
"SWPALD",
|
||||
"SWPALW",
|
||||
"SWPALH",
|
||||
"SWPALB",
|
||||
"SWPD",
|
||||
"SWPW",
|
||||
"SWPH",
|
||||
"SWPB",
|
||||
"SWPLD",
|
||||
"SWPLW",
|
||||
"SWPLH",
|
||||
"SWPLB",
|
||||
"BEQ",
|
||||
"BNE",
|
||||
"BCS",
|
||||
"BHS",
|
||||
"BCC",
|
||||
"BLO",
|
||||
"BMI",
|
||||
"BPL",
|
||||
"BVS",
|
||||
"BVC",
|
||||
"BHI",
|
||||
"BLS",
|
||||
"BGE",
|
||||
"BLT",
|
||||
"BGT",
|
||||
"BLE",
|
||||
"FABSD",
|
||||
"FABSS",
|
||||
"FADDD",
|
||||
"FADDS",
|
||||
"FCCMPD",
|
||||
"FCCMPED",
|
||||
"FCCMPS",
|
||||
"FCCMPES",
|
||||
"FCMPD",
|
||||
"FCMPED",
|
||||
"FCMPES",
|
||||
"FCMPS",
|
||||
"FCVTSD",
|
||||
"FCVTDS",
|
||||
"FCVTZSD",
|
||||
"FCVTZSDW",
|
||||
"FCVTZSS",
|
||||
"FCVTZSSW",
|
||||
"FCVTZUD",
|
||||
"FCVTZUDW",
|
||||
"FCVTZUS",
|
||||
"FCVTZUSW",
|
||||
"FDIVD",
|
||||
"FDIVS",
|
||||
"FLDPD",
|
||||
"FLDPS",
|
||||
"FMOVD",
|
||||
"FMOVS",
|
||||
"FMOVQ",
|
||||
"FMULD",
|
||||
"FMULS",
|
||||
"FNEGD",
|
||||
"FNEGS",
|
||||
"FSQRTD",
|
||||
"FSQRTS",
|
||||
"FSTPD",
|
||||
"FSTPS",
|
||||
"FSUBD",
|
||||
"FSUBS",
|
||||
"SCVTFD",
|
||||
"SCVTFS",
|
||||
"SCVTFWD",
|
||||
"SCVTFWS",
|
||||
"UCVTFD",
|
||||
"UCVTFS",
|
||||
"UCVTFWD",
|
||||
"UCVTFWS",
|
||||
"WORD",
|
||||
"DWORD",
|
||||
"FCSELS",
|
||||
"FCSELD",
|
||||
"FMAXS",
|
||||
"FMINS",
|
||||
"FMAXD",
|
||||
"FMIND",
|
||||
"FMAXNMS",
|
||||
"FMAXNMD",
|
||||
"FNMULS",
|
||||
"FNMULD",
|
||||
"FRINTNS",
|
||||
"FRINTND",
|
||||
"FRINTPS",
|
||||
"FRINTPD",
|
||||
"FRINTMS",
|
||||
"FRINTMD",
|
||||
"FRINTZS",
|
||||
"FRINTZD",
|
||||
"FRINTAS",
|
||||
"FRINTAD",
|
||||
"FRINTXS",
|
||||
"FRINTXD",
|
||||
"FRINTIS",
|
||||
"FRINTID",
|
||||
"FMADDS",
|
||||
"FMADDD",
|
||||
"FMSUBS",
|
||||
"FMSUBD",
|
||||
"FNMADDS",
|
||||
"FNMADDD",
|
||||
"FNMSUBS",
|
||||
"FNMSUBD",
|
||||
"FMINNMS",
|
||||
"FMINNMD",
|
||||
"FCVTDH",
|
||||
"FCVTHS",
|
||||
"FCVTHD",
|
||||
"FCVTSH",
|
||||
"AESD",
|
||||
"AESE",
|
||||
"AESIMC",
|
||||
"AESMC",
|
||||
"SHA1C",
|
||||
"SHA1H",
|
||||
"SHA1M",
|
||||
"SHA1P",
|
||||
"SHA1SU0",
|
||||
"SHA1SU1",
|
||||
"SHA256H",
|
||||
"SHA256H2",
|
||||
"SHA256SU0",
|
||||
"SHA256SU1",
|
||||
"SHA512H",
|
||||
"SHA512H2",
|
||||
"SHA512SU0",
|
||||
"SHA512SU1",
|
||||
"VADD",
|
||||
"VADDP",
|
||||
"VAND",
|
||||
"VBIF",
|
||||
"VCMEQ",
|
||||
"VCNT",
|
||||
"VEOR",
|
||||
"VMOV",
|
||||
"VLD1",
|
||||
"VLD2",
|
||||
"VLD3",
|
||||
"VLD4",
|
||||
"VLD1R",
|
||||
"VLD2R",
|
||||
"VLD3R",
|
||||
"VLD4R",
|
||||
"VORR",
|
||||
"VREV16",
|
||||
"VREV32",
|
||||
"VREV64",
|
||||
"VST1",
|
||||
"VST2",
|
||||
"VST3",
|
||||
"VST4",
|
||||
"VDUP",
|
||||
"VADDV",
|
||||
"VMOVI",
|
||||
"VUADDLV",
|
||||
"VSUB",
|
||||
"VFMLA",
|
||||
"VFMLS",
|
||||
"VPMULL",
|
||||
"VPMULL2",
|
||||
"VEXT",
|
||||
"VRBIT",
|
||||
"VUSHR",
|
||||
"VUSHLL",
|
||||
"VUSHLL2",
|
||||
"VUXTL",
|
||||
"VUXTL2",
|
||||
"VUZP1",
|
||||
"VUZP2",
|
||||
"VSHL",
|
||||
"VSRI",
|
||||
"VBSL",
|
||||
"VBIT",
|
||||
"VTBL",
|
||||
"VZIP1",
|
||||
"VZIP2",
|
||||
"VCMTST",
|
||||
"LAST",
|
||||
}
|
||||
100
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/anames7.go
generated
vendored
Normal file
100
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/anames7.go
generated
vendored
Normal file
@ -0,0 +1,100 @@
|
||||
// Copyright 2015 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package arm64
|
||||
|
||||
// This order should be strictly consistent to that in a.out.go
|
||||
var cnames7 = []string{
|
||||
"NONE",
|
||||
"REG",
|
||||
"RSP",
|
||||
"FREG",
|
||||
"VREG",
|
||||
"PAIR",
|
||||
"SHIFT",
|
||||
"EXTREG",
|
||||
"SPR",
|
||||
"COND",
|
||||
"ARNG",
|
||||
"ELEM",
|
||||
"LIST",
|
||||
"ZCON",
|
||||
"ABCON0",
|
||||
"ADDCON0",
|
||||
"ABCON",
|
||||
"AMCON",
|
||||
"ADDCON",
|
||||
"MBCON",
|
||||
"MOVCON",
|
||||
"BITCON",
|
||||
"ADDCON2",
|
||||
"LCON",
|
||||
"MOVCON2",
|
||||
"MOVCON3",
|
||||
"VCON",
|
||||
"FCON",
|
||||
"VCONADDR",
|
||||
"AACON",
|
||||
"AACON2",
|
||||
"LACON",
|
||||
"AECON",
|
||||
"SBRA",
|
||||
"LBRA",
|
||||
"ZAUTO",
|
||||
"NSAUTO_8",
|
||||
"NSAUTO_4",
|
||||
"NSAUTO",
|
||||
"NPAUTO",
|
||||
"NAUTO4K",
|
||||
"PSAUTO_8",
|
||||
"PSAUTO_4",
|
||||
"PSAUTO",
|
||||
"PPAUTO",
|
||||
"UAUTO4K_8",
|
||||
"UAUTO4K_4",
|
||||
"UAUTO4K_2",
|
||||
"UAUTO4K",
|
||||
"UAUTO8K_8",
|
||||
"UAUTO8K_4",
|
||||
"UAUTO8K",
|
||||
"UAUTO16K_8",
|
||||
"UAUTO16K",
|
||||
"UAUTO32K",
|
||||
"LAUTO",
|
||||
"SEXT1",
|
||||
"SEXT2",
|
||||
"SEXT4",
|
||||
"SEXT8",
|
||||
"SEXT16",
|
||||
"LEXT",
|
||||
"ZOREG",
|
||||
"NSOREG_8",
|
||||
"NSOREG_4",
|
||||
"NSOREG",
|
||||
"NPOREG",
|
||||
"NOREG4K",
|
||||
"PSOREG_8",
|
||||
"PSOREG_4",
|
||||
"PSOREG",
|
||||
"PPOREG",
|
||||
"UOREG4K_8",
|
||||
"UOREG4K_4",
|
||||
"UOREG4K_2",
|
||||
"UOREG4K",
|
||||
"UOREG8K_8",
|
||||
"UOREG8K_4",
|
||||
"UOREG8K",
|
||||
"UOREG16K_8",
|
||||
"UOREG16K",
|
||||
"UOREG32K",
|
||||
"LOREG",
|
||||
"ADDR",
|
||||
"GOTADDR",
|
||||
"TLS_LE",
|
||||
"TLS_IE",
|
||||
"ROFF",
|
||||
"GOK",
|
||||
"TEXTSIZE",
|
||||
"NCLASS",
|
||||
}
|
||||
7140
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/asm7.go
generated
vendored
Normal file
7140
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/asm7.go
generated
vendored
Normal file
File diff suppressed because it is too large
Load Diff
249
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/doc.go
generated
vendored
Normal file
249
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/doc.go
generated
vendored
Normal file
@ -0,0 +1,249 @@
|
||||
// Copyright 2018 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
/*
|
||||
Package arm64 implements an ARM64 assembler. Go assembly syntax is different from GNU ARM64
|
||||
syntax, but we can still follow the general rules to map between them.
|
||||
|
||||
Instructions mnemonics mapping rules
|
||||
|
||||
1. Most instructions use width suffixes of instruction names to indicate operand width rather than
|
||||
using different register names.
|
||||
|
||||
Examples:
|
||||
ADC R24, R14, R12 <=> adc x12, x24
|
||||
ADDW R26->24, R21, R15 <=> add w15, w21, w26, asr #24
|
||||
FCMPS F2, F3 <=> fcmp s3, s2
|
||||
FCMPD F2, F3 <=> fcmp d3, d2
|
||||
FCVTDH F2, F3 <=> fcvt h3, d2
|
||||
|
||||
2. Go uses .P and .W suffixes to indicate post-increment and pre-increment.
|
||||
|
||||
Examples:
|
||||
MOVD.P -8(R10), R8 <=> ldr x8, [x10],#-8
|
||||
MOVB.W 16(R16), R10 <=> ldrsb x10, [x16,#16]!
|
||||
MOVBU.W 16(R16), R10 <=> ldrb x10, [x16,#16]!
|
||||
|
||||
3. Go uses a series of MOV instructions as load and store.
|
||||
|
||||
64-bit variant ldr, str, stur => MOVD;
|
||||
32-bit variant str, stur, ldrsw => MOVW;
|
||||
32-bit variant ldr => MOVWU;
|
||||
ldrb => MOVBU; ldrh => MOVHU;
|
||||
ldrsb, sturb, strb => MOVB;
|
||||
ldrsh, sturh, strh => MOVH.
|
||||
|
||||
4. Go moves conditions into opcode suffix, like BLT.
|
||||
|
||||
5. Go adds a V prefix for most floating-point and SIMD instructions, except cryptographic extension
|
||||
instructions and floating-point(scalar) instructions.
|
||||
|
||||
Examples:
|
||||
VADD V5.H8, V18.H8, V9.H8 <=> add v9.8h, v18.8h, v5.8h
|
||||
VLD1.P (R6)(R11), [V31.D1] <=> ld1 {v31.1d}, [x6], x11
|
||||
VFMLA V29.S2, V20.S2, V14.S2 <=> fmla v14.2s, v20.2s, v29.2s
|
||||
AESD V22.B16, V19.B16 <=> aesd v19.16b, v22.16b
|
||||
SCVTFWS R3, F16 <=> scvtf s17, w6
|
||||
|
||||
6. Align directive
|
||||
|
||||
Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned
|
||||
to a specified boundary by padding with NOOP instruction. The alignment value supported on arm64
|
||||
must be a power of 2 and in the range of [8, 2048].
|
||||
|
||||
Examples:
|
||||
PCALIGN $16
|
||||
MOVD $2, R0 // This instruction is aligned with 16 bytes.
|
||||
PCALIGN $1024
|
||||
MOVD $3, R1 // This instruction is aligned with 1024 bytes.
|
||||
|
||||
PCALIGN also changes the function alignment. If a function has one or more PCALIGN directives,
|
||||
its address will be aligned to the same or coarser boundary, which is the maximum of all the
|
||||
alignment values.
|
||||
|
||||
In the following example, the function Add is aligned with 128 bytes.
|
||||
Examples:
|
||||
TEXT ·Add(SB),$40-16
|
||||
MOVD $2, R0
|
||||
PCALIGN $32
|
||||
MOVD $4, R1
|
||||
PCALIGN $128
|
||||
MOVD $8, R2
|
||||
RET
|
||||
|
||||
On arm64, functions in Go are aligned to 16 bytes by default, we can also use PCALGIN to set the
|
||||
function alignment. The functions that need to be aligned are preferably using NOFRAME and NOSPLIT
|
||||
to avoid the impact of the prologues inserted by the assembler, so that the function address will
|
||||
have the same alignment as the first hand-written instruction.
|
||||
|
||||
In the following example, PCALIGN at the entry of the function Add will align its address to 2048 bytes.
|
||||
|
||||
Examples:
|
||||
TEXT ·Add(SB),NOSPLIT|NOFRAME,$0
|
||||
PCALIGN $2048
|
||||
MOVD $1, R0
|
||||
MOVD $1, R1
|
||||
RET
|
||||
|
||||
Special Cases.
|
||||
|
||||
(1) umov is written as VMOV.
|
||||
|
||||
(2) br is renamed JMP, blr is renamed CALL.
|
||||
|
||||
(3) No need to add "W" suffix: LDARB, LDARH, LDAXRB, LDAXRH, LDTRH, LDXRB, LDXRH.
|
||||
|
||||
(4) In Go assembly syntax, NOP is a zero-width pseudo-instruction serves generic purpose, nothing
|
||||
related to real ARM64 instruction. NOOP serves for the hardware nop instruction. NOOP is an alias of
|
||||
HINT $0.
|
||||
|
||||
Examples:
|
||||
VMOV V13.B[1], R20 <=> mov x20, v13.b[1]
|
||||
VMOV V13.H[1], R20 <=> mov w20, v13.h[1]
|
||||
JMP (R3) <=> br x3
|
||||
CALL (R17) <=> blr x17
|
||||
LDAXRB (R19), R16 <=> ldaxrb w16, [x19]
|
||||
NOOP <=> nop
|
||||
|
||||
|
||||
Register mapping rules
|
||||
|
||||
1. All basic register names are written as Rn.
|
||||
|
||||
2. Go uses ZR as the zero register and RSP as the stack pointer.
|
||||
|
||||
3. Bn, Hn, Dn, Sn and Qn instructions are written as Fn in floating-point instructions and as Vn
|
||||
in SIMD instructions.
|
||||
|
||||
|
||||
Argument mapping rules
|
||||
|
||||
1. The operands appear in left-to-right assignment order.
|
||||
|
||||
Go reverses the arguments of most instructions.
|
||||
|
||||
Examples:
|
||||
ADD R11.SXTB<<1, RSP, R25 <=> add x25, sp, w11, sxtb #1
|
||||
VADD V16, V19, V14 <=> add d14, d19, d16
|
||||
|
||||
Special Cases.
|
||||
|
||||
(1) Argument order is the same as in the GNU ARM64 syntax: cbz, cbnz and some store instructions,
|
||||
such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1.
|
||||
|
||||
Examples:
|
||||
MOVD R29, 384(R19) <=> str x29, [x19,#384]
|
||||
MOVB.P R30, 30(R4) <=> strb w30, [x4],#30
|
||||
STLRH R21, (R19) <=> stlrh w21, [x19]
|
||||
|
||||
(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>
|
||||
|
||||
Examples:
|
||||
MADD R2, R30, R22, R6 <=> madd x6, x22, x2, x30
|
||||
SMSUBL R10, R3, R17, R27 <=> smsubl x27, w17, w10, x3
|
||||
|
||||
(3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>
|
||||
|
||||
Examples:
|
||||
FMADDD F30, F20, F3, F29 <=> fmadd d29, d3, d30, d20
|
||||
FNMSUBS F7, F25, F7, F22 <=> fnmsub s22, s7, s7, s25
|
||||
|
||||
(4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>
|
||||
|
||||
Examples:
|
||||
BFIW $16, R20, $6, R0 <=> bfi w0, w20, #16, #6
|
||||
UBFIZ $34, R26, $5, R20 <=> ubfiz x20, x26, #34, #5
|
||||
|
||||
(5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv>
|
||||
|
||||
Examples:
|
||||
FCCMPD AL, F8, F26, $0 <=> fccmp d26, d8, #0x0, al
|
||||
FCCMPS VS, F29, F4, $4 <=> fccmp s4, s29, #0x4, vs
|
||||
FCCMPED LE, F20, F5, $13 <=> fccmpe d5, d20, #0xd, le
|
||||
FCCMPES NE, F26, F10, $0 <=> fccmpe s10, s26, #0x0, ne
|
||||
|
||||
(6) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, $<imm>, $<nzcv>
|
||||
|
||||
Examples:
|
||||
CCMP MI, R22, $12, $13 <=> ccmp x22, #0xc, #0xd, mi
|
||||
CCMNW AL, R1, $11, $8 <=> ccmn w1, #0xb, #0x8, al
|
||||
|
||||
(7) CCMN, CCMNW, CCMP, CCMPW <cond>, <Rn>, <Rm>, $<nzcv>
|
||||
|
||||
Examples:
|
||||
CCMN VS, R13, R22, $10 <=> ccmn x13, x22, #0xa, vs
|
||||
CCMPW HS, R19, R14, $11 <=> ccmp w19, w14, #0xb, cs
|
||||
|
||||
(9) CSEL, CSELW, CSNEG, CSNEGW, CSINC, CSINCW <cond>, <Rn>, <Rm>, <Rd> ;
|
||||
FCSELD, FCSELS <cond>, <Fn>, <Fm>, <Fd>
|
||||
|
||||
Examples:
|
||||
CSEL GT, R0, R19, R1 <=> csel x1, x0, x19, gt
|
||||
CSNEGW GT, R7, R17, R8 <=> csneg w8, w7, w17, gt
|
||||
FCSELD EQ, F15, F18, F16 <=> fcsel d16, d15, d18, eq
|
||||
|
||||
(10) TBNZ, TBZ $<imm>, <Rt>, <label>
|
||||
|
||||
|
||||
(11) STLXR, STLXRW, STXR, STXRW, STLXRB, STLXRH, STXRB, STXRH <Rf>, (<Rn|RSP>), <Rs>
|
||||
|
||||
Examples:
|
||||
STLXR ZR, (R15), R16 <=> stlxr w16, xzr, [x15]
|
||||
STXRB R9, (R21), R19 <=> stxrb w19, w9, [x21]
|
||||
|
||||
(12) STLXP, STLXPW, STXP, STXPW (<Rf1>, <Rf2>), (<Rn|RSP>), <Rs>
|
||||
|
||||
Examples:
|
||||
STLXP (R17, R19), (R4), R5 <=> stlxp w5, x17, x19, [x4]
|
||||
STXPW (R30, R25), (R22), R13 <=> stxp w13, w30, w25, [x22]
|
||||
|
||||
2. Expressions for special arguments.
|
||||
|
||||
#<immediate> is written as $<immediate>.
|
||||
|
||||
Optionally-shifted immediate.
|
||||
|
||||
Examples:
|
||||
ADD $(3151<<12), R14, R20 <=> add x20, x14, #0xc4f, lsl #12
|
||||
ADDW $1864, R25, R6 <=> add w6, w25, #0x748
|
||||
|
||||
Optionally-shifted registers are written as <Rm>{<shift><amount>}.
|
||||
The <shift> can be <<(lsl), >>(lsr), ->(asr), @>(ror).
|
||||
|
||||
Examples:
|
||||
ADD R19>>30, R10, R24 <=> add x24, x10, x19, lsr #30
|
||||
ADDW R26->24, R21, R15 <=> add w15, w21, w26, asr #24
|
||||
|
||||
Extended registers are written as <Rm>{.<extend>{<<<amount>}}.
|
||||
<extend> can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX.
|
||||
|
||||
Examples:
|
||||
ADDS R19.UXTB<<4, R9, R26 <=> adds x26, x9, w19, uxtb #4
|
||||
ADDSW R14.SXTX, R14, R6 <=> adds w6, w14, w14, sxtx
|
||||
|
||||
Memory references: [<Xn|SP>{,#0}] is written as (Rn|RSP), a base register and an immediate
|
||||
offset is written as imm(Rn|RSP), a base register and an offset register is written as (Rn|RSP)(Rm).
|
||||
|
||||
Examples:
|
||||
LDAR (R22), R9 <=> ldar x9, [x22]
|
||||
LDP 28(R17), (R15, R23) <=> ldp x15, x23, [x17,#28]
|
||||
MOVWU (R4)(R12<<2), R8 <=> ldr w8, [x4, x12, lsl #2]
|
||||
MOVD (R7)(R11.UXTW<<3), R25 <=> ldr x25, [x7,w11,uxtw #3]
|
||||
MOVBU (R27)(R23), R14 <=> ldrb w14, [x27,x23]
|
||||
|
||||
Register pairs are written as (Rt1, Rt2).
|
||||
|
||||
Examples:
|
||||
LDP.P -240(R11), (R12, R26) <=> ldp x12, x26, [x11],#-240
|
||||
|
||||
Register with arrangement and register with arrangement and index.
|
||||
|
||||
Examples:
|
||||
VADD V5.H8, V18.H8, V9.H8 <=> add v9.8h, v18.8h, v5.8h
|
||||
VLD1 (R2), [V21.B16] <=> ld1 {v21.16b}, [x2]
|
||||
VST1.P V9.S[1], (R16)(R21) <=> st1 {v9.s}[1], [x16], x28
|
||||
VST1.P [V13.H8, V14.H8, V15.H8], (R3)(R14) <=> st1 {v13.8h-v15.8h}, [x3], x14
|
||||
VST1.P [V14.D1, V15.D1], (R7)(R23) <=> st1 {v14.1d, v15.1d}, [x7], x23
|
||||
*/
|
||||
package arm64
|
||||
288
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/list7.go
generated
vendored
Normal file
288
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/list7.go
generated
vendored
Normal file
@ -0,0 +1,288 @@
|
||||
// cmd/7l/list.c and cmd/7l/sub.c from Vita Nuova.
|
||||
// https://code.google.com/p/ken-cc/source/browse/
|
||||
//
|
||||
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
|
||||
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
|
||||
// Portions Copyright © 1997-1999 Vita Nuova Limited
|
||||
// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
|
||||
// Portions Copyright © 2004,2006 Bruce Ellis
|
||||
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
|
||||
// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
|
||||
// Portions Copyright © 2009 The Go Authors. All rights reserved.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
// of this software and associated documentation files (the "Software"), to deal
|
||||
// in the Software without restriction, including without limitation the rights
|
||||
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
// copies of the Software, and to permit persons to whom the Software is
|
||||
// furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in
|
||||
// all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
// THE SOFTWARE.
|
||||
|
||||
package arm64
|
||||
|
||||
import (
|
||||
"github.com/twitchyliquid64/golang-asm/obj"
|
||||
"fmt"
|
||||
)
|
||||
|
||||
var strcond = [16]string{
|
||||
"EQ",
|
||||
"NE",
|
||||
"HS",
|
||||
"LO",
|
||||
"MI",
|
||||
"PL",
|
||||
"VS",
|
||||
"VC",
|
||||
"HI",
|
||||
"LS",
|
||||
"GE",
|
||||
"LT",
|
||||
"GT",
|
||||
"LE",
|
||||
"AL",
|
||||
"NV",
|
||||
}
|
||||
|
||||
func init() {
|
||||
obj.RegisterRegister(obj.RBaseARM64, REG_SPECIAL+1024, rconv)
|
||||
obj.RegisterOpcode(obj.ABaseARM64, Anames)
|
||||
obj.RegisterRegisterList(obj.RegListARM64Lo, obj.RegListARM64Hi, rlconv)
|
||||
obj.RegisterOpSuffix("arm64", obj.CConvARM)
|
||||
}
|
||||
|
||||
func arrange(a int) string {
|
||||
switch a {
|
||||
case ARNG_8B:
|
||||
return "B8"
|
||||
case ARNG_16B:
|
||||
return "B16"
|
||||
case ARNG_4H:
|
||||
return "H4"
|
||||
case ARNG_8H:
|
||||
return "H8"
|
||||
case ARNG_2S:
|
||||
return "S2"
|
||||
case ARNG_4S:
|
||||
return "S4"
|
||||
case ARNG_1D:
|
||||
return "D1"
|
||||
case ARNG_2D:
|
||||
return "D2"
|
||||
case ARNG_B:
|
||||
return "B"
|
||||
case ARNG_H:
|
||||
return "H"
|
||||
case ARNG_S:
|
||||
return "S"
|
||||
case ARNG_D:
|
||||
return "D"
|
||||
case ARNG_1Q:
|
||||
return "Q1"
|
||||
default:
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
func rconv(r int) string {
|
||||
ext := (r >> 5) & 7
|
||||
if r == REGG {
|
||||
return "g"
|
||||
}
|
||||
switch {
|
||||
case REG_R0 <= r && r <= REG_R30:
|
||||
return fmt.Sprintf("R%d", r-REG_R0)
|
||||
case r == REG_R31:
|
||||
return "ZR"
|
||||
case REG_F0 <= r && r <= REG_F31:
|
||||
return fmt.Sprintf("F%d", r-REG_F0)
|
||||
case REG_V0 <= r && r <= REG_V31:
|
||||
return fmt.Sprintf("V%d", r-REG_V0)
|
||||
case COND_EQ <= r && r <= COND_NV:
|
||||
return strcond[r-COND_EQ]
|
||||
case r == REGSP:
|
||||
return "RSP"
|
||||
case r == REG_DAIFSet:
|
||||
return "DAIFSet"
|
||||
case r == REG_DAIFClr:
|
||||
return "DAIFClr"
|
||||
case r == REG_PLDL1KEEP:
|
||||
return "PLDL1KEEP"
|
||||
case r == REG_PLDL1STRM:
|
||||
return "PLDL1STRM"
|
||||
case r == REG_PLDL2KEEP:
|
||||
return "PLDL2KEEP"
|
||||
case r == REG_PLDL2STRM:
|
||||
return "PLDL2STRM"
|
||||
case r == REG_PLDL3KEEP:
|
||||
return "PLDL3KEEP"
|
||||
case r == REG_PLDL3STRM:
|
||||
return "PLDL3STRM"
|
||||
case r == REG_PLIL1KEEP:
|
||||
return "PLIL1KEEP"
|
||||
case r == REG_PLIL1STRM:
|
||||
return "PLIL1STRM"
|
||||
case r == REG_PLIL2KEEP:
|
||||
return "PLIL2KEEP"
|
||||
case r == REG_PLIL2STRM:
|
||||
return "PLIL2STRM"
|
||||
case r == REG_PLIL3KEEP:
|
||||
return "PLIL3KEEP"
|
||||
case r == REG_PLIL3STRM:
|
||||
return "PLIL3STRM"
|
||||
case r == REG_PSTL1KEEP:
|
||||
return "PSTL1KEEP"
|
||||
case r == REG_PSTL1STRM:
|
||||
return "PSTL1STRM"
|
||||
case r == REG_PSTL2KEEP:
|
||||
return "PSTL2KEEP"
|
||||
case r == REG_PSTL2STRM:
|
||||
return "PSTL2STRM"
|
||||
case r == REG_PSTL3KEEP:
|
||||
return "PSTL3KEEP"
|
||||
case r == REG_PSTL3STRM:
|
||||
return "PSTL3STRM"
|
||||
case REG_UXTB <= r && r < REG_UXTH:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.UXTB<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.UXTB", regname(r))
|
||||
}
|
||||
case REG_UXTH <= r && r < REG_UXTW:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.UXTH<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.UXTH", regname(r))
|
||||
}
|
||||
case REG_UXTW <= r && r < REG_UXTX:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.UXTW<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.UXTW", regname(r))
|
||||
}
|
||||
case REG_UXTX <= r && r < REG_SXTB:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.UXTX<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.UXTX", regname(r))
|
||||
}
|
||||
case REG_SXTB <= r && r < REG_SXTH:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.SXTB<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.SXTB", regname(r))
|
||||
}
|
||||
case REG_SXTH <= r && r < REG_SXTW:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.SXTH<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.SXTH", regname(r))
|
||||
}
|
||||
case REG_SXTW <= r && r < REG_SXTX:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.SXTW<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.SXTW", regname(r))
|
||||
}
|
||||
case REG_SXTX <= r && r < REG_SPECIAL:
|
||||
if ext != 0 {
|
||||
return fmt.Sprintf("%s.SXTX<<%d", regname(r), ext)
|
||||
} else {
|
||||
return fmt.Sprintf("%s.SXTX", regname(r))
|
||||
}
|
||||
// bits 0-4 indicate register, bits 5-7 indicate shift amount, bit 8 equals to 0.
|
||||
case REG_LSL <= r && r < (REG_LSL+1<<8):
|
||||
return fmt.Sprintf("R%d<<%d", r&31, (r>>5)&7)
|
||||
case REG_ARNG <= r && r < REG_ELEM:
|
||||
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
|
||||
case REG_ELEM <= r && r < REG_ELEM_END:
|
||||
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
|
||||
}
|
||||
// Return system register name.
|
||||
name, _, _ := SysRegEnc(int16(r))
|
||||
if name != "" {
|
||||
return name
|
||||
}
|
||||
return fmt.Sprintf("badreg(%d)", r)
|
||||
}
|
||||
|
||||
func DRconv(a int) string {
|
||||
if a >= C_NONE && a <= C_NCLASS {
|
||||
return cnames7[a]
|
||||
}
|
||||
return "C_??"
|
||||
}
|
||||
|
||||
func rlconv(list int64) string {
|
||||
str := ""
|
||||
|
||||
// ARM64 register list follows ARM64 instruction decode schema
|
||||
// | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... |
|
||||
// +----+----+-----+---------+---------+-----+
|
||||
// | | Q | ... | opcode | size | ... |
|
||||
|
||||
firstReg := int(list & 31)
|
||||
opcode := (list >> 12) & 15
|
||||
var regCnt int
|
||||
var t string
|
||||
switch opcode {
|
||||
case 0x7:
|
||||
regCnt = 1
|
||||
case 0xa:
|
||||
regCnt = 2
|
||||
case 0x6:
|
||||
regCnt = 3
|
||||
case 0x2:
|
||||
regCnt = 4
|
||||
default:
|
||||
regCnt = -1
|
||||
}
|
||||
// Q:size
|
||||
arng := ((list>>30)&1)<<2 | (list>>10)&3
|
||||
switch arng {
|
||||
case 0:
|
||||
t = "B8"
|
||||
case 4:
|
||||
t = "B16"
|
||||
case 1:
|
||||
t = "H4"
|
||||
case 5:
|
||||
t = "H8"
|
||||
case 2:
|
||||
t = "S2"
|
||||
case 6:
|
||||
t = "S4"
|
||||
case 3:
|
||||
t = "D1"
|
||||
case 7:
|
||||
t = "D2"
|
||||
}
|
||||
for i := 0; i < regCnt; i++ {
|
||||
if str == "" {
|
||||
str += "["
|
||||
} else {
|
||||
str += ","
|
||||
}
|
||||
str += fmt.Sprintf("V%d.", (firstReg+i)&31)
|
||||
str += t
|
||||
}
|
||||
str += "]"
|
||||
return str
|
||||
}
|
||||
|
||||
func regname(r int) string {
|
||||
if r&31 == 31 {
|
||||
return "ZR"
|
||||
}
|
||||
return fmt.Sprintf("R%d", r&31)
|
||||
}
|
||||
998
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/obj7.go
generated
vendored
Normal file
998
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/obj7.go
generated
vendored
Normal file
@ -0,0 +1,998 @@
|
||||
// cmd/7l/noop.c, cmd/7l/obj.c, cmd/ld/pass.c from Vita Nuova.
|
||||
// https://code.google.com/p/ken-cc/source/browse/
|
||||
//
|
||||
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
|
||||
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
|
||||
// Portions Copyright © 1997-1999 Vita Nuova Limited
|
||||
// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
|
||||
// Portions Copyright © 2004,2006 Bruce Ellis
|
||||
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
|
||||
// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
|
||||
// Portions Copyright © 2009 The Go Authors. All rights reserved.
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
// of this software and associated documentation files (the "Software"), to deal
|
||||
// in the Software without restriction, including without limitation the rights
|
||||
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
// copies of the Software, and to permit persons to whom the Software is
|
||||
// furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in
|
||||
// all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
// THE SOFTWARE.
|
||||
|
||||
package arm64
|
||||
|
||||
import (
|
||||
"github.com/twitchyliquid64/golang-asm/obj"
|
||||
"github.com/twitchyliquid64/golang-asm/objabi"
|
||||
"github.com/twitchyliquid64/golang-asm/src"
|
||||
"github.com/twitchyliquid64/golang-asm/sys"
|
||||
"math"
|
||||
)
|
||||
|
||||
var complements = []obj.As{
|
||||
AADD: ASUB,
|
||||
AADDW: ASUBW,
|
||||
ASUB: AADD,
|
||||
ASUBW: AADDW,
|
||||
ACMP: ACMN,
|
||||
ACMPW: ACMNW,
|
||||
ACMN: ACMP,
|
||||
ACMNW: ACMPW,
|
||||
}
|
||||
|
||||
func (c *ctxt7) stacksplit(p *obj.Prog, framesize int32) *obj.Prog {
|
||||
// MOV g_stackguard(g), R1
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = REGG
|
||||
p.From.Offset = 2 * int64(c.ctxt.Arch.PtrSize) // G.stackguard0
|
||||
if c.cursym.CFunc() {
|
||||
p.From.Offset = 3 * int64(c.ctxt.Arch.PtrSize) // G.stackguard1
|
||||
}
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R1
|
||||
|
||||
// Mark the stack bound check and morestack call async nonpreemptible.
|
||||
// If we get preempted here, when resumed the preemption request is
|
||||
// cleared, but we'll still call morestack, which will double the stack
|
||||
// unnecessarily. See issue #35470.
|
||||
p = c.ctxt.StartUnsafePoint(p, c.newprog)
|
||||
|
||||
q := (*obj.Prog)(nil)
|
||||
if framesize <= objabi.StackSmall {
|
||||
// small stack: SP < stackguard
|
||||
// MOV SP, R2
|
||||
// CMP stackguard, R2
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R2
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = ACMP
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REG_R1
|
||||
p.Reg = REG_R2
|
||||
} else if framesize <= objabi.StackBig {
|
||||
// large stack: SP-framesize < stackguard-StackSmall
|
||||
// SUB $(framesize-StackSmall), SP, R2
|
||||
// CMP stackguard, R2
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
|
||||
p.As = ASUB
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = int64(framesize) - objabi.StackSmall
|
||||
p.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R2
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = ACMP
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REG_R1
|
||||
p.Reg = REG_R2
|
||||
} else {
|
||||
// Such a large stack we need to protect against wraparound
|
||||
// if SP is close to zero.
|
||||
// SP-stackguard+StackGuard < framesize + (StackGuard-StackSmall)
|
||||
// The +StackGuard on both sides is required to keep the left side positive:
|
||||
// SP is allowed to be slightly below stackguard. See stack.h.
|
||||
// CMP $StackPreempt, R1
|
||||
// BEQ label_of_call_to_morestack
|
||||
// ADD $StackGuard, SP, R2
|
||||
// SUB R1, R2
|
||||
// MOV $(framesize+(StackGuard-StackSmall)), R3
|
||||
// CMP R3, R2
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
|
||||
p.As = ACMP
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = objabi.StackPreempt
|
||||
p.Reg = REG_R1
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
q = p
|
||||
p.As = ABEQ
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = AADD
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = int64(objabi.StackGuard)
|
||||
p.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R2
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = ASUB
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REG_R1
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R2
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = int64(framesize) + (int64(objabi.StackGuard) - objabi.StackSmall)
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REG_R3
|
||||
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = ACMP
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REG_R3
|
||||
p.Reg = REG_R2
|
||||
}
|
||||
|
||||
// BLS do-morestack
|
||||
bls := obj.Appendp(p, c.newprog)
|
||||
bls.As = ABLS
|
||||
bls.To.Type = obj.TYPE_BRANCH
|
||||
|
||||
end := c.ctxt.EndUnsafePoint(bls, c.newprog, -1)
|
||||
|
||||
var last *obj.Prog
|
||||
for last = c.cursym.Func.Text; last.Link != nil; last = last.Link {
|
||||
}
|
||||
|
||||
// Now we are at the end of the function, but logically
|
||||
// we are still in function prologue. We need to fix the
|
||||
// SP data and PCDATA.
|
||||
spfix := obj.Appendp(last, c.newprog)
|
||||
spfix.As = obj.ANOP
|
||||
spfix.Spadj = -framesize
|
||||
|
||||
pcdata := c.ctxt.EmitEntryStackMap(c.cursym, spfix, c.newprog)
|
||||
pcdata = c.ctxt.StartUnsafePoint(pcdata, c.newprog)
|
||||
|
||||
// MOV LR, R3
|
||||
movlr := obj.Appendp(pcdata, c.newprog)
|
||||
movlr.As = AMOVD
|
||||
movlr.From.Type = obj.TYPE_REG
|
||||
movlr.From.Reg = REGLINK
|
||||
movlr.To.Type = obj.TYPE_REG
|
||||
movlr.To.Reg = REG_R3
|
||||
if q != nil {
|
||||
q.To.SetTarget(movlr)
|
||||
}
|
||||
bls.To.SetTarget(movlr)
|
||||
|
||||
debug := movlr
|
||||
if false {
|
||||
debug = obj.Appendp(debug, c.newprog)
|
||||
debug.As = AMOVD
|
||||
debug.From.Type = obj.TYPE_CONST
|
||||
debug.From.Offset = int64(framesize)
|
||||
debug.To.Type = obj.TYPE_REG
|
||||
debug.To.Reg = REGTMP
|
||||
}
|
||||
|
||||
// BL runtime.morestack(SB)
|
||||
call := obj.Appendp(debug, c.newprog)
|
||||
call.As = ABL
|
||||
call.To.Type = obj.TYPE_BRANCH
|
||||
morestack := "runtime.morestack"
|
||||
switch {
|
||||
case c.cursym.CFunc():
|
||||
morestack = "runtime.morestackc"
|
||||
case !c.cursym.Func.Text.From.Sym.NeedCtxt():
|
||||
morestack = "runtime.morestack_noctxt"
|
||||
}
|
||||
call.To.Sym = c.ctxt.Lookup(morestack)
|
||||
|
||||
pcdata = c.ctxt.EndUnsafePoint(call, c.newprog, -1)
|
||||
|
||||
// B start
|
||||
jmp := obj.Appendp(pcdata, c.newprog)
|
||||
jmp.As = AB
|
||||
jmp.To.Type = obj.TYPE_BRANCH
|
||||
jmp.To.SetTarget(c.cursym.Func.Text.Link)
|
||||
jmp.Spadj = +framesize
|
||||
|
||||
return end
|
||||
}
|
||||
|
||||
func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
|
||||
c := ctxt7{ctxt: ctxt, newprog: newprog}
|
||||
|
||||
p.From.Class = 0
|
||||
p.To.Class = 0
|
||||
|
||||
// $0 results in C_ZCON, which matches both C_REG and various
|
||||
// C_xCON, however the C_REG cases in asmout don't expect a
|
||||
// constant, so they will use the register fields and assemble
|
||||
// a R0. To prevent that, rewrite $0 as ZR.
|
||||
if p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REGZERO
|
||||
}
|
||||
if p.To.Type == obj.TYPE_CONST && p.To.Offset == 0 {
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGZERO
|
||||
}
|
||||
|
||||
// Rewrite BR/BL to symbol as TYPE_BRANCH.
|
||||
switch p.As {
|
||||
case AB,
|
||||
ABL,
|
||||
obj.ARET,
|
||||
obj.ADUFFZERO,
|
||||
obj.ADUFFCOPY:
|
||||
if p.To.Sym != nil {
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
}
|
||||
break
|
||||
}
|
||||
|
||||
// Rewrite float constants to values stored in memory.
|
||||
switch p.As {
|
||||
case AFMOVS:
|
||||
if p.From.Type == obj.TYPE_FCONST {
|
||||
f64 := p.From.Val.(float64)
|
||||
f32 := float32(f64)
|
||||
if c.chipfloat7(f64) > 0 {
|
||||
break
|
||||
}
|
||||
if math.Float32bits(f32) == 0 {
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REGZERO
|
||||
break
|
||||
}
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Sym = c.ctxt.Float32Sym(f32)
|
||||
p.From.Name = obj.NAME_EXTERN
|
||||
p.From.Offset = 0
|
||||
}
|
||||
|
||||
case AFMOVD:
|
||||
if p.From.Type == obj.TYPE_FCONST {
|
||||
f64 := p.From.Val.(float64)
|
||||
if c.chipfloat7(f64) > 0 {
|
||||
break
|
||||
}
|
||||
if math.Float64bits(f64) == 0 {
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REGZERO
|
||||
break
|
||||
}
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Sym = c.ctxt.Float64Sym(f64)
|
||||
p.From.Name = obj.NAME_EXTERN
|
||||
p.From.Offset = 0
|
||||
}
|
||||
|
||||
break
|
||||
}
|
||||
|
||||
// Rewrite negative immediates as positive immediates with
|
||||
// complementary instruction.
|
||||
switch p.As {
|
||||
case AADD, ASUB, ACMP, ACMN:
|
||||
if p.From.Type == obj.TYPE_CONST && p.From.Offset < 0 && p.From.Offset != -1<<63 {
|
||||
p.From.Offset = -p.From.Offset
|
||||
p.As = complements[p.As]
|
||||
}
|
||||
case AADDW, ASUBW, ACMPW, ACMNW:
|
||||
if p.From.Type == obj.TYPE_CONST && p.From.Offset < 0 && int32(p.From.Offset) != -1<<31 {
|
||||
p.From.Offset = -p.From.Offset
|
||||
p.As = complements[p.As]
|
||||
}
|
||||
}
|
||||
|
||||
// For 32-bit logical instruction with constant,
|
||||
// rewrite the high 32-bit to be a repetition of
|
||||
// the low 32-bit, so that the BITCON test can be
|
||||
// shared for both 32-bit and 64-bit. 32-bit ops
|
||||
// will zero the high 32-bit of the destination
|
||||
// register anyway.
|
||||
if isANDWop(p.As) && p.From.Type == obj.TYPE_CONST {
|
||||
v := p.From.Offset & 0xffffffff
|
||||
p.From.Offset = v | v<<32
|
||||
}
|
||||
|
||||
if c.ctxt.Flag_dynlink {
|
||||
c.rewriteToUseGot(p)
|
||||
}
|
||||
}
|
||||
|
||||
// Rewrite p, if necessary, to access global data via the global offset table.
|
||||
func (c *ctxt7) rewriteToUseGot(p *obj.Prog) {
|
||||
if p.As == obj.ADUFFCOPY || p.As == obj.ADUFFZERO {
|
||||
// ADUFFxxx $offset
|
||||
// becomes
|
||||
// MOVD runtime.duffxxx@GOT, REGTMP
|
||||
// ADD $offset, REGTMP
|
||||
// CALL REGTMP
|
||||
var sym *obj.LSym
|
||||
if p.As == obj.ADUFFZERO {
|
||||
sym = c.ctxt.Lookup("runtime.duffzero")
|
||||
} else {
|
||||
sym = c.ctxt.Lookup("runtime.duffcopy")
|
||||
}
|
||||
offset := p.To.Offset
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Name = obj.NAME_GOTREF
|
||||
p.From.Sym = sym
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGTMP
|
||||
p.To.Name = obj.NAME_NONE
|
||||
p.To.Offset = 0
|
||||
p.To.Sym = nil
|
||||
p1 := obj.Appendp(p, c.newprog)
|
||||
p1.As = AADD
|
||||
p1.From.Type = obj.TYPE_CONST
|
||||
p1.From.Offset = offset
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = REGTMP
|
||||
p2 := obj.Appendp(p1, c.newprog)
|
||||
p2.As = obj.ACALL
|
||||
p2.To.Type = obj.TYPE_REG
|
||||
p2.To.Reg = REGTMP
|
||||
}
|
||||
|
||||
// We only care about global data: NAME_EXTERN means a global
|
||||
// symbol in the Go sense, and p.Sym.Local is true for a few
|
||||
// internally defined symbols.
|
||||
if p.From.Type == obj.TYPE_ADDR && p.From.Name == obj.NAME_EXTERN && !p.From.Sym.Local() {
|
||||
// MOVD $sym, Rx becomes MOVD sym@GOT, Rx
|
||||
// MOVD $sym+<off>, Rx becomes MOVD sym@GOT, Rx; ADD <off>, Rx
|
||||
if p.As != AMOVD {
|
||||
c.ctxt.Diag("do not know how to handle TYPE_ADDR in %v with -dynlink", p)
|
||||
}
|
||||
if p.To.Type != obj.TYPE_REG {
|
||||
c.ctxt.Diag("do not know how to handle LEAQ-type insn to non-register in %v with -dynlink", p)
|
||||
}
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Name = obj.NAME_GOTREF
|
||||
if p.From.Offset != 0 {
|
||||
q := obj.Appendp(p, c.newprog)
|
||||
q.As = AADD
|
||||
q.From.Type = obj.TYPE_CONST
|
||||
q.From.Offset = p.From.Offset
|
||||
q.To = p.To
|
||||
p.From.Offset = 0
|
||||
}
|
||||
}
|
||||
if p.GetFrom3() != nil && p.GetFrom3().Name == obj.NAME_EXTERN {
|
||||
c.ctxt.Diag("don't know how to handle %v with -dynlink", p)
|
||||
}
|
||||
var source *obj.Addr
|
||||
// MOVx sym, Ry becomes MOVD sym@GOT, REGTMP; MOVx (REGTMP), Ry
|
||||
// MOVx Ry, sym becomes MOVD sym@GOT, REGTMP; MOVD Ry, (REGTMP)
|
||||
// An addition may be inserted between the two MOVs if there is an offset.
|
||||
if p.From.Name == obj.NAME_EXTERN && !p.From.Sym.Local() {
|
||||
if p.To.Name == obj.NAME_EXTERN && !p.To.Sym.Local() {
|
||||
c.ctxt.Diag("cannot handle NAME_EXTERN on both sides in %v with -dynlink", p)
|
||||
}
|
||||
source = &p.From
|
||||
} else if p.To.Name == obj.NAME_EXTERN && !p.To.Sym.Local() {
|
||||
source = &p.To
|
||||
} else {
|
||||
return
|
||||
}
|
||||
if p.As == obj.ATEXT || p.As == obj.AFUNCDATA || p.As == obj.ACALL || p.As == obj.ARET || p.As == obj.AJMP {
|
||||
return
|
||||
}
|
||||
if source.Sym.Type == objabi.STLSBSS {
|
||||
return
|
||||
}
|
||||
if source.Type != obj.TYPE_MEM {
|
||||
c.ctxt.Diag("don't know how to handle %v with -dynlink", p)
|
||||
}
|
||||
p1 := obj.Appendp(p, c.newprog)
|
||||
p2 := obj.Appendp(p1, c.newprog)
|
||||
p1.As = AMOVD
|
||||
p1.From.Type = obj.TYPE_MEM
|
||||
p1.From.Sym = source.Sym
|
||||
p1.From.Name = obj.NAME_GOTREF
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = REGTMP
|
||||
|
||||
p2.As = p.As
|
||||
p2.From = p.From
|
||||
p2.To = p.To
|
||||
if p.From.Name == obj.NAME_EXTERN {
|
||||
p2.From.Reg = REGTMP
|
||||
p2.From.Name = obj.NAME_NONE
|
||||
p2.From.Sym = nil
|
||||
} else if p.To.Name == obj.NAME_EXTERN {
|
||||
p2.To.Reg = REGTMP
|
||||
p2.To.Name = obj.NAME_NONE
|
||||
p2.To.Sym = nil
|
||||
} else {
|
||||
return
|
||||
}
|
||||
obj.Nopout(p)
|
||||
}
|
||||
|
||||
func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
|
||||
if cursym.Func.Text == nil || cursym.Func.Text.Link == nil {
|
||||
return
|
||||
}
|
||||
|
||||
c := ctxt7{ctxt: ctxt, newprog: newprog, cursym: cursym}
|
||||
|
||||
p := c.cursym.Func.Text
|
||||
textstksiz := p.To.Offset
|
||||
if textstksiz == -8 {
|
||||
// Historical way to mark NOFRAME.
|
||||
p.From.Sym.Set(obj.AttrNoFrame, true)
|
||||
textstksiz = 0
|
||||
}
|
||||
if textstksiz < 0 {
|
||||
c.ctxt.Diag("negative frame size %d - did you mean NOFRAME?", textstksiz)
|
||||
}
|
||||
if p.From.Sym.NoFrame() {
|
||||
if textstksiz != 0 {
|
||||
c.ctxt.Diag("NOFRAME functions must have a frame size of 0, not %d", textstksiz)
|
||||
}
|
||||
}
|
||||
|
||||
c.cursym.Func.Args = p.To.Val.(int32)
|
||||
c.cursym.Func.Locals = int32(textstksiz)
|
||||
|
||||
/*
|
||||
* find leaf subroutines
|
||||
*/
|
||||
for p := c.cursym.Func.Text; p != nil; p = p.Link {
|
||||
switch p.As {
|
||||
case obj.ATEXT:
|
||||
p.Mark |= LEAF
|
||||
|
||||
case ABL,
|
||||
obj.ADUFFZERO,
|
||||
obj.ADUFFCOPY:
|
||||
c.cursym.Func.Text.Mark &^= LEAF
|
||||
}
|
||||
}
|
||||
|
||||
var q *obj.Prog
|
||||
var q1 *obj.Prog
|
||||
var retjmp *obj.LSym
|
||||
for p := c.cursym.Func.Text; p != nil; p = p.Link {
|
||||
o := p.As
|
||||
switch o {
|
||||
case obj.ATEXT:
|
||||
c.cursym.Func.Text = p
|
||||
c.autosize = int32(textstksiz)
|
||||
|
||||
if p.Mark&LEAF != 0 && c.autosize == 0 {
|
||||
// A leaf function with no locals has no frame.
|
||||
p.From.Sym.Set(obj.AttrNoFrame, true)
|
||||
}
|
||||
|
||||
if !p.From.Sym.NoFrame() {
|
||||
// If there is a stack frame at all, it includes
|
||||
// space to save the LR.
|
||||
c.autosize += 8
|
||||
}
|
||||
|
||||
if c.autosize != 0 {
|
||||
extrasize := int32(0)
|
||||
if c.autosize%16 == 8 {
|
||||
// Allocate extra 8 bytes on the frame top to save FP
|
||||
extrasize = 8
|
||||
} else if c.autosize&(16-1) == 0 {
|
||||
// Allocate extra 16 bytes to save FP for the old frame whose size is 8 mod 16
|
||||
extrasize = 16
|
||||
} else {
|
||||
c.ctxt.Diag("%v: unaligned frame size %d - must be 16 aligned", p, c.autosize-8)
|
||||
}
|
||||
c.autosize += extrasize
|
||||
c.cursym.Func.Locals += extrasize
|
||||
|
||||
// low 32 bits for autosize
|
||||
// high 32 bits for extrasize
|
||||
p.To.Offset = int64(c.autosize) | int64(extrasize)<<32
|
||||
} else {
|
||||
// NOFRAME
|
||||
p.To.Offset = 0
|
||||
}
|
||||
|
||||
if c.autosize == 0 && c.cursym.Func.Text.Mark&LEAF == 0 {
|
||||
if c.ctxt.Debugvlog {
|
||||
c.ctxt.Logf("save suppressed in: %s\n", c.cursym.Func.Text.From.Sym.Name)
|
||||
}
|
||||
c.cursym.Func.Text.Mark |= LEAF
|
||||
}
|
||||
|
||||
if cursym.Func.Text.Mark&LEAF != 0 {
|
||||
cursym.Set(obj.AttrLeaf, true)
|
||||
if p.From.Sym.NoFrame() {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
if !p.From.Sym.NoSplit() {
|
||||
p = c.stacksplit(p, c.autosize) // emit split check
|
||||
}
|
||||
|
||||
var prologueEnd *obj.Prog
|
||||
|
||||
aoffset := c.autosize
|
||||
if aoffset > 0xF0 {
|
||||
aoffset = 0xF0
|
||||
}
|
||||
|
||||
// Frame is non-empty. Make sure to save link register, even if
|
||||
// it is a leaf function, so that traceback works.
|
||||
q = p
|
||||
if c.autosize > aoffset {
|
||||
// Frame size is too large for a MOVD.W instruction.
|
||||
// Store link register before decrementing SP, so if a signal comes
|
||||
// during the execution of the function prologue, the traceback
|
||||
// code will not see a half-updated stack frame.
|
||||
// This sequence is not async preemptible, as if we open a frame
|
||||
// at the current SP, it will clobber the saved LR.
|
||||
q = c.ctxt.StartUnsafePoint(q, c.newprog)
|
||||
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.Pos = p.Pos
|
||||
q.As = ASUB
|
||||
q.From.Type = obj.TYPE_CONST
|
||||
q.From.Offset = int64(c.autosize)
|
||||
q.Reg = REGSP
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REGTMP
|
||||
|
||||
prologueEnd = q
|
||||
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.Pos = p.Pos
|
||||
q.As = AMOVD
|
||||
q.From.Type = obj.TYPE_REG
|
||||
q.From.Reg = REGLINK
|
||||
q.To.Type = obj.TYPE_MEM
|
||||
q.To.Reg = REGTMP
|
||||
|
||||
q1 = obj.Appendp(q, c.newprog)
|
||||
q1.Pos = p.Pos
|
||||
q1.As = AMOVD
|
||||
q1.From.Type = obj.TYPE_REG
|
||||
q1.From.Reg = REGTMP
|
||||
q1.To.Type = obj.TYPE_REG
|
||||
q1.To.Reg = REGSP
|
||||
q1.Spadj = c.autosize
|
||||
|
||||
if c.ctxt.Headtype == objabi.Hdarwin {
|
||||
// iOS does not support SA_ONSTACK. We will run the signal handler
|
||||
// on the G stack. If we write below SP, it may be clobbered by
|
||||
// the signal handler. So we save LR after decrementing SP.
|
||||
q1 = obj.Appendp(q1, c.newprog)
|
||||
q1.Pos = p.Pos
|
||||
q1.As = AMOVD
|
||||
q1.From.Type = obj.TYPE_REG
|
||||
q1.From.Reg = REGLINK
|
||||
q1.To.Type = obj.TYPE_MEM
|
||||
q1.To.Reg = REGSP
|
||||
}
|
||||
|
||||
q1 = c.ctxt.EndUnsafePoint(q1, c.newprog, -1)
|
||||
} else {
|
||||
// small frame, update SP and save LR in a single MOVD.W instruction
|
||||
q1 = obj.Appendp(q, c.newprog)
|
||||
q1.As = AMOVD
|
||||
q1.Pos = p.Pos
|
||||
q1.From.Type = obj.TYPE_REG
|
||||
q1.From.Reg = REGLINK
|
||||
q1.To.Type = obj.TYPE_MEM
|
||||
q1.Scond = C_XPRE
|
||||
q1.To.Offset = int64(-aoffset)
|
||||
q1.To.Reg = REGSP
|
||||
q1.Spadj = aoffset
|
||||
|
||||
prologueEnd = q1
|
||||
}
|
||||
|
||||
prologueEnd.Pos = prologueEnd.Pos.WithXlogue(src.PosPrologueEnd)
|
||||
|
||||
if objabi.Framepointer_enabled {
|
||||
q1 = obj.Appendp(q1, c.newprog)
|
||||
q1.Pos = p.Pos
|
||||
q1.As = AMOVD
|
||||
q1.From.Type = obj.TYPE_REG
|
||||
q1.From.Reg = REGFP
|
||||
q1.To.Type = obj.TYPE_MEM
|
||||
q1.To.Reg = REGSP
|
||||
q1.To.Offset = -8
|
||||
|
||||
q1 = obj.Appendp(q1, c.newprog)
|
||||
q1.Pos = p.Pos
|
||||
q1.As = ASUB
|
||||
q1.From.Type = obj.TYPE_CONST
|
||||
q1.From.Offset = 8
|
||||
q1.Reg = REGSP
|
||||
q1.To.Type = obj.TYPE_REG
|
||||
q1.To.Reg = REGFP
|
||||
}
|
||||
|
||||
if c.cursym.Func.Text.From.Sym.Wrapper() {
|
||||
// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame
|
||||
//
|
||||
// MOV g_panic(g), R1
|
||||
// CBNZ checkargp
|
||||
// end:
|
||||
// NOP
|
||||
// ... function body ...
|
||||
// checkargp:
|
||||
// MOV panic_argp(R1), R2
|
||||
// ADD $(autosize+8), RSP, R3
|
||||
// CMP R2, R3
|
||||
// BNE end
|
||||
// ADD $8, RSP, R4
|
||||
// MOVD R4, panic_argp(R1)
|
||||
// B end
|
||||
//
|
||||
// The NOP is needed to give the jumps somewhere to land.
|
||||
// It is a liblink NOP, not an ARM64 NOP: it encodes to 0 instruction bytes.
|
||||
q = q1
|
||||
|
||||
// MOV g_panic(g), R1
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = AMOVD
|
||||
q.From.Type = obj.TYPE_MEM
|
||||
q.From.Reg = REGG
|
||||
q.From.Offset = 4 * int64(c.ctxt.Arch.PtrSize) // G.panic
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REG_R1
|
||||
|
||||
// CBNZ R1, checkargp
|
||||
cbnz := obj.Appendp(q, c.newprog)
|
||||
cbnz.As = ACBNZ
|
||||
cbnz.From.Type = obj.TYPE_REG
|
||||
cbnz.From.Reg = REG_R1
|
||||
cbnz.To.Type = obj.TYPE_BRANCH
|
||||
|
||||
// Empty branch target at the top of the function body
|
||||
end := obj.Appendp(cbnz, c.newprog)
|
||||
end.As = obj.ANOP
|
||||
|
||||
// find the end of the function
|
||||
var last *obj.Prog
|
||||
for last = end; last.Link != nil; last = last.Link {
|
||||
}
|
||||
|
||||
// MOV panic_argp(R1), R2
|
||||
mov := obj.Appendp(last, c.newprog)
|
||||
mov.As = AMOVD
|
||||
mov.From.Type = obj.TYPE_MEM
|
||||
mov.From.Reg = REG_R1
|
||||
mov.From.Offset = 0 // Panic.argp
|
||||
mov.To.Type = obj.TYPE_REG
|
||||
mov.To.Reg = REG_R2
|
||||
|
||||
// CBNZ branches to the MOV above
|
||||
cbnz.To.SetTarget(mov)
|
||||
|
||||
// ADD $(autosize+8), SP, R3
|
||||
q = obj.Appendp(mov, c.newprog)
|
||||
q.As = AADD
|
||||
q.From.Type = obj.TYPE_CONST
|
||||
q.From.Offset = int64(c.autosize) + 8
|
||||
q.Reg = REGSP
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REG_R3
|
||||
|
||||
// CMP R2, R3
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = ACMP
|
||||
q.From.Type = obj.TYPE_REG
|
||||
q.From.Reg = REG_R2
|
||||
q.Reg = REG_R3
|
||||
|
||||
// BNE end
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = ABNE
|
||||
q.To.Type = obj.TYPE_BRANCH
|
||||
q.To.SetTarget(end)
|
||||
|
||||
// ADD $8, SP, R4
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = AADD
|
||||
q.From.Type = obj.TYPE_CONST
|
||||
q.From.Offset = 8
|
||||
q.Reg = REGSP
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REG_R4
|
||||
|
||||
// MOV R4, panic_argp(R1)
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = AMOVD
|
||||
q.From.Type = obj.TYPE_REG
|
||||
q.From.Reg = REG_R4
|
||||
q.To.Type = obj.TYPE_MEM
|
||||
q.To.Reg = REG_R1
|
||||
q.To.Offset = 0 // Panic.argp
|
||||
|
||||
// B end
|
||||
q = obj.Appendp(q, c.newprog)
|
||||
q.As = AB
|
||||
q.To.Type = obj.TYPE_BRANCH
|
||||
q.To.SetTarget(end)
|
||||
}
|
||||
|
||||
case obj.ARET:
|
||||
nocache(p)
|
||||
if p.From.Type == obj.TYPE_CONST {
|
||||
c.ctxt.Diag("using BECOME (%v) is not supported!", p)
|
||||
break
|
||||
}
|
||||
|
||||
retjmp = p.To.Sym
|
||||
p.To = obj.Addr{}
|
||||
if c.cursym.Func.Text.Mark&LEAF != 0 {
|
||||
if c.autosize != 0 {
|
||||
p.As = AADD
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = int64(c.autosize)
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGSP
|
||||
p.Spadj = -c.autosize
|
||||
|
||||
if objabi.Framepointer_enabled {
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
p.As = ASUB
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = 8
|
||||
p.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGFP
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* want write-back pre-indexed SP+autosize -> SP, loading REGLINK*/
|
||||
|
||||
if objabi.Framepointer_enabled {
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = REGSP
|
||||
p.From.Offset = -8
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGFP
|
||||
p = obj.Appendp(p, c.newprog)
|
||||
}
|
||||
|
||||
aoffset := c.autosize
|
||||
|
||||
if aoffset <= 0xF0 {
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.Scond = C_XPOST
|
||||
p.From.Offset = int64(aoffset)
|
||||
p.From.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGLINK
|
||||
p.Spadj = -aoffset
|
||||
} else {
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Offset = 0
|
||||
p.From.Reg = REGSP
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = REGLINK
|
||||
|
||||
q = newprog()
|
||||
q.As = AADD
|
||||
q.From.Type = obj.TYPE_CONST
|
||||
q.From.Offset = int64(aoffset)
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REGSP
|
||||
q.Link = p.Link
|
||||
q.Spadj = int32(-q.From.Offset)
|
||||
q.Pos = p.Pos
|
||||
p.Link = q
|
||||
p = q
|
||||
}
|
||||
}
|
||||
|
||||
if p.As != obj.ARET {
|
||||
q = newprog()
|
||||
q.Pos = p.Pos
|
||||
q.Link = p.Link
|
||||
p.Link = q
|
||||
p = q
|
||||
}
|
||||
|
||||
if retjmp != nil { // retjmp
|
||||
p.As = AB
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
p.To.Sym = retjmp
|
||||
p.Spadj = +c.autosize
|
||||
break
|
||||
}
|
||||
|
||||
p.As = obj.ARET
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Offset = 0
|
||||
p.To.Reg = REGLINK
|
||||
p.Spadj = +c.autosize
|
||||
|
||||
case AADD, ASUB:
|
||||
if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSP && p.From.Type == obj.TYPE_CONST {
|
||||
if p.As == AADD {
|
||||
p.Spadj = int32(-p.From.Offset)
|
||||
} else {
|
||||
p.Spadj = int32(+p.From.Offset)
|
||||
}
|
||||
}
|
||||
|
||||
case obj.AGETCALLERPC:
|
||||
if cursym.Leaf() {
|
||||
/* MOVD LR, Rd */
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = REGLINK
|
||||
} else {
|
||||
/* MOVD (RSP), Rd */
|
||||
p.As = AMOVD
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = REGSP
|
||||
}
|
||||
|
||||
case obj.ADUFFCOPY:
|
||||
if objabi.Framepointer_enabled {
|
||||
// ADR ret_addr, R27
|
||||
// STP (FP, R27), -24(SP)
|
||||
// SUB 24, SP, FP
|
||||
// DUFFCOPY
|
||||
// ret_addr:
|
||||
// SUB 8, SP, FP
|
||||
|
||||
q1 := p
|
||||
// copy DUFFCOPY from q1 to q4
|
||||
q4 := obj.Appendp(p, c.newprog)
|
||||
q4.Pos = p.Pos
|
||||
q4.As = obj.ADUFFCOPY
|
||||
q4.To = p.To
|
||||
|
||||
q1.As = AADR
|
||||
q1.From.Type = obj.TYPE_BRANCH
|
||||
q1.To.Type = obj.TYPE_REG
|
||||
q1.To.Reg = REG_R27
|
||||
|
||||
q2 := obj.Appendp(q1, c.newprog)
|
||||
q2.Pos = p.Pos
|
||||
q2.As = ASTP
|
||||
q2.From.Type = obj.TYPE_REGREG
|
||||
q2.From.Reg = REGFP
|
||||
q2.From.Offset = int64(REG_R27)
|
||||
q2.To.Type = obj.TYPE_MEM
|
||||
q2.To.Reg = REGSP
|
||||
q2.To.Offset = -24
|
||||
|
||||
// maintaine FP for DUFFCOPY
|
||||
q3 := obj.Appendp(q2, c.newprog)
|
||||
q3.Pos = p.Pos
|
||||
q3.As = ASUB
|
||||
q3.From.Type = obj.TYPE_CONST
|
||||
q3.From.Offset = 24
|
||||
q3.Reg = REGSP
|
||||
q3.To.Type = obj.TYPE_REG
|
||||
q3.To.Reg = REGFP
|
||||
|
||||
q5 := obj.Appendp(q4, c.newprog)
|
||||
q5.Pos = p.Pos
|
||||
q5.As = ASUB
|
||||
q5.From.Type = obj.TYPE_CONST
|
||||
q5.From.Offset = 8
|
||||
q5.Reg = REGSP
|
||||
q5.To.Type = obj.TYPE_REG
|
||||
q5.To.Reg = REGFP
|
||||
q1.From.SetTarget(q5)
|
||||
p = q5
|
||||
}
|
||||
|
||||
case obj.ADUFFZERO:
|
||||
if objabi.Framepointer_enabled {
|
||||
// ADR ret_addr, R27
|
||||
// STP (FP, R27), -24(SP)
|
||||
// SUB 24, SP, FP
|
||||
// DUFFZERO
|
||||
// ret_addr:
|
||||
// SUB 8, SP, FP
|
||||
|
||||
q1 := p
|
||||
// copy DUFFZERO from q1 to q4
|
||||
q4 := obj.Appendp(p, c.newprog)
|
||||
q4.Pos = p.Pos
|
||||
q4.As = obj.ADUFFZERO
|
||||
q4.To = p.To
|
||||
|
||||
q1.As = AADR
|
||||
q1.From.Type = obj.TYPE_BRANCH
|
||||
q1.To.Type = obj.TYPE_REG
|
||||
q1.To.Reg = REG_R27
|
||||
|
||||
q2 := obj.Appendp(q1, c.newprog)
|
||||
q2.Pos = p.Pos
|
||||
q2.As = ASTP
|
||||
q2.From.Type = obj.TYPE_REGREG
|
||||
q2.From.Reg = REGFP
|
||||
q2.From.Offset = int64(REG_R27)
|
||||
q2.To.Type = obj.TYPE_MEM
|
||||
q2.To.Reg = REGSP
|
||||
q2.To.Offset = -24
|
||||
|
||||
// maintaine FP for DUFFZERO
|
||||
q3 := obj.Appendp(q2, c.newprog)
|
||||
q3.Pos = p.Pos
|
||||
q3.As = ASUB
|
||||
q3.From.Type = obj.TYPE_CONST
|
||||
q3.From.Offset = 24
|
||||
q3.Reg = REGSP
|
||||
q3.To.Type = obj.TYPE_REG
|
||||
q3.To.Reg = REGFP
|
||||
|
||||
q5 := obj.Appendp(q4, c.newprog)
|
||||
q5.Pos = p.Pos
|
||||
q5.As = ASUB
|
||||
q5.From.Type = obj.TYPE_CONST
|
||||
q5.From.Offset = 8
|
||||
q5.Reg = REGSP
|
||||
q5.To.Type = obj.TYPE_REG
|
||||
q5.To.Reg = REGFP
|
||||
q1.From.SetTarget(q5)
|
||||
p = q5
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func nocache(p *obj.Prog) {
|
||||
p.Optab = 0
|
||||
p.From.Class = 0
|
||||
p.To.Class = 0
|
||||
}
|
||||
|
||||
var unaryDst = map[obj.As]bool{
|
||||
AWORD: true,
|
||||
ADWORD: true,
|
||||
ABL: true,
|
||||
AB: true,
|
||||
ACLREX: true,
|
||||
}
|
||||
|
||||
var Linkarm64 = obj.LinkArch{
|
||||
Arch: sys.ArchARM64,
|
||||
Init: buildop,
|
||||
Preprocess: preprocess,
|
||||
Assemble: span7,
|
||||
Progedit: progedit,
|
||||
UnaryDst: unaryDst,
|
||||
DWARFRegisters: ARM64DWARFRegisters,
|
||||
}
|
||||
895
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/sysRegEnc.go
generated
vendored
Normal file
895
vendor/github.com/twitchyliquid64/golang-asm/obj/arm64/sysRegEnc.go
generated
vendored
Normal file
@ -0,0 +1,895 @@
|
||||
// Code generated by arm64gen -i ./files -o sysRegEnc.go. DO NOT EDIT.
|
||||
|
||||
package arm64
|
||||
|
||||
const (
|
||||
SYSREG_BEGIN = REG_SPECIAL + iota
|
||||
REG_ACTLR_EL1
|
||||
REG_AFSR0_EL1
|
||||
REG_AFSR1_EL1
|
||||
REG_AIDR_EL1
|
||||
REG_AMAIR_EL1
|
||||
REG_AMCFGR_EL0
|
||||
REG_AMCGCR_EL0
|
||||
REG_AMCNTENCLR0_EL0
|
||||
REG_AMCNTENCLR1_EL0
|
||||
REG_AMCNTENSET0_EL0
|
||||
REG_AMCNTENSET1_EL0
|
||||
REG_AMCR_EL0
|
||||
REG_AMEVCNTR00_EL0
|
||||
REG_AMEVCNTR01_EL0
|
||||
REG_AMEVCNTR02_EL0
|
||||
REG_AMEVCNTR03_EL0
|
||||
REG_AMEVCNTR04_EL0
|
||||
REG_AMEVCNTR05_EL0
|
||||
REG_AMEVCNTR06_EL0
|
||||
REG_AMEVCNTR07_EL0
|
||||
REG_AMEVCNTR08_EL0
|
||||
REG_AMEVCNTR09_EL0
|
||||
REG_AMEVCNTR010_EL0
|
||||
REG_AMEVCNTR011_EL0
|
||||
REG_AMEVCNTR012_EL0
|
||||
REG_AMEVCNTR013_EL0
|
||||
REG_AMEVCNTR014_EL0
|
||||
REG_AMEVCNTR015_EL0
|
||||
REG_AMEVCNTR10_EL0
|
||||
REG_AMEVCNTR11_EL0
|
||||
REG_AMEVCNTR12_EL0
|
||||
REG_AMEVCNTR13_EL0
|
||||
REG_AMEVCNTR14_EL0
|
||||
REG_AMEVCNTR15_EL0
|
||||
REG_AMEVCNTR16_EL0
|
||||
REG_AMEVCNTR17_EL0
|
||||
REG_AMEVCNTR18_EL0
|
||||
REG_AMEVCNTR19_EL0
|
||||
REG_AMEVCNTR110_EL0
|
||||
REG_AMEVCNTR111_EL0
|
||||
REG_AMEVCNTR112_EL0
|
||||
REG_AMEVCNTR113_EL0
|
||||
REG_AMEVCNTR114_EL0
|
||||
REG_AMEVCNTR115_EL0
|
||||
REG_AMEVTYPER00_EL0
|
||||
REG_AMEVTYPER01_EL0
|
||||
REG_AMEVTYPER02_EL0
|
||||
REG_AMEVTYPER03_EL0
|
||||
REG_AMEVTYPER04_EL0
|
||||
REG_AMEVTYPER05_EL0
|
||||
REG_AMEVTYPER06_EL0
|
||||
REG_AMEVTYPER07_EL0
|
||||
REG_AMEVTYPER08_EL0
|
||||
REG_AMEVTYPER09_EL0
|
||||
REG_AMEVTYPER010_EL0
|
||||
REG_AMEVTYPER011_EL0
|
||||
REG_AMEVTYPER012_EL0
|
||||
REG_AMEVTYPER013_EL0
|
||||
REG_AMEVTYPER014_EL0
|
||||
REG_AMEVTYPER015_EL0
|
||||
REG_AMEVTYPER10_EL0
|
||||
REG_AMEVTYPER11_EL0
|
||||
REG_AMEVTYPER12_EL0
|
||||
REG_AMEVTYPER13_EL0
|
||||
REG_AMEVTYPER14_EL0
|
||||
REG_AMEVTYPER15_EL0
|
||||
REG_AMEVTYPER16_EL0
|
||||
REG_AMEVTYPER17_EL0
|
||||
REG_AMEVTYPER18_EL0
|
||||
REG_AMEVTYPER19_EL0
|
||||
REG_AMEVTYPER110_EL0
|
||||
REG_AMEVTYPER111_EL0
|
||||
REG_AMEVTYPER112_EL0
|
||||
REG_AMEVTYPER113_EL0
|
||||
REG_AMEVTYPER114_EL0
|
||||
REG_AMEVTYPER115_EL0
|
||||
REG_AMUSERENR_EL0
|
||||
REG_APDAKeyHi_EL1
|
||||
REG_APDAKeyLo_EL1
|
||||
REG_APDBKeyHi_EL1
|
||||
REG_APDBKeyLo_EL1
|
||||
REG_APGAKeyHi_EL1
|
||||
REG_APGAKeyLo_EL1
|
||||
REG_APIAKeyHi_EL1
|
||||
REG_APIAKeyLo_EL1
|
||||
REG_APIBKeyHi_EL1
|
||||
REG_APIBKeyLo_EL1
|
||||
REG_CCSIDR2_EL1
|
||||
REG_CCSIDR_EL1
|
||||
REG_CLIDR_EL1
|
||||
REG_CNTFRQ_EL0
|
||||
REG_CNTKCTL_EL1
|
||||
REG_CNTP_CTL_EL0
|
||||
REG_CNTP_CVAL_EL0
|
||||
REG_CNTP_TVAL_EL0
|
||||
REG_CNTPCT_EL0
|
||||
REG_CNTPS_CTL_EL1
|
||||
REG_CNTPS_CVAL_EL1
|
||||
REG_CNTPS_TVAL_EL1
|
||||
REG_CNTV_CTL_EL0
|
||||
REG_CNTV_CVAL_EL0
|
||||
REG_CNTV_TVAL_EL0
|
||||
REG_CNTVCT_EL0
|
||||
REG_CONTEXTIDR_EL1
|
||||
REG_CPACR_EL1
|
||||
REG_CSSELR_EL1
|
||||
REG_CTR_EL0
|
||||
REG_CurrentEL
|
||||
REG_DAIF
|
||||
REG_DBGAUTHSTATUS_EL1
|
||||
REG_DBGBCR0_EL1
|
||||
REG_DBGBCR1_EL1
|
||||
REG_DBGBCR2_EL1
|
||||
REG_DBGBCR3_EL1
|
||||
REG_DBGBCR4_EL1
|
||||
REG_DBGBCR5_EL1
|
||||
REG_DBGBCR6_EL1
|
||||
REG_DBGBCR7_EL1
|
||||
REG_DBGBCR8_EL1
|
||||
REG_DBGBCR9_EL1
|
||||
REG_DBGBCR10_EL1
|
||||
REG_DBGBCR11_EL1
|
||||
REG_DBGBCR12_EL1
|
||||
REG_DBGBCR13_EL1
|
||||
REG_DBGBCR14_EL1
|
||||
REG_DBGBCR15_EL1
|
||||
REG_DBGBVR0_EL1
|
||||
REG_DBGBVR1_EL1
|
||||
REG_DBGBVR2_EL1
|
||||
REG_DBGBVR3_EL1
|
||||
REG_DBGBVR4_EL1
|
||||
REG_DBGBVR5_EL1
|
||||
REG_DBGBVR6_EL1
|
||||
REG_DBGBVR7_EL1
|
||||
REG_DBGBVR8_EL1
|
||||
REG_DBGBVR9_EL1
|
||||
REG_DBGBVR10_EL1
|
||||
REG_DBGBVR11_EL1
|
||||
REG_DBGBVR12_EL1
|
||||
REG_DBGBVR13_EL1
|
||||
REG_DBGBVR14_EL1
|
||||
REG_DBGBVR15_EL1
|
||||
REG_DBGCLAIMCLR_EL1
|
||||
REG_DBGCLAIMSET_EL1
|
||||
REG_DBGDTR_EL0
|
||||
REG_DBGDTRRX_EL0
|
||||
REG_DBGDTRTX_EL0
|
||||
REG_DBGPRCR_EL1
|
||||
REG_DBGWCR0_EL1
|
||||
REG_DBGWCR1_EL1
|
||||
REG_DBGWCR2_EL1
|
||||
REG_DBGWCR3_EL1
|
||||
REG_DBGWCR4_EL1
|
||||
REG_DBGWCR5_EL1
|
||||
REG_DBGWCR6_EL1
|
||||
REG_DBGWCR7_EL1
|
||||
REG_DBGWCR8_EL1
|
||||
REG_DBGWCR9_EL1
|
||||
REG_DBGWCR10_EL1
|
||||
REG_DBGWCR11_EL1
|
||||
REG_DBGWCR12_EL1
|
||||
REG_DBGWCR13_EL1
|
||||
REG_DBGWCR14_EL1
|
||||
REG_DBGWCR15_EL1
|
||||
REG_DBGWVR0_EL1
|
||||
REG_DBGWVR1_EL1
|
||||
REG_DBGWVR2_EL1
|
||||
REG_DBGWVR3_EL1
|
||||
REG_DBGWVR4_EL1
|
||||
REG_DBGWVR5_EL1
|
||||
REG_DBGWVR6_EL1
|
||||
REG_DBGWVR7_EL1
|
||||
REG_DBGWVR8_EL1
|
||||
REG_DBGWVR9_EL1
|
||||
REG_DBGWVR10_EL1
|
||||
REG_DBGWVR11_EL1
|
||||
REG_DBGWVR12_EL1
|
||||
REG_DBGWVR13_EL1
|
||||
REG_DBGWVR14_EL1
|
||||
REG_DBGWVR15_EL1
|
||||
REG_DCZID_EL0
|
||||
REG_DISR_EL1
|
||||
REG_DIT
|
||||
REG_DLR_EL0
|
||||
REG_DSPSR_EL0
|
||||
REG_ELR_EL1
|
||||
REG_ERRIDR_EL1
|
||||
REG_ERRSELR_EL1
|
||||
REG_ERXADDR_EL1
|
||||
REG_ERXCTLR_EL1
|
||||
REG_ERXFR_EL1
|
||||
REG_ERXMISC0_EL1
|
||||
REG_ERXMISC1_EL1
|
||||
REG_ERXMISC2_EL1
|
||||
REG_ERXMISC3_EL1
|
||||
REG_ERXPFGCDN_EL1
|
||||
REG_ERXPFGCTL_EL1
|
||||
REG_ERXPFGF_EL1
|
||||
REG_ERXSTATUS_EL1
|
||||
REG_ESR_EL1
|
||||
REG_FAR_EL1
|
||||
REG_FPCR
|
||||
REG_FPSR
|
||||
REG_GCR_EL1
|
||||
REG_GMID_EL1
|
||||
REG_ICC_AP0R0_EL1
|
||||
REG_ICC_AP0R1_EL1
|
||||
REG_ICC_AP0R2_EL1
|
||||
REG_ICC_AP0R3_EL1
|
||||
REG_ICC_AP1R0_EL1
|
||||
REG_ICC_AP1R1_EL1
|
||||
REG_ICC_AP1R2_EL1
|
||||
REG_ICC_AP1R3_EL1
|
||||
REG_ICC_ASGI1R_EL1
|
||||
REG_ICC_BPR0_EL1
|
||||
REG_ICC_BPR1_EL1
|
||||
REG_ICC_CTLR_EL1
|
||||
REG_ICC_DIR_EL1
|
||||
REG_ICC_EOIR0_EL1
|
||||
REG_ICC_EOIR1_EL1
|
||||
REG_ICC_HPPIR0_EL1
|
||||
REG_ICC_HPPIR1_EL1
|
||||
REG_ICC_IAR0_EL1
|
||||
REG_ICC_IAR1_EL1
|
||||
REG_ICC_IGRPEN0_EL1
|
||||
REG_ICC_IGRPEN1_EL1
|
||||
REG_ICC_PMR_EL1
|
||||
REG_ICC_RPR_EL1
|
||||
REG_ICC_SGI0R_EL1
|
||||
REG_ICC_SGI1R_EL1
|
||||
REG_ICC_SRE_EL1
|
||||
REG_ICV_AP0R0_EL1
|
||||
REG_ICV_AP0R1_EL1
|
||||
REG_ICV_AP0R2_EL1
|
||||
REG_ICV_AP0R3_EL1
|
||||
REG_ICV_AP1R0_EL1
|
||||
REG_ICV_AP1R1_EL1
|
||||
REG_ICV_AP1R2_EL1
|
||||
REG_ICV_AP1R3_EL1
|
||||
REG_ICV_BPR0_EL1
|
||||
REG_ICV_BPR1_EL1
|
||||
REG_ICV_CTLR_EL1
|
||||
REG_ICV_DIR_EL1
|
||||
REG_ICV_EOIR0_EL1
|
||||
REG_ICV_EOIR1_EL1
|
||||
REG_ICV_HPPIR0_EL1
|
||||
REG_ICV_HPPIR1_EL1
|
||||
REG_ICV_IAR0_EL1
|
||||
REG_ICV_IAR1_EL1
|
||||
REG_ICV_IGRPEN0_EL1
|
||||
REG_ICV_IGRPEN1_EL1
|
||||
REG_ICV_PMR_EL1
|
||||
REG_ICV_RPR_EL1
|
||||
REG_ID_AA64AFR0_EL1
|
||||
REG_ID_AA64AFR1_EL1
|
||||
REG_ID_AA64DFR0_EL1
|
||||
REG_ID_AA64DFR1_EL1
|
||||
REG_ID_AA64ISAR0_EL1
|
||||
REG_ID_AA64ISAR1_EL1
|
||||
REG_ID_AA64MMFR0_EL1
|
||||
REG_ID_AA64MMFR1_EL1
|
||||
REG_ID_AA64MMFR2_EL1
|
||||
REG_ID_AA64PFR0_EL1
|
||||
REG_ID_AA64PFR1_EL1
|
||||
REG_ID_AA64ZFR0_EL1
|
||||
REG_ID_AFR0_EL1
|
||||
REG_ID_DFR0_EL1
|
||||
REG_ID_ISAR0_EL1
|
||||
REG_ID_ISAR1_EL1
|
||||
REG_ID_ISAR2_EL1
|
||||
REG_ID_ISAR3_EL1
|
||||
REG_ID_ISAR4_EL1
|
||||
REG_ID_ISAR5_EL1
|
||||
REG_ID_ISAR6_EL1
|
||||
REG_ID_MMFR0_EL1
|
||||
REG_ID_MMFR1_EL1
|
||||
REG_ID_MMFR2_EL1
|
||||
REG_ID_MMFR3_EL1
|
||||
REG_ID_MMFR4_EL1
|
||||
REG_ID_PFR0_EL1
|
||||
REG_ID_PFR1_EL1
|
||||
REG_ID_PFR2_EL1
|
||||
REG_ISR_EL1
|
||||
REG_LORC_EL1
|
||||
REG_LOREA_EL1
|
||||
REG_LORID_EL1
|
||||
REG_LORN_EL1
|
||||
REG_LORSA_EL1
|
||||
REG_MAIR_EL1
|
||||
REG_MDCCINT_EL1
|
||||
REG_MDCCSR_EL0
|
||||
REG_MDRAR_EL1
|
||||
REG_MDSCR_EL1
|
||||
REG_MIDR_EL1
|
||||
REG_MPAM0_EL1
|
||||
REG_MPAM1_EL1
|
||||
REG_MPAMIDR_EL1
|
||||
REG_MPIDR_EL1
|
||||
REG_MVFR0_EL1
|
||||
REG_MVFR1_EL1
|
||||
REG_MVFR2_EL1
|
||||
REG_NZCV
|
||||
REG_OSDLR_EL1
|
||||
REG_OSDTRRX_EL1
|
||||
REG_OSDTRTX_EL1
|
||||
REG_OSECCR_EL1
|
||||
REG_OSLAR_EL1
|
||||
REG_OSLSR_EL1
|
||||
REG_PAN
|
||||
REG_PAR_EL1
|
||||
REG_PMBIDR_EL1
|
||||
REG_PMBLIMITR_EL1
|
||||
REG_PMBPTR_EL1
|
||||
REG_PMBSR_EL1
|
||||
REG_PMCCFILTR_EL0
|
||||
REG_PMCCNTR_EL0
|
||||
REG_PMCEID0_EL0
|
||||
REG_PMCEID1_EL0
|
||||
REG_PMCNTENCLR_EL0
|
||||
REG_PMCNTENSET_EL0
|
||||
REG_PMCR_EL0
|
||||
REG_PMEVCNTR0_EL0
|
||||
REG_PMEVCNTR1_EL0
|
||||
REG_PMEVCNTR2_EL0
|
||||
REG_PMEVCNTR3_EL0
|
||||
REG_PMEVCNTR4_EL0
|
||||
REG_PMEVCNTR5_EL0
|
||||
REG_PMEVCNTR6_EL0
|
||||
REG_PMEVCNTR7_EL0
|
||||
REG_PMEVCNTR8_EL0
|
||||
REG_PMEVCNTR9_EL0
|
||||
REG_PMEVCNTR10_EL0
|
||||
REG_PMEVCNTR11_EL0
|
||||
REG_PMEVCNTR12_EL0
|
||||
REG_PMEVCNTR13_EL0
|
||||
REG_PMEVCNTR14_EL0
|
||||
REG_PMEVCNTR15_EL0
|
||||
REG_PMEVCNTR16_EL0
|
||||
REG_PMEVCNTR17_EL0
|
||||
REG_PMEVCNTR18_EL0
|
||||
REG_PMEVCNTR19_EL0
|
||||
REG_PMEVCNTR20_EL0
|
||||
REG_PMEVCNTR21_EL0
|
||||
REG_PMEVCNTR22_EL0
|
||||
REG_PMEVCNTR23_EL0
|
||||
REG_PMEVCNTR24_EL0
|
||||
REG_PMEVCNTR25_EL0
|
||||
REG_PMEVCNTR26_EL0
|
||||
REG_PMEVCNTR27_EL0
|
||||
REG_PMEVCNTR28_EL0
|
||||
REG_PMEVCNTR29_EL0
|
||||
REG_PMEVCNTR30_EL0
|
||||
REG_PMEVTYPER0_EL0
|
||||
REG_PMEVTYPER1_EL0
|
||||
REG_PMEVTYPER2_EL0
|
||||
REG_PMEVTYPER3_EL0
|
||||
REG_PMEVTYPER4_EL0
|
||||
REG_PMEVTYPER5_EL0
|
||||
REG_PMEVTYPER6_EL0
|
||||
REG_PMEVTYPER7_EL0
|
||||
REG_PMEVTYPER8_EL0
|
||||
REG_PMEVTYPER9_EL0
|
||||
REG_PMEVTYPER10_EL0
|
||||
REG_PMEVTYPER11_EL0
|
||||
REG_PMEVTYPER12_EL0
|
||||
REG_PMEVTYPER13_EL0
|
||||
REG_PMEVTYPER14_EL0
|
||||
REG_PMEVTYPER15_EL0
|
||||
REG_PMEVTYPER16_EL0
|
||||
REG_PMEVTYPER17_EL0
|
||||
REG_PMEVTYPER18_EL0
|
||||
REG_PMEVTYPER19_EL0
|
||||
REG_PMEVTYPER20_EL0
|
||||
REG_PMEVTYPER21_EL0
|
||||
REG_PMEVTYPER22_EL0
|
||||
REG_PMEVTYPER23_EL0
|
||||
REG_PMEVTYPER24_EL0
|
||||
REG_PMEVTYPER25_EL0
|
||||
REG_PMEVTYPER26_EL0
|
||||
REG_PMEVTYPER27_EL0
|
||||
REG_PMEVTYPER28_EL0
|
||||
REG_PMEVTYPER29_EL0
|
||||
REG_PMEVTYPER30_EL0
|
||||
REG_PMINTENCLR_EL1
|
||||
REG_PMINTENSET_EL1
|
||||
REG_PMMIR_EL1
|
||||
REG_PMOVSCLR_EL0
|
||||
REG_PMOVSSET_EL0
|
||||
REG_PMSCR_EL1
|
||||
REG_PMSELR_EL0
|
||||
REG_PMSEVFR_EL1
|
||||
REG_PMSFCR_EL1
|
||||
REG_PMSICR_EL1
|
||||
REG_PMSIDR_EL1
|
||||
REG_PMSIRR_EL1
|
||||
REG_PMSLATFR_EL1
|
||||
REG_PMSWINC_EL0
|
||||
REG_PMUSERENR_EL0
|
||||
REG_PMXEVCNTR_EL0
|
||||
REG_PMXEVTYPER_EL0
|
||||
REG_REVIDR_EL1
|
||||
REG_RGSR_EL1
|
||||
REG_RMR_EL1
|
||||
REG_RNDR
|
||||
REG_RNDRRS
|
||||
REG_RVBAR_EL1
|
||||
REG_SCTLR_EL1
|
||||
REG_SCXTNUM_EL0
|
||||
REG_SCXTNUM_EL1
|
||||
REG_SP_EL0
|
||||
REG_SP_EL1
|
||||
REG_SPSel
|
||||
REG_SPSR_abt
|
||||
REG_SPSR_EL1
|
||||
REG_SPSR_fiq
|
||||
REG_SPSR_irq
|
||||
REG_SPSR_und
|
||||
REG_SSBS
|
||||
REG_TCO
|
||||
REG_TCR_EL1
|
||||
REG_TFSR_EL1
|
||||
REG_TFSRE0_EL1
|
||||
REG_TPIDR_EL0
|
||||
REG_TPIDR_EL1
|
||||
REG_TPIDRRO_EL0
|
||||
REG_TRFCR_EL1
|
||||
REG_TTBR0_EL1
|
||||
REG_TTBR1_EL1
|
||||
REG_UAO
|
||||
REG_VBAR_EL1
|
||||
REG_ZCR_EL1
|
||||
SYSREG_END
|
||||
)
|
||||
|
||||
const (
|
||||
SR_READ = 1 << iota
|
||||
SR_WRITE
|
||||
)
|
||||
|
||||
var SystemReg = []struct {
|
||||
Name string
|
||||
Reg int16
|
||||
Enc uint32
|
||||
// AccessFlags is the readable and writeable property of system register.
|
||||
AccessFlags uint8
|
||||
}{
|
||||
{"ACTLR_EL1", REG_ACTLR_EL1, 0x181020, SR_READ | SR_WRITE},
|
||||
{"AFSR0_EL1", REG_AFSR0_EL1, 0x185100, SR_READ | SR_WRITE},
|
||||
{"AFSR1_EL1", REG_AFSR1_EL1, 0x185120, SR_READ | SR_WRITE},
|
||||
{"AIDR_EL1", REG_AIDR_EL1, 0x1900e0, SR_READ},
|
||||
{"AMAIR_EL1", REG_AMAIR_EL1, 0x18a300, SR_READ | SR_WRITE},
|
||||
{"AMCFGR_EL0", REG_AMCFGR_EL0, 0x1bd220, SR_READ},
|
||||
{"AMCGCR_EL0", REG_AMCGCR_EL0, 0x1bd240, SR_READ},
|
||||
{"AMCNTENCLR0_EL0", REG_AMCNTENCLR0_EL0, 0x1bd280, SR_READ | SR_WRITE},
|
||||
{"AMCNTENCLR1_EL0", REG_AMCNTENCLR1_EL0, 0x1bd300, SR_READ | SR_WRITE},
|
||||
{"AMCNTENSET0_EL0", REG_AMCNTENSET0_EL0, 0x1bd2a0, SR_READ | SR_WRITE},
|
||||
{"AMCNTENSET1_EL0", REG_AMCNTENSET1_EL0, 0x1bd320, SR_READ | SR_WRITE},
|
||||
{"AMCR_EL0", REG_AMCR_EL0, 0x1bd200, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR00_EL0", REG_AMEVCNTR00_EL0, 0x1bd400, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR01_EL0", REG_AMEVCNTR01_EL0, 0x1bd420, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR02_EL0", REG_AMEVCNTR02_EL0, 0x1bd440, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR03_EL0", REG_AMEVCNTR03_EL0, 0x1bd460, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR04_EL0", REG_AMEVCNTR04_EL0, 0x1bd480, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR05_EL0", REG_AMEVCNTR05_EL0, 0x1bd4a0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR06_EL0", REG_AMEVCNTR06_EL0, 0x1bd4c0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR07_EL0", REG_AMEVCNTR07_EL0, 0x1bd4e0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR08_EL0", REG_AMEVCNTR08_EL0, 0x1bd500, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR09_EL0", REG_AMEVCNTR09_EL0, 0x1bd520, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR010_EL0", REG_AMEVCNTR010_EL0, 0x1bd540, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR011_EL0", REG_AMEVCNTR011_EL0, 0x1bd560, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR012_EL0", REG_AMEVCNTR012_EL0, 0x1bd580, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR013_EL0", REG_AMEVCNTR013_EL0, 0x1bd5a0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR014_EL0", REG_AMEVCNTR014_EL0, 0x1bd5c0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR015_EL0", REG_AMEVCNTR015_EL0, 0x1bd5e0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR10_EL0", REG_AMEVCNTR10_EL0, 0x1bdc00, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR11_EL0", REG_AMEVCNTR11_EL0, 0x1bdc20, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR12_EL0", REG_AMEVCNTR12_EL0, 0x1bdc40, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR13_EL0", REG_AMEVCNTR13_EL0, 0x1bdc60, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR14_EL0", REG_AMEVCNTR14_EL0, 0x1bdc80, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR15_EL0", REG_AMEVCNTR15_EL0, 0x1bdca0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR16_EL0", REG_AMEVCNTR16_EL0, 0x1bdcc0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR17_EL0", REG_AMEVCNTR17_EL0, 0x1bdce0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR18_EL0", REG_AMEVCNTR18_EL0, 0x1bdd00, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR19_EL0", REG_AMEVCNTR19_EL0, 0x1bdd20, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR110_EL0", REG_AMEVCNTR110_EL0, 0x1bdd40, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR111_EL0", REG_AMEVCNTR111_EL0, 0x1bdd60, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR112_EL0", REG_AMEVCNTR112_EL0, 0x1bdd80, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR113_EL0", REG_AMEVCNTR113_EL0, 0x1bdda0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR114_EL0", REG_AMEVCNTR114_EL0, 0x1bddc0, SR_READ | SR_WRITE},
|
||||
{"AMEVCNTR115_EL0", REG_AMEVCNTR115_EL0, 0x1bdde0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER00_EL0", REG_AMEVTYPER00_EL0, 0x1bd600, SR_READ},
|
||||
{"AMEVTYPER01_EL0", REG_AMEVTYPER01_EL0, 0x1bd620, SR_READ},
|
||||
{"AMEVTYPER02_EL0", REG_AMEVTYPER02_EL0, 0x1bd640, SR_READ},
|
||||
{"AMEVTYPER03_EL0", REG_AMEVTYPER03_EL0, 0x1bd660, SR_READ},
|
||||
{"AMEVTYPER04_EL0", REG_AMEVTYPER04_EL0, 0x1bd680, SR_READ},
|
||||
{"AMEVTYPER05_EL0", REG_AMEVTYPER05_EL0, 0x1bd6a0, SR_READ},
|
||||
{"AMEVTYPER06_EL0", REG_AMEVTYPER06_EL0, 0x1bd6c0, SR_READ},
|
||||
{"AMEVTYPER07_EL0", REG_AMEVTYPER07_EL0, 0x1bd6e0, SR_READ},
|
||||
{"AMEVTYPER08_EL0", REG_AMEVTYPER08_EL0, 0x1bd700, SR_READ},
|
||||
{"AMEVTYPER09_EL0", REG_AMEVTYPER09_EL0, 0x1bd720, SR_READ},
|
||||
{"AMEVTYPER010_EL0", REG_AMEVTYPER010_EL0, 0x1bd740, SR_READ},
|
||||
{"AMEVTYPER011_EL0", REG_AMEVTYPER011_EL0, 0x1bd760, SR_READ},
|
||||
{"AMEVTYPER012_EL0", REG_AMEVTYPER012_EL0, 0x1bd780, SR_READ},
|
||||
{"AMEVTYPER013_EL0", REG_AMEVTYPER013_EL0, 0x1bd7a0, SR_READ},
|
||||
{"AMEVTYPER014_EL0", REG_AMEVTYPER014_EL0, 0x1bd7c0, SR_READ},
|
||||
{"AMEVTYPER015_EL0", REG_AMEVTYPER015_EL0, 0x1bd7e0, SR_READ},
|
||||
{"AMEVTYPER10_EL0", REG_AMEVTYPER10_EL0, 0x1bde00, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER11_EL0", REG_AMEVTYPER11_EL0, 0x1bde20, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER12_EL0", REG_AMEVTYPER12_EL0, 0x1bde40, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER13_EL0", REG_AMEVTYPER13_EL0, 0x1bde60, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER14_EL0", REG_AMEVTYPER14_EL0, 0x1bde80, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER15_EL0", REG_AMEVTYPER15_EL0, 0x1bdea0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER16_EL0", REG_AMEVTYPER16_EL0, 0x1bdec0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER17_EL0", REG_AMEVTYPER17_EL0, 0x1bdee0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER18_EL0", REG_AMEVTYPER18_EL0, 0x1bdf00, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER19_EL0", REG_AMEVTYPER19_EL0, 0x1bdf20, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER110_EL0", REG_AMEVTYPER110_EL0, 0x1bdf40, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER111_EL0", REG_AMEVTYPER111_EL0, 0x1bdf60, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER112_EL0", REG_AMEVTYPER112_EL0, 0x1bdf80, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER113_EL0", REG_AMEVTYPER113_EL0, 0x1bdfa0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER114_EL0", REG_AMEVTYPER114_EL0, 0x1bdfc0, SR_READ | SR_WRITE},
|
||||
{"AMEVTYPER115_EL0", REG_AMEVTYPER115_EL0, 0x1bdfe0, SR_READ | SR_WRITE},
|
||||
{"AMUSERENR_EL0", REG_AMUSERENR_EL0, 0x1bd260, SR_READ | SR_WRITE},
|
||||
{"APDAKeyHi_EL1", REG_APDAKeyHi_EL1, 0x182220, SR_READ | SR_WRITE},
|
||||
{"APDAKeyLo_EL1", REG_APDAKeyLo_EL1, 0x182200, SR_READ | SR_WRITE},
|
||||
{"APDBKeyHi_EL1", REG_APDBKeyHi_EL1, 0x182260, SR_READ | SR_WRITE},
|
||||
{"APDBKeyLo_EL1", REG_APDBKeyLo_EL1, 0x182240, SR_READ | SR_WRITE},
|
||||
{"APGAKeyHi_EL1", REG_APGAKeyHi_EL1, 0x182320, SR_READ | SR_WRITE},
|
||||
{"APGAKeyLo_EL1", REG_APGAKeyLo_EL1, 0x182300, SR_READ | SR_WRITE},
|
||||
{"APIAKeyHi_EL1", REG_APIAKeyHi_EL1, 0x182120, SR_READ | SR_WRITE},
|
||||
{"APIAKeyLo_EL1", REG_APIAKeyLo_EL1, 0x182100, SR_READ | SR_WRITE},
|
||||
{"APIBKeyHi_EL1", REG_APIBKeyHi_EL1, 0x182160, SR_READ | SR_WRITE},
|
||||
{"APIBKeyLo_EL1", REG_APIBKeyLo_EL1, 0x182140, SR_READ | SR_WRITE},
|
||||
{"CCSIDR2_EL1", REG_CCSIDR2_EL1, 0x190040, SR_READ},
|
||||
{"CCSIDR_EL1", REG_CCSIDR_EL1, 0x190000, SR_READ},
|
||||
{"CLIDR_EL1", REG_CLIDR_EL1, 0x190020, SR_READ},
|
||||
{"CNTFRQ_EL0", REG_CNTFRQ_EL0, 0x1be000, SR_READ | SR_WRITE},
|
||||
{"CNTKCTL_EL1", REG_CNTKCTL_EL1, 0x18e100, SR_READ | SR_WRITE},
|
||||
{"CNTP_CTL_EL0", REG_CNTP_CTL_EL0, 0x1be220, SR_READ | SR_WRITE},
|
||||
{"CNTP_CVAL_EL0", REG_CNTP_CVAL_EL0, 0x1be240, SR_READ | SR_WRITE},
|
||||
{"CNTP_TVAL_EL0", REG_CNTP_TVAL_EL0, 0x1be200, SR_READ | SR_WRITE},
|
||||
{"CNTPCT_EL0", REG_CNTPCT_EL0, 0x1be020, SR_READ},
|
||||
{"CNTPS_CTL_EL1", REG_CNTPS_CTL_EL1, 0x1fe220, SR_READ | SR_WRITE},
|
||||
{"CNTPS_CVAL_EL1", REG_CNTPS_CVAL_EL1, 0x1fe240, SR_READ | SR_WRITE},
|
||||
{"CNTPS_TVAL_EL1", REG_CNTPS_TVAL_EL1, 0x1fe200, SR_READ | SR_WRITE},
|
||||
{"CNTV_CTL_EL0", REG_CNTV_CTL_EL0, 0x1be320, SR_READ | SR_WRITE},
|
||||
{"CNTV_CVAL_EL0", REG_CNTV_CVAL_EL0, 0x1be340, SR_READ | SR_WRITE},
|
||||
{"CNTV_TVAL_EL0", REG_CNTV_TVAL_EL0, 0x1be300, SR_READ | SR_WRITE},
|
||||
{"CNTVCT_EL0", REG_CNTVCT_EL0, 0x1be040, SR_READ},
|
||||
{"CONTEXTIDR_EL1", REG_CONTEXTIDR_EL1, 0x18d020, SR_READ | SR_WRITE},
|
||||
{"CPACR_EL1", REG_CPACR_EL1, 0x181040, SR_READ | SR_WRITE},
|
||||
{"CSSELR_EL1", REG_CSSELR_EL1, 0x1a0000, SR_READ | SR_WRITE},
|
||||
{"CTR_EL0", REG_CTR_EL0, 0x1b0020, SR_READ},
|
||||
{"CurrentEL", REG_CurrentEL, 0x184240, SR_READ},
|
||||
{"DAIF", REG_DAIF, 0x1b4220, SR_READ | SR_WRITE},
|
||||
{"DBGAUTHSTATUS_EL1", REG_DBGAUTHSTATUS_EL1, 0x107ec0, SR_READ},
|
||||
{"DBGBCR0_EL1", REG_DBGBCR0_EL1, 0x1000a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR1_EL1", REG_DBGBCR1_EL1, 0x1001a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR2_EL1", REG_DBGBCR2_EL1, 0x1002a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR3_EL1", REG_DBGBCR3_EL1, 0x1003a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR4_EL1", REG_DBGBCR4_EL1, 0x1004a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR5_EL1", REG_DBGBCR5_EL1, 0x1005a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR6_EL1", REG_DBGBCR6_EL1, 0x1006a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR7_EL1", REG_DBGBCR7_EL1, 0x1007a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR8_EL1", REG_DBGBCR8_EL1, 0x1008a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR9_EL1", REG_DBGBCR9_EL1, 0x1009a0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR10_EL1", REG_DBGBCR10_EL1, 0x100aa0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR11_EL1", REG_DBGBCR11_EL1, 0x100ba0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR12_EL1", REG_DBGBCR12_EL1, 0x100ca0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR13_EL1", REG_DBGBCR13_EL1, 0x100da0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR14_EL1", REG_DBGBCR14_EL1, 0x100ea0, SR_READ | SR_WRITE},
|
||||
{"DBGBCR15_EL1", REG_DBGBCR15_EL1, 0x100fa0, SR_READ | SR_WRITE},
|
||||
{"DBGBVR0_EL1", REG_DBGBVR0_EL1, 0x100080, SR_READ | SR_WRITE},
|
||||
{"DBGBVR1_EL1", REG_DBGBVR1_EL1, 0x100180, SR_READ | SR_WRITE},
|
||||
{"DBGBVR2_EL1", REG_DBGBVR2_EL1, 0x100280, SR_READ | SR_WRITE},
|
||||
{"DBGBVR3_EL1", REG_DBGBVR3_EL1, 0x100380, SR_READ | SR_WRITE},
|
||||
{"DBGBVR4_EL1", REG_DBGBVR4_EL1, 0x100480, SR_READ | SR_WRITE},
|
||||
{"DBGBVR5_EL1", REG_DBGBVR5_EL1, 0x100580, SR_READ | SR_WRITE},
|
||||
{"DBGBVR6_EL1", REG_DBGBVR6_EL1, 0x100680, SR_READ | SR_WRITE},
|
||||
{"DBGBVR7_EL1", REG_DBGBVR7_EL1, 0x100780, SR_READ | SR_WRITE},
|
||||
{"DBGBVR8_EL1", REG_DBGBVR8_EL1, 0x100880, SR_READ | SR_WRITE},
|
||||
{"DBGBVR9_EL1", REG_DBGBVR9_EL1, 0x100980, SR_READ | SR_WRITE},
|
||||
{"DBGBVR10_EL1", REG_DBGBVR10_EL1, 0x100a80, SR_READ | SR_WRITE},
|
||||
{"DBGBVR11_EL1", REG_DBGBVR11_EL1, 0x100b80, SR_READ | SR_WRITE},
|
||||
{"DBGBVR12_EL1", REG_DBGBVR12_EL1, 0x100c80, SR_READ | SR_WRITE},
|
||||
{"DBGBVR13_EL1", REG_DBGBVR13_EL1, 0x100d80, SR_READ | SR_WRITE},
|
||||
{"DBGBVR14_EL1", REG_DBGBVR14_EL1, 0x100e80, SR_READ | SR_WRITE},
|
||||
{"DBGBVR15_EL1", REG_DBGBVR15_EL1, 0x100f80, SR_READ | SR_WRITE},
|
||||
{"DBGCLAIMCLR_EL1", REG_DBGCLAIMCLR_EL1, 0x1079c0, SR_READ | SR_WRITE},
|
||||
{"DBGCLAIMSET_EL1", REG_DBGCLAIMSET_EL1, 0x1078c0, SR_READ | SR_WRITE},
|
||||
{"DBGDTR_EL0", REG_DBGDTR_EL0, 0x130400, SR_READ | SR_WRITE},
|
||||
{"DBGDTRRX_EL0", REG_DBGDTRRX_EL0, 0x130500, SR_READ},
|
||||
{"DBGDTRTX_EL0", REG_DBGDTRTX_EL0, 0x130500, SR_WRITE},
|
||||
{"DBGPRCR_EL1", REG_DBGPRCR_EL1, 0x101480, SR_READ | SR_WRITE},
|
||||
{"DBGWCR0_EL1", REG_DBGWCR0_EL1, 0x1000e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR1_EL1", REG_DBGWCR1_EL1, 0x1001e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR2_EL1", REG_DBGWCR2_EL1, 0x1002e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR3_EL1", REG_DBGWCR3_EL1, 0x1003e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR4_EL1", REG_DBGWCR4_EL1, 0x1004e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR5_EL1", REG_DBGWCR5_EL1, 0x1005e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR6_EL1", REG_DBGWCR6_EL1, 0x1006e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR7_EL1", REG_DBGWCR7_EL1, 0x1007e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR8_EL1", REG_DBGWCR8_EL1, 0x1008e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR9_EL1", REG_DBGWCR9_EL1, 0x1009e0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR10_EL1", REG_DBGWCR10_EL1, 0x100ae0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR11_EL1", REG_DBGWCR11_EL1, 0x100be0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR12_EL1", REG_DBGWCR12_EL1, 0x100ce0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR13_EL1", REG_DBGWCR13_EL1, 0x100de0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR14_EL1", REG_DBGWCR14_EL1, 0x100ee0, SR_READ | SR_WRITE},
|
||||
{"DBGWCR15_EL1", REG_DBGWCR15_EL1, 0x100fe0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR0_EL1", REG_DBGWVR0_EL1, 0x1000c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR1_EL1", REG_DBGWVR1_EL1, 0x1001c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR2_EL1", REG_DBGWVR2_EL1, 0x1002c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR3_EL1", REG_DBGWVR3_EL1, 0x1003c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR4_EL1", REG_DBGWVR4_EL1, 0x1004c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR5_EL1", REG_DBGWVR5_EL1, 0x1005c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR6_EL1", REG_DBGWVR6_EL1, 0x1006c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR7_EL1", REG_DBGWVR7_EL1, 0x1007c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR8_EL1", REG_DBGWVR8_EL1, 0x1008c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR9_EL1", REG_DBGWVR9_EL1, 0x1009c0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR10_EL1", REG_DBGWVR10_EL1, 0x100ac0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR11_EL1", REG_DBGWVR11_EL1, 0x100bc0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR12_EL1", REG_DBGWVR12_EL1, 0x100cc0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR13_EL1", REG_DBGWVR13_EL1, 0x100dc0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR14_EL1", REG_DBGWVR14_EL1, 0x100ec0, SR_READ | SR_WRITE},
|
||||
{"DBGWVR15_EL1", REG_DBGWVR15_EL1, 0x100fc0, SR_READ | SR_WRITE},
|
||||
{"DCZID_EL0", REG_DCZID_EL0, 0x1b00e0, SR_READ},
|
||||
{"DISR_EL1", REG_DISR_EL1, 0x18c120, SR_READ | SR_WRITE},
|
||||
{"DIT", REG_DIT, 0x1b42a0, SR_READ | SR_WRITE},
|
||||
{"DLR_EL0", REG_DLR_EL0, 0x1b4520, SR_READ | SR_WRITE},
|
||||
{"DSPSR_EL0", REG_DSPSR_EL0, 0x1b4500, SR_READ | SR_WRITE},
|
||||
{"ELR_EL1", REG_ELR_EL1, 0x184020, SR_READ | SR_WRITE},
|
||||
{"ERRIDR_EL1", REG_ERRIDR_EL1, 0x185300, SR_READ},
|
||||
{"ERRSELR_EL1", REG_ERRSELR_EL1, 0x185320, SR_READ | SR_WRITE},
|
||||
{"ERXADDR_EL1", REG_ERXADDR_EL1, 0x185460, SR_READ | SR_WRITE},
|
||||
{"ERXCTLR_EL1", REG_ERXCTLR_EL1, 0x185420, SR_READ | SR_WRITE},
|
||||
{"ERXFR_EL1", REG_ERXFR_EL1, 0x185400, SR_READ},
|
||||
{"ERXMISC0_EL1", REG_ERXMISC0_EL1, 0x185500, SR_READ | SR_WRITE},
|
||||
{"ERXMISC1_EL1", REG_ERXMISC1_EL1, 0x185520, SR_READ | SR_WRITE},
|
||||
{"ERXMISC2_EL1", REG_ERXMISC2_EL1, 0x185540, SR_READ | SR_WRITE},
|
||||
{"ERXMISC3_EL1", REG_ERXMISC3_EL1, 0x185560, SR_READ | SR_WRITE},
|
||||
{"ERXPFGCDN_EL1", REG_ERXPFGCDN_EL1, 0x1854c0, SR_READ | SR_WRITE},
|
||||
{"ERXPFGCTL_EL1", REG_ERXPFGCTL_EL1, 0x1854a0, SR_READ | SR_WRITE},
|
||||
{"ERXPFGF_EL1", REG_ERXPFGF_EL1, 0x185480, SR_READ},
|
||||
{"ERXSTATUS_EL1", REG_ERXSTATUS_EL1, 0x185440, SR_READ | SR_WRITE},
|
||||
{"ESR_EL1", REG_ESR_EL1, 0x185200, SR_READ | SR_WRITE},
|
||||
{"FAR_EL1", REG_FAR_EL1, 0x186000, SR_READ | SR_WRITE},
|
||||
{"FPCR", REG_FPCR, 0x1b4400, SR_READ | SR_WRITE},
|
||||
{"FPSR", REG_FPSR, 0x1b4420, SR_READ | SR_WRITE},
|
||||
{"GCR_EL1", REG_GCR_EL1, 0x1810c0, SR_READ | SR_WRITE},
|
||||
{"GMID_EL1", REG_GMID_EL1, 0x31400, SR_READ},
|
||||
{"ICC_AP0R0_EL1", REG_ICC_AP0R0_EL1, 0x18c880, SR_READ | SR_WRITE},
|
||||
{"ICC_AP0R1_EL1", REG_ICC_AP0R1_EL1, 0x18c8a0, SR_READ | SR_WRITE},
|
||||
{"ICC_AP0R2_EL1", REG_ICC_AP0R2_EL1, 0x18c8c0, SR_READ | SR_WRITE},
|
||||
{"ICC_AP0R3_EL1", REG_ICC_AP0R3_EL1, 0x18c8e0, SR_READ | SR_WRITE},
|
||||
{"ICC_AP1R0_EL1", REG_ICC_AP1R0_EL1, 0x18c900, SR_READ | SR_WRITE},
|
||||
{"ICC_AP1R1_EL1", REG_ICC_AP1R1_EL1, 0x18c920, SR_READ | SR_WRITE},
|
||||
{"ICC_AP1R2_EL1", REG_ICC_AP1R2_EL1, 0x18c940, SR_READ | SR_WRITE},
|
||||
{"ICC_AP1R3_EL1", REG_ICC_AP1R3_EL1, 0x18c960, SR_READ | SR_WRITE},
|
||||
{"ICC_ASGI1R_EL1", REG_ICC_ASGI1R_EL1, 0x18cbc0, SR_WRITE},
|
||||
{"ICC_BPR0_EL1", REG_ICC_BPR0_EL1, 0x18c860, SR_READ | SR_WRITE},
|
||||
{"ICC_BPR1_EL1", REG_ICC_BPR1_EL1, 0x18cc60, SR_READ | SR_WRITE},
|
||||
{"ICC_CTLR_EL1", REG_ICC_CTLR_EL1, 0x18cc80, SR_READ | SR_WRITE},
|
||||
{"ICC_DIR_EL1", REG_ICC_DIR_EL1, 0x18cb20, SR_WRITE},
|
||||
{"ICC_EOIR0_EL1", REG_ICC_EOIR0_EL1, 0x18c820, SR_WRITE},
|
||||
{"ICC_EOIR1_EL1", REG_ICC_EOIR1_EL1, 0x18cc20, SR_WRITE},
|
||||
{"ICC_HPPIR0_EL1", REG_ICC_HPPIR0_EL1, 0x18c840, SR_READ},
|
||||
{"ICC_HPPIR1_EL1", REG_ICC_HPPIR1_EL1, 0x18cc40, SR_READ},
|
||||
{"ICC_IAR0_EL1", REG_ICC_IAR0_EL1, 0x18c800, SR_READ},
|
||||
{"ICC_IAR1_EL1", REG_ICC_IAR1_EL1, 0x18cc00, SR_READ},
|
||||
{"ICC_IGRPEN0_EL1", REG_ICC_IGRPEN0_EL1, 0x18ccc0, SR_READ | SR_WRITE},
|
||||
{"ICC_IGRPEN1_EL1", REG_ICC_IGRPEN1_EL1, 0x18cce0, SR_READ | SR_WRITE},
|
||||
{"ICC_PMR_EL1", REG_ICC_PMR_EL1, 0x184600, SR_READ | SR_WRITE},
|
||||
{"ICC_RPR_EL1", REG_ICC_RPR_EL1, 0x18cb60, SR_READ},
|
||||
{"ICC_SGI0R_EL1", REG_ICC_SGI0R_EL1, 0x18cbe0, SR_WRITE},
|
||||
{"ICC_SGI1R_EL1", REG_ICC_SGI1R_EL1, 0x18cba0, SR_WRITE},
|
||||
{"ICC_SRE_EL1", REG_ICC_SRE_EL1, 0x18cca0, SR_READ | SR_WRITE},
|
||||
{"ICV_AP0R0_EL1", REG_ICV_AP0R0_EL1, 0x18c880, SR_READ | SR_WRITE},
|
||||
{"ICV_AP0R1_EL1", REG_ICV_AP0R1_EL1, 0x18c8a0, SR_READ | SR_WRITE},
|
||||
{"ICV_AP0R2_EL1", REG_ICV_AP0R2_EL1, 0x18c8c0, SR_READ | SR_WRITE},
|
||||
{"ICV_AP0R3_EL1", REG_ICV_AP0R3_EL1, 0x18c8e0, SR_READ | SR_WRITE},
|
||||
{"ICV_AP1R0_EL1", REG_ICV_AP1R0_EL1, 0x18c900, SR_READ | SR_WRITE},
|
||||
{"ICV_AP1R1_EL1", REG_ICV_AP1R1_EL1, 0x18c920, SR_READ | SR_WRITE},
|
||||
{"ICV_AP1R2_EL1", REG_ICV_AP1R2_EL1, 0x18c940, SR_READ | SR_WRITE},
|
||||
{"ICV_AP1R3_EL1", REG_ICV_AP1R3_EL1, 0x18c960, SR_READ | SR_WRITE},
|
||||
{"ICV_BPR0_EL1", REG_ICV_BPR0_EL1, 0x18c860, SR_READ | SR_WRITE},
|
||||
{"ICV_BPR1_EL1", REG_ICV_BPR1_EL1, 0x18cc60, SR_READ | SR_WRITE},
|
||||
{"ICV_CTLR_EL1", REG_ICV_CTLR_EL1, 0x18cc80, SR_READ | SR_WRITE},
|
||||
{"ICV_DIR_EL1", REG_ICV_DIR_EL1, 0x18cb20, SR_WRITE},
|
||||
{"ICV_EOIR0_EL1", REG_ICV_EOIR0_EL1, 0x18c820, SR_WRITE},
|
||||
{"ICV_EOIR1_EL1", REG_ICV_EOIR1_EL1, 0x18cc20, SR_WRITE},
|
||||
{"ICV_HPPIR0_EL1", REG_ICV_HPPIR0_EL1, 0x18c840, SR_READ},
|
||||
{"ICV_HPPIR1_EL1", REG_ICV_HPPIR1_EL1, 0x18cc40, SR_READ},
|
||||
{"ICV_IAR0_EL1", REG_ICV_IAR0_EL1, 0x18c800, SR_READ},
|
||||
{"ICV_IAR1_EL1", REG_ICV_IAR1_EL1, 0x18cc00, SR_READ},
|
||||
{"ICV_IGRPEN0_EL1", REG_ICV_IGRPEN0_EL1, 0x18ccc0, SR_READ | SR_WRITE},
|
||||
{"ICV_IGRPEN1_EL1", REG_ICV_IGRPEN1_EL1, 0x18cce0, SR_READ | SR_WRITE},
|
||||
{"ICV_PMR_EL1", REG_ICV_PMR_EL1, 0x184600, SR_READ | SR_WRITE},
|
||||
{"ICV_RPR_EL1", REG_ICV_RPR_EL1, 0x18cb60, SR_READ},
|
||||
{"ID_AA64AFR0_EL1", REG_ID_AA64AFR0_EL1, 0x180580, SR_READ},
|
||||
{"ID_AA64AFR1_EL1", REG_ID_AA64AFR1_EL1, 0x1805a0, SR_READ},
|
||||
{"ID_AA64DFR0_EL1", REG_ID_AA64DFR0_EL1, 0x180500, SR_READ},
|
||||
{"ID_AA64DFR1_EL1", REG_ID_AA64DFR1_EL1, 0x180520, SR_READ},
|
||||
{"ID_AA64ISAR0_EL1", REG_ID_AA64ISAR0_EL1, 0x180600, SR_READ},
|
||||
{"ID_AA64ISAR1_EL1", REG_ID_AA64ISAR1_EL1, 0x180620, SR_READ},
|
||||
{"ID_AA64MMFR0_EL1", REG_ID_AA64MMFR0_EL1, 0x180700, SR_READ},
|
||||
{"ID_AA64MMFR1_EL1", REG_ID_AA64MMFR1_EL1, 0x180720, SR_READ},
|
||||
{"ID_AA64MMFR2_EL1", REG_ID_AA64MMFR2_EL1, 0x180740, SR_READ},
|
||||
{"ID_AA64PFR0_EL1", REG_ID_AA64PFR0_EL1, 0x180400, SR_READ},
|
||||
{"ID_AA64PFR1_EL1", REG_ID_AA64PFR1_EL1, 0x180420, SR_READ},
|
||||
{"ID_AA64ZFR0_EL1", REG_ID_AA64ZFR0_EL1, 0x180480, SR_READ},
|
||||
{"ID_AFR0_EL1", REG_ID_AFR0_EL1, 0x180160, SR_READ},
|
||||
{"ID_DFR0_EL1", REG_ID_DFR0_EL1, 0x180140, SR_READ},
|
||||
{"ID_ISAR0_EL1", REG_ID_ISAR0_EL1, 0x180200, SR_READ},
|
||||
{"ID_ISAR1_EL1", REG_ID_ISAR1_EL1, 0x180220, SR_READ},
|
||||
{"ID_ISAR2_EL1", REG_ID_ISAR2_EL1, 0x180240, SR_READ},
|
||||
{"ID_ISAR3_EL1", REG_ID_ISAR3_EL1, 0x180260, SR_READ},
|
||||
{"ID_ISAR4_EL1", REG_ID_ISAR4_EL1, 0x180280, SR_READ},
|
||||
{"ID_ISAR5_EL1", REG_ID_ISAR5_EL1, 0x1802a0, SR_READ},
|
||||
{"ID_ISAR6_EL1", REG_ID_ISAR6_EL1, 0x1802e0, SR_READ},
|
||||
{"ID_MMFR0_EL1", REG_ID_MMFR0_EL1, 0x180180, SR_READ},
|
||||
{"ID_MMFR1_EL1", REG_ID_MMFR1_EL1, 0x1801a0, SR_READ},
|
||||
{"ID_MMFR2_EL1", REG_ID_MMFR2_EL1, 0x1801c0, SR_READ},
|
||||
{"ID_MMFR3_EL1", REG_ID_MMFR3_EL1, 0x1801e0, SR_READ},
|
||||
{"ID_MMFR4_EL1", REG_ID_MMFR4_EL1, 0x1802c0, SR_READ},
|
||||
{"ID_PFR0_EL1", REG_ID_PFR0_EL1, 0x180100, SR_READ},
|
||||
{"ID_PFR1_EL1", REG_ID_PFR1_EL1, 0x180120, SR_READ},
|
||||
{"ID_PFR2_EL1", REG_ID_PFR2_EL1, 0x180380, SR_READ},
|
||||
{"ISR_EL1", REG_ISR_EL1, 0x18c100, SR_READ},
|
||||
{"LORC_EL1", REG_LORC_EL1, 0x18a460, SR_READ | SR_WRITE},
|
||||
{"LOREA_EL1", REG_LOREA_EL1, 0x18a420, SR_READ | SR_WRITE},
|
||||
{"LORID_EL1", REG_LORID_EL1, 0x18a4e0, SR_READ},
|
||||
{"LORN_EL1", REG_LORN_EL1, 0x18a440, SR_READ | SR_WRITE},
|
||||
{"LORSA_EL1", REG_LORSA_EL1, 0x18a400, SR_READ | SR_WRITE},
|
||||
{"MAIR_EL1", REG_MAIR_EL1, 0x18a200, SR_READ | SR_WRITE},
|
||||
{"MDCCINT_EL1", REG_MDCCINT_EL1, 0x100200, SR_READ | SR_WRITE},
|
||||
{"MDCCSR_EL0", REG_MDCCSR_EL0, 0x130100, SR_READ},
|
||||
{"MDRAR_EL1", REG_MDRAR_EL1, 0x101000, SR_READ},
|
||||
{"MDSCR_EL1", REG_MDSCR_EL1, 0x100240, SR_READ | SR_WRITE},
|
||||
{"MIDR_EL1", REG_MIDR_EL1, 0x180000, SR_READ},
|
||||
{"MPAM0_EL1", REG_MPAM0_EL1, 0x18a520, SR_READ | SR_WRITE},
|
||||
{"MPAM1_EL1", REG_MPAM1_EL1, 0x18a500, SR_READ | SR_WRITE},
|
||||
{"MPAMIDR_EL1", REG_MPAMIDR_EL1, 0x18a480, SR_READ},
|
||||
{"MPIDR_EL1", REG_MPIDR_EL1, 0x1800a0, SR_READ},
|
||||
{"MVFR0_EL1", REG_MVFR0_EL1, 0x180300, SR_READ},
|
||||
{"MVFR1_EL1", REG_MVFR1_EL1, 0x180320, SR_READ},
|
||||
{"MVFR2_EL1", REG_MVFR2_EL1, 0x180340, SR_READ},
|
||||
{"NZCV", REG_NZCV, 0x1b4200, SR_READ | SR_WRITE},
|
||||
{"OSDLR_EL1", REG_OSDLR_EL1, 0x101380, SR_READ | SR_WRITE},
|
||||
{"OSDTRRX_EL1", REG_OSDTRRX_EL1, 0x100040, SR_READ | SR_WRITE},
|
||||
{"OSDTRTX_EL1", REG_OSDTRTX_EL1, 0x100340, SR_READ | SR_WRITE},
|
||||
{"OSECCR_EL1", REG_OSECCR_EL1, 0x100640, SR_READ | SR_WRITE},
|
||||
{"OSLAR_EL1", REG_OSLAR_EL1, 0x101080, SR_WRITE},
|
||||
{"OSLSR_EL1", REG_OSLSR_EL1, 0x101180, SR_READ},
|
||||
{"PAN", REG_PAN, 0x184260, SR_READ | SR_WRITE},
|
||||
{"PAR_EL1", REG_PAR_EL1, 0x187400, SR_READ | SR_WRITE},
|
||||
{"PMBIDR_EL1", REG_PMBIDR_EL1, 0x189ae0, SR_READ},
|
||||
{"PMBLIMITR_EL1", REG_PMBLIMITR_EL1, 0x189a00, SR_READ | SR_WRITE},
|
||||
{"PMBPTR_EL1", REG_PMBPTR_EL1, 0x189a20, SR_READ | SR_WRITE},
|
||||
{"PMBSR_EL1", REG_PMBSR_EL1, 0x189a60, SR_READ | SR_WRITE},
|
||||
{"PMCCFILTR_EL0", REG_PMCCFILTR_EL0, 0x1befe0, SR_READ | SR_WRITE},
|
||||
{"PMCCNTR_EL0", REG_PMCCNTR_EL0, 0x1b9d00, SR_READ | SR_WRITE},
|
||||
{"PMCEID0_EL0", REG_PMCEID0_EL0, 0x1b9cc0, SR_READ},
|
||||
{"PMCEID1_EL0", REG_PMCEID1_EL0, 0x1b9ce0, SR_READ},
|
||||
{"PMCNTENCLR_EL0", REG_PMCNTENCLR_EL0, 0x1b9c40, SR_READ | SR_WRITE},
|
||||
{"PMCNTENSET_EL0", REG_PMCNTENSET_EL0, 0x1b9c20, SR_READ | SR_WRITE},
|
||||
{"PMCR_EL0", REG_PMCR_EL0, 0x1b9c00, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR0_EL0", REG_PMEVCNTR0_EL0, 0x1be800, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR1_EL0", REG_PMEVCNTR1_EL0, 0x1be820, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR2_EL0", REG_PMEVCNTR2_EL0, 0x1be840, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR3_EL0", REG_PMEVCNTR3_EL0, 0x1be860, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR4_EL0", REG_PMEVCNTR4_EL0, 0x1be880, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR5_EL0", REG_PMEVCNTR5_EL0, 0x1be8a0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR6_EL0", REG_PMEVCNTR6_EL0, 0x1be8c0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR7_EL0", REG_PMEVCNTR7_EL0, 0x1be8e0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR8_EL0", REG_PMEVCNTR8_EL0, 0x1be900, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR9_EL0", REG_PMEVCNTR9_EL0, 0x1be920, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR10_EL0", REG_PMEVCNTR10_EL0, 0x1be940, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR11_EL0", REG_PMEVCNTR11_EL0, 0x1be960, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR12_EL0", REG_PMEVCNTR12_EL0, 0x1be980, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR13_EL0", REG_PMEVCNTR13_EL0, 0x1be9a0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR14_EL0", REG_PMEVCNTR14_EL0, 0x1be9c0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR15_EL0", REG_PMEVCNTR15_EL0, 0x1be9e0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR16_EL0", REG_PMEVCNTR16_EL0, 0x1bea00, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR17_EL0", REG_PMEVCNTR17_EL0, 0x1bea20, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR18_EL0", REG_PMEVCNTR18_EL0, 0x1bea40, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR19_EL0", REG_PMEVCNTR19_EL0, 0x1bea60, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR20_EL0", REG_PMEVCNTR20_EL0, 0x1bea80, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR21_EL0", REG_PMEVCNTR21_EL0, 0x1beaa0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR22_EL0", REG_PMEVCNTR22_EL0, 0x1beac0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR23_EL0", REG_PMEVCNTR23_EL0, 0x1beae0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR24_EL0", REG_PMEVCNTR24_EL0, 0x1beb00, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR25_EL0", REG_PMEVCNTR25_EL0, 0x1beb20, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR26_EL0", REG_PMEVCNTR26_EL0, 0x1beb40, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR27_EL0", REG_PMEVCNTR27_EL0, 0x1beb60, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR28_EL0", REG_PMEVCNTR28_EL0, 0x1beb80, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR29_EL0", REG_PMEVCNTR29_EL0, 0x1beba0, SR_READ | SR_WRITE},
|
||||
{"PMEVCNTR30_EL0", REG_PMEVCNTR30_EL0, 0x1bebc0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER0_EL0", REG_PMEVTYPER0_EL0, 0x1bec00, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER1_EL0", REG_PMEVTYPER1_EL0, 0x1bec20, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER2_EL0", REG_PMEVTYPER2_EL0, 0x1bec40, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER3_EL0", REG_PMEVTYPER3_EL0, 0x1bec60, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER4_EL0", REG_PMEVTYPER4_EL0, 0x1bec80, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER5_EL0", REG_PMEVTYPER5_EL0, 0x1beca0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER6_EL0", REG_PMEVTYPER6_EL0, 0x1becc0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER7_EL0", REG_PMEVTYPER7_EL0, 0x1bece0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER8_EL0", REG_PMEVTYPER8_EL0, 0x1bed00, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER9_EL0", REG_PMEVTYPER9_EL0, 0x1bed20, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER10_EL0", REG_PMEVTYPER10_EL0, 0x1bed40, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER11_EL0", REG_PMEVTYPER11_EL0, 0x1bed60, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER12_EL0", REG_PMEVTYPER12_EL0, 0x1bed80, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER13_EL0", REG_PMEVTYPER13_EL0, 0x1beda0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER14_EL0", REG_PMEVTYPER14_EL0, 0x1bedc0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER15_EL0", REG_PMEVTYPER15_EL0, 0x1bede0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER16_EL0", REG_PMEVTYPER16_EL0, 0x1bee00, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER17_EL0", REG_PMEVTYPER17_EL0, 0x1bee20, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER18_EL0", REG_PMEVTYPER18_EL0, 0x1bee40, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER19_EL0", REG_PMEVTYPER19_EL0, 0x1bee60, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER20_EL0", REG_PMEVTYPER20_EL0, 0x1bee80, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER21_EL0", REG_PMEVTYPER21_EL0, 0x1beea0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER22_EL0", REG_PMEVTYPER22_EL0, 0x1beec0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER23_EL0", REG_PMEVTYPER23_EL0, 0x1beee0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER24_EL0", REG_PMEVTYPER24_EL0, 0x1bef00, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER25_EL0", REG_PMEVTYPER25_EL0, 0x1bef20, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER26_EL0", REG_PMEVTYPER26_EL0, 0x1bef40, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER27_EL0", REG_PMEVTYPER27_EL0, 0x1bef60, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER28_EL0", REG_PMEVTYPER28_EL0, 0x1bef80, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER29_EL0", REG_PMEVTYPER29_EL0, 0x1befa0, SR_READ | SR_WRITE},
|
||||
{"PMEVTYPER30_EL0", REG_PMEVTYPER30_EL0, 0x1befc0, SR_READ | SR_WRITE},
|
||||
{"PMINTENCLR_EL1", REG_PMINTENCLR_EL1, 0x189e40, SR_READ | SR_WRITE},
|
||||
{"PMINTENSET_EL1", REG_PMINTENSET_EL1, 0x189e20, SR_READ | SR_WRITE},
|
||||
{"PMMIR_EL1", REG_PMMIR_EL1, 0x189ec0, SR_READ},
|
||||
{"PMOVSCLR_EL0", REG_PMOVSCLR_EL0, 0x1b9c60, SR_READ | SR_WRITE},
|
||||
{"PMOVSSET_EL0", REG_PMOVSSET_EL0, 0x1b9e60, SR_READ | SR_WRITE},
|
||||
{"PMSCR_EL1", REG_PMSCR_EL1, 0x189900, SR_READ | SR_WRITE},
|
||||
{"PMSELR_EL0", REG_PMSELR_EL0, 0x1b9ca0, SR_READ | SR_WRITE},
|
||||
{"PMSEVFR_EL1", REG_PMSEVFR_EL1, 0x1899a0, SR_READ | SR_WRITE},
|
||||
{"PMSFCR_EL1", REG_PMSFCR_EL1, 0x189980, SR_READ | SR_WRITE},
|
||||
{"PMSICR_EL1", REG_PMSICR_EL1, 0x189940, SR_READ | SR_WRITE},
|
||||
{"PMSIDR_EL1", REG_PMSIDR_EL1, 0x1899e0, SR_READ},
|
||||
{"PMSIRR_EL1", REG_PMSIRR_EL1, 0x189960, SR_READ | SR_WRITE},
|
||||
{"PMSLATFR_EL1", REG_PMSLATFR_EL1, 0x1899c0, SR_READ | SR_WRITE},
|
||||
{"PMSWINC_EL0", REG_PMSWINC_EL0, 0x1b9c80, SR_WRITE},
|
||||
{"PMUSERENR_EL0", REG_PMUSERENR_EL0, 0x1b9e00, SR_READ | SR_WRITE},
|
||||
{"PMXEVCNTR_EL0", REG_PMXEVCNTR_EL0, 0x1b9d40, SR_READ | SR_WRITE},
|
||||
{"PMXEVTYPER_EL0", REG_PMXEVTYPER_EL0, 0x1b9d20, SR_READ | SR_WRITE},
|
||||
{"REVIDR_EL1", REG_REVIDR_EL1, 0x1800c0, SR_READ},
|
||||
{"RGSR_EL1", REG_RGSR_EL1, 0x1810a0, SR_READ | SR_WRITE},
|
||||
{"RMR_EL1", REG_RMR_EL1, 0x18c040, SR_READ | SR_WRITE},
|
||||
{"RNDR", REG_RNDR, 0x1b2400, SR_READ},
|
||||
{"RNDRRS", REG_RNDRRS, 0x1b2420, SR_READ},
|
||||
{"RVBAR_EL1", REG_RVBAR_EL1, 0x18c020, SR_READ},
|
||||
{"SCTLR_EL1", REG_SCTLR_EL1, 0x181000, SR_READ | SR_WRITE},
|
||||
{"SCXTNUM_EL0", REG_SCXTNUM_EL0, 0x1bd0e0, SR_READ | SR_WRITE},
|
||||
{"SCXTNUM_EL1", REG_SCXTNUM_EL1, 0x18d0e0, SR_READ | SR_WRITE},
|
||||
{"SP_EL0", REG_SP_EL0, 0x184100, SR_READ | SR_WRITE},
|
||||
{"SP_EL1", REG_SP_EL1, 0x1c4100, SR_READ | SR_WRITE},
|
||||
{"SPSel", REG_SPSel, 0x184200, SR_READ | SR_WRITE},
|
||||
{"SPSR_abt", REG_SPSR_abt, 0x1c4320, SR_READ | SR_WRITE},
|
||||
{"SPSR_EL1", REG_SPSR_EL1, 0x184000, SR_READ | SR_WRITE},
|
||||
{"SPSR_fiq", REG_SPSR_fiq, 0x1c4360, SR_READ | SR_WRITE},
|
||||
{"SPSR_irq", REG_SPSR_irq, 0x1c4300, SR_READ | SR_WRITE},
|
||||
{"SPSR_und", REG_SPSR_und, 0x1c4340, SR_READ | SR_WRITE},
|
||||
{"SSBS", REG_SSBS, 0x1b42c0, SR_READ | SR_WRITE},
|
||||
{"TCO", REG_TCO, 0x1b42e0, SR_READ | SR_WRITE},
|
||||
{"TCR_EL1", REG_TCR_EL1, 0x182040, SR_READ | SR_WRITE},
|
||||
{"TFSR_EL1", REG_TFSR_EL1, 0x185600, SR_READ | SR_WRITE},
|
||||
{"TFSRE0_EL1", REG_TFSRE0_EL1, 0x185620, SR_READ | SR_WRITE},
|
||||
{"TPIDR_EL0", REG_TPIDR_EL0, 0x1bd040, SR_READ | SR_WRITE},
|
||||
{"TPIDR_EL1", REG_TPIDR_EL1, 0x18d080, SR_READ | SR_WRITE},
|
||||
{"TPIDRRO_EL0", REG_TPIDRRO_EL0, 0x1bd060, SR_READ | SR_WRITE},
|
||||
{"TRFCR_EL1", REG_TRFCR_EL1, 0x181220, SR_READ | SR_WRITE},
|
||||
{"TTBR0_EL1", REG_TTBR0_EL1, 0x182000, SR_READ | SR_WRITE},
|
||||
{"TTBR1_EL1", REG_TTBR1_EL1, 0x182020, SR_READ | SR_WRITE},
|
||||
{"UAO", REG_UAO, 0x184280, SR_READ | SR_WRITE},
|
||||
{"VBAR_EL1", REG_VBAR_EL1, 0x18c000, SR_READ | SR_WRITE},
|
||||
{"ZCR_EL1", REG_ZCR_EL1, 0x181200, SR_READ | SR_WRITE},
|
||||
}
|
||||
|
||||
func SysRegEnc(r int16) (string, uint32, uint8) {
|
||||
// The automatic generator guarantees that the order
|
||||
// of Reg in SystemReg struct is consistent with the
|
||||
// order of system register declarations
|
||||
if r <= SYSREG_BEGIN || r >= SYSREG_END {
|
||||
return "", 0, 0
|
||||
}
|
||||
v := SystemReg[r-SYSREG_BEGIN-1]
|
||||
return v.Name, v.Enc, v.AccessFlags
|
||||
}
|
||||
Reference in New Issue
Block a user