1cfc2fea73
A new release of VDSP means syncing random updates to the libgloss headers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* cplb.h
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*
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* (c) Copyright 2002-2007 Analog Devices, Inc. All rights reserved.
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*
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************************************************************************/
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/* Defines necessary for cplb initialisation routines. */
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#ifndef _CPLB_H
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#define _CPLB_H
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#include <sys/platform.h>
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4)
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#endif /* _MISRA_RULES */
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
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#define CPLB_ENABLE_ICPLBS_P 4
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#define CPLB_ENABLE_DCPLBS_P 5
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#define CPLB_SET_DCBS_P 6
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#define CPLB_INVALIDATE_B_P 23
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/* ___cplb_ctrl bitmasks */
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#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
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#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
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#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
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#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
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#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
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#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
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#define CPLB_ENABLE_ANY_CPLBS \
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( CPLB_ENABLE_CPLBS | CPLB_ENABLE_ICPLBS | CPLB_ENABLE_DCPLBS )
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#define CPLB_SET_DCBS (1<<CPLB_SET_DCBS_P)
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/* Bitmasks for dcache_invalidate routine parameters */
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#define CPLB_INVALIDATE_A 0
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#define CPLB_INVALIDATE_B (1<<CPLB_INVALIDATE_B_P)
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/* _cplb_mgr return values */
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#define CPLB_RELOADED 0x0000
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#define CPLB_NO_UNLOCKED 0x0001
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#define CPLB_NO_ADDR_MATCH 0x0002
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#define CPLB_PROT_VIOL 0x0003
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#define CPLB_NO_ACTION 0x0004
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/* CPLB configurations */
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#define CPLB_DEF_CACHE_WT ( CPLB_L1_CHBL | CPLB_WT )
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#define CPLB_DEF_CACHE_WB ( CPLB_L1_CHBL )
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#define CPLB_CACHE_ENABLED ( CPLB_L1_CHBL | CPLB_DIRTY )
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#define CPLB_DEF_CACHE ( CPLB_L1_CHBL | CPLB_WT )
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#define CPLB_ALL_ACCESS ( CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR )
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#define CPLB_I_PAGE_MGMT ( CPLB_LOCK | CPLB_VALID )
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#define CPLB_D_PAGE_MGMT ( CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID )
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#define CPLB_DNOCACHE ( CPLB_ALL_ACCESS | CPLB_VALID )
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#define CPLB_DDOCACHE ( CPLB_DNOCACHE | CPLB_DEF_CACHE )
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#define CPLB_INOCACHE ( CPLB_USER_RD | CPLB_VALID )
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#define CPLB_IDOCACHE ( CPLB_INOCACHE | CPLB_L1_CHBL )
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#define CPLB_DDOCACHE_WT ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WT )
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#define CPLB_DDOCACHE_WB ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WB )
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/* Event type parameter for replacement manager _cplb_mgr */
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#define CPLB_EVT_ICPLB_MISS 0
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#define CPLB_EVT_DCPLB_MISS 1
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#define CPLB_EVT_DCPLB_WRITE 2
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/* size of cplb tables */
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#define __CPLB_TABLE_SIZE 16
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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#endif /* _MISRA_RULES */
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#endif /* _CPLB_H */
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