cdf81c0c4c
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64/Makefile.in: New file.
* aarch64/_exit.c: New file.
* aarch64/_kill.c: New file.
* aarch64/aclocal.m4: Generated.
* aarch64/configure: Generated.
* aarch64/configure.in: New file.
* aarch64/cpu-init/Makefile.in: New file.
* aarch64/cpu-init/rdimon-aem-el3.S: New file.
* aarch64/crt0.S: New file.
* aarch64/elf-rdimon.specs: New file.
* aarch64/libcfunc.c: New file.
* aarch64/svc.h: New file.
* aarch64/syscalls.c: New file.
* configure.in: Add AArch64.
* configure: Re-generated.
76 lines
3.0 KiB
C
76 lines
3.0 KiB
C
/* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. The name of the company may not be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* Now the SWI numbers and reason codes for RDI (Angel) monitors. */
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#define AngelSVC 0xF000
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#define AngelSVCInsn "hlt"
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#define AngelSVCAsm hlt
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/* The reason codes: */
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#define AngelSVC_Reason_Open 0x01
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#define AngelSVC_Reason_Close 0x02
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#define AngelSVC_Reason_WriteC 0x03
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#define AngelSVC_Reason_Write0 0x04
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#define AngelSVC_Reason_Write 0x05
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#define AngelSVC_Reason_Read 0x06
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#define AngelSVC_Reason_ReadC 0x07
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#define AngelSVC_Reason_IsTTY 0x09
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#define AngelSVC_Reason_Seek 0x0A
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#define AngelSVC_Reason_FLen 0x0C
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#define AngelSVC_Reason_TmpNam 0x0D
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#define AngelSVC_Reason_Remove 0x0E
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#define AngelSVC_Reason_Rename 0x0F
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#define AngelSVC_Reason_Clock 0x10
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#define AngelSVC_Reason_Time 0x11
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#define AngelSVC_Reason_System 0x12
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#define AngelSVC_Reason_Errno 0x13
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#define AngelSVC_Reason_GetCmdLine 0x15
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#define AngelSVC_Reason_HeapInfo 0x16
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#define AngelSVC_Reason_EnterSVC 0x17
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#define AngelSVC_Reason_ReportException 0x18
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#define AngelSVC_Reason_SyncCacheRange 0x19
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#define AngelSVC_Reason_Elapsed 0x30
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#define ADP_Stopped_ApplicationExit ((2 << 16) + 38)
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#define ADP_Stopped_RunTimeError ((2 << 16) + 35)
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#if defined(ARM_RDI_MONITOR) && !defined(__ASSEMBLER__)
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/* Type of each entry in a parameter block. */
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typedef long long param_block_t;
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static inline long long
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do_AngelSVC (int reason, param_block_t * arg)
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{
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long long value;
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asm volatile ("mov w0, %w1; mov x1, %2; " AngelSVCInsn " %3; mov %0, x0"
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: "=r" (value) /* Outputs */
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: "r" (reason), "r" (arg), "n" (AngelSVC) /* Inputs */
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: "x0", "x1", "x2", "x3", "x17", "x30", "memory", "cc"
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/* Clobbers x0 and x1, and lr if in supervisor mode */);
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return value;
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}
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#endif
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