f115039df1
* tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
719 lines
24 KiB
C
719 lines
24 KiB
C
/* TI C6X opcode information.
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Copyright 2010-2013 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef OPCODE_TIC6X_H
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#define OPCODE_TIC6X_H
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#include "bfd.h"
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#include "symcat.h"
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/* A field in an instruction format. The names are based on those
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used in the architecture manuals. */
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typedef enum
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{
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tic6x_field_baseR,
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tic6x_field_cc,
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tic6x_field_creg,
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tic6x_field_cst,
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tic6x_field_csta,
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tic6x_field_cstb,
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tic6x_field_dst,
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tic6x_field_dstms,
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tic6x_field_dw,
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tic6x_field_fstgfcyc,
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tic6x_field_h,
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tic6x_field_ii,
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tic6x_field_mask,
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tic6x_field_mode,
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tic6x_field_n,
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tic6x_field_na,
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tic6x_field_offsetR,
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tic6x_field_op,
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tic6x_field_p,
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tic6x_field_ptr,
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tic6x_field_r,
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tic6x_field_s,
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tic6x_field_sc,
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tic6x_field_src,
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tic6x_field_src1,
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tic6x_field_src2,
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tic6x_field_srcdst,
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tic6x_field_srcms,
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tic6x_field_sn,
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tic6x_field_sz,
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tic6x_field_unit,
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tic6x_field_t,
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tic6x_field_x,
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tic6x_field_y,
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tic6x_field_z
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} tic6x_insn_field_id;
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typedef struct
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{
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/* The least-significant bit position in the field. */
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unsigned short low_pos;
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/* The number of bits in the field. */
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unsigned short width;
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/* The position of the bitfield in the field. */
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unsigned short pos;
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} tic6x_bitfield;
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/* Maximum number of subfields in composite field. */
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#define TIC6X_MAX_BITFIELDS 4
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typedef struct
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{
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/* The name used to reference the field. */
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tic6x_insn_field_id field_id;
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unsigned int num_bitfields;
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tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
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} tic6x_insn_field;
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/* Maximum number of variable fields in an instruction format. */
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#define TIC6X_MAX_INSN_FIELDS 11
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/* A particular instruction format. */
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typedef struct
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{
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/* How many bits in the instruction. */
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unsigned int num_bits;
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/* Constant bits in the instruction. */
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unsigned int cst_bits;
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/* Mask matching those bits. */
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unsigned int mask;
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/* The number of instruction fields. */
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unsigned int num_fields;
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/* Descriptions of instruction fields. */
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tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
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} tic6x_insn_format;
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/* An index into the table of instruction formats. */
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typedef enum
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{
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#define FMT(name, num_bits, cst_bits, mask, fields) \
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CONCAT2(tic6x_insn_format_, name),
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#include "tic6x-insn-formats.h"
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#undef FMT
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tic6x_insn_format_max
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} tic6x_insn_format_id;
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/* The table itself. */
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extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
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/* If instruction format FMT has a field FIELD, return a pointer to
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the description of that field; otherwise return NULL. */
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const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
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tic6x_insn_field_id field);
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/* Description of a field (in an instruction format) whose value is
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fixed, or constrained to be in a particular range, in a particular
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opcode. */
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typedef struct
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{
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/* The name of the field. */
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tic6x_insn_field_id field_id;
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/* The least value of the field in this instruction. */
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unsigned int min_val;
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/* The greatest value of the field in this instruction. */
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unsigned int max_val;
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} tic6x_fixed_field;
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/* Pseudo opcode fields position for compact instructions
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If 16 bits instruction detected, the opcode is enriched
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[DSZ/3][BR][SAT][opcode] */
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#define TIC6X_COMPACT_SAT_POS 16
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#define TIC6X_COMPACT_BR_POS 17
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#define TIC6X_COMPACT_DSZ_POS 18
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/* Bit-masks for defining instructions present on some subset of
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processors; each indicates an instruction present on that processor
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and those that are supersets of it. The options passed to the
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assembler determine a bit-mask ANDed with the bit-mask indicating
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when the instruction was added to determine whether the instruction
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is enabled. */
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#define TIC6X_INSN_C62X 0x0001
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#define TIC6X_INSN_C64X 0x0002
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#define TIC6X_INSN_C64XP 0x0004
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#define TIC6X_INSN_C67X 0x0008
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#define TIC6X_INSN_C67XP 0x0010
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#define TIC6X_INSN_C674X 0x0020
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/* Flags with further information about an opcode table entry. */
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/* Only used by the assembler, not the disassembler. */
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#define TIC6X_FLAG_MACRO 0x0001
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/* Must be first in its execute packet. */
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#define TIC6X_FLAG_FIRST 0x0002
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/* Multi-cycle NOP (not used for the NOP n instruction itself, which
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is only a multicycle NOP if n > 1). */
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#define TIC6X_FLAG_MCNOP 0x0004
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/* Cannot be in parallel with a multi-cycle NOP. */
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#define TIC6X_FLAG_NO_MCNOP 0x0008
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/* Load instruction. */
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#define TIC6X_FLAG_LOAD 0x0010
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/* Store instruction. */
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#define TIC6X_FLAG_STORE 0x0020
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/* Unaligned memory operation. */
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#define TIC6X_FLAG_UNALIGNED 0x0040
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/* Only on side B. */
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#define TIC6X_FLAG_SIDE_B_ONLY 0x0080
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/* Only on data path T2. */
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#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100
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/* Does not support cross paths. */
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#define TIC6X_FLAG_NO_CROSS 0x0200
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/* Annotate this branch instruction as a call. */
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#define TIC6X_FLAG_CALL 0x0400
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/* Annotate this branch instruction as a return. */
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#define TIC6X_FLAG_RETURN 0x0800
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/* This instruction starts a software pipelined loop. */
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#define TIC6X_FLAG_SPLOOP 0x1000
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/* This instruction ends a software pipelined loop. */
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#define TIC6X_FLAG_SPKERNEL 0x2000
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/* This instruction takes a list of functional units as parameters;
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although described as having one parameter, the number may be 0 to
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8. */
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#define TIC6X_FLAG_SPMASK 0x4000
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/* When more than one opcode matches the assembly source, prefer the
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one with the highest value for this bit-field. If two opcode table
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entries can match the same syntactic form, they must have different
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values here. */
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#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
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#define TIC6X_FLAG_PREFER(n) ((n) << 15)
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/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
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#define TIC6X_FLAG_INSN16_SPRED 0x00100000
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/* 16 bits opcode ignores RS bit of fetch packet header */
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#define TIC6X_FLAG_INSN16_NORS 0x00200000
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/* 16 bits opcode only on side B */
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#define TIC6X_FLAG_INSN16_BSIDE 0x00400000
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/* 16 bits opcode ptr reg is b15 */
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#define TIC6X_FLAG_INSN16_B15PTR 0x00800000
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/* 16 bits opcode memory access modes */
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#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16)
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#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
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#define TIC6X_MEM_MODE_NEGATIVE 0
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#define TIC6X_MEM_MODE_POSITIVE 1
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#define TIC6X_MEM_MODE_REG_NEGATIVE 4
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#define TIC6X_MEM_MODE_REG_POSITIVE 5
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#define TIC6X_MEM_MODE_PREDECR 8
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#define TIC6X_MEM_MODE_PREINCR 9
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#define TIC6X_MEM_MODE_POSTDECR 10
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#define TIC6X_MEM_MODE_POSTINCR 11
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#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
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#define TIC6X_NUM_PREFER 2
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/* Maximum number of fixed fields for a particular opcode. */
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#define TIC6X_MAX_FIXED_FIELDS 4
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/* Maximum number of operands in the opcode table for a particular
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opcode. */
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#define TIC6X_MAX_OPERANDS 4
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/* Maximum number of operands in the source code for a particular
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opcode (different from the number in the opcode table for SPMASK
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and SPMASKR). */
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#define TIC6X_MAX_SOURCE_OPERANDS 8
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/* Maximum number of variable fields for a particular opcode. */
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#define TIC6X_MAX_VAR_FIELDS 7
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/* Which functional units an opcode uses. This only describes the
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basic choice of D, L, M, S or no functional unit; other fields are
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used to describe further restrictions (instructions only operating
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on one side), use of cross paths and load/store instructions using
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one side for the address and the other side for the source or
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destination register. */
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typedef enum
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{
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tic6x_func_unit_d,
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tic6x_func_unit_l,
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tic6x_func_unit_m,
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tic6x_func_unit_s,
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tic6x_func_unit_nfu
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} tic6x_func_unit_base;
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/* Possible forms of source operand. */
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typedef enum
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{
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/* An assembly-time constant. */
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tic6x_operand_asm_const,
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/* A link-time constant. */
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tic6x_operand_link_const,
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/* A register, from the same side as the functional unit
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selected. */
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tic6x_operand_reg,
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/* A register, from the same side as the functional unit
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selected that ignore RS header bit */
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tic6x_operand_reg_nors,
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/* A register, from the b side */
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tic6x_operand_reg_bside,
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/* A register, from the b side and from the low register set */
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tic6x_operand_reg_bside_nors,
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/* A register, that is from the other side if a cross path is
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used. */
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tic6x_operand_xreg,
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/* A register, that is from the side of the data path
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selected. */
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tic6x_operand_dreg,
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/* An address register usable with 15-bit offsets (B14 or B15).
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This is from the same side as the functional unit if a cross
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path is not used, and the other side if a cross path is
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used. */
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tic6x_operand_areg,
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/* The B15 register */
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tic6x_operand_b15reg,
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/* A register coded as an offset from either A16 or B16 depending
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on the value of the t bit. */
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tic6x_operand_treg,
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/* A register (A0 or B0), from the same side as the
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functional unit selected. */
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tic6x_operand_zreg,
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/* A return address register (A3 or B3), from the same side as the
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functional unit selected. */
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tic6x_operand_retreg,
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/* A register pair, from the same side as the functional unit
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selected. */
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tic6x_operand_regpair,
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/* A register pair, that is from the other side if a cross path is
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used. */
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tic6x_operand_xregpair,
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/* A register pair, from the side of the data path selected. */
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tic6x_operand_dregpair,
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/* A register pair coded as an offset from either A16 or B16 depending
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on the value of the t bit. */
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tic6x_operand_tregpair,
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/* The literal string "irp" (case-insensitive). */
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tic6x_operand_irp,
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/* The literal string "nrp" (case-insensitive). */
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tic6x_operand_nrp,
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/* The literal string "ilc" (case-insensitive). */
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tic6x_operand_ilc,
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/* A control register. */
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tic6x_operand_ctrl,
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/* A memory reference (base and offset registers from the side of
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the functional unit selected), using either unsigned 5-bit
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constant or register offset, if any offset; register offsets
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cannot use unscaled () syntax. */
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tic6x_operand_mem_short,
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/* A memory reference (base and offset registers from the side of
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the functional unit selected), using either unsigned 5-bit
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constant or register offset, if any offset; register offsets
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can use unscaled () syntax (for LDNDW and STNDW). */
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tic6x_operand_mem_ndw,
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/* A memory reference using 15-bit link-time constant offset
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relative to B14 or B15. */
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tic6x_operand_mem_long,
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/* A memory reference that only dereferences a register with no
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further adjustments (*REG), that register being from the side
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of the functional unit selected. */
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tic6x_operand_mem_deref,
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/* A functional unit name or a list thereof (for SPMASK and
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SPMASKR). */
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tic6x_operand_func_unit,
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/* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
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instruction formats - spru732j.pdf Appendix F.4 */
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tic6x_operand_hw_const_minus_1,
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tic6x_operand_hw_const_0,
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tic6x_operand_hw_const_1,
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tic6x_operand_hw_const_5,
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tic6x_operand_hw_const_16,
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tic6x_operand_hw_const_24,
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tic6x_operand_hw_const_31
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} tic6x_operand_form;
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/* Whether something is, or can be, read or written. */
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typedef enum
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{
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tic6x_rw_none,
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tic6x_rw_read,
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tic6x_rw_write,
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tic6x_rw_read_write
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} tic6x_rw;
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/* Description of a source operand and how it is used. */
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typedef struct
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{
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/* The syntactic form of the operand. */
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tic6x_operand_form form;
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/* For non-constant operands, the size in bytes (1, 2, 4, 5 or
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8). Ignored for constant operands. */
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unsigned int size;
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/* Whether the operand is read, written or both. In addition to the
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operations described here, address registers are read on cycle 1
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regardless of when the memory operand is read or written, and may
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be modified as described by the addressing mode, and control
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registers may be implicitly read by some instructions. There are
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also some special cases not fully described by this
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structure.
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- For mpydp, the low part of src2 is read on cycles 1 and 3 but
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not 2, and the high part on cycles 2 and 4 but not 3.
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- The swap2 pseudo-operation maps to packlh2, reading the first
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operand of swap2 twice. */
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tic6x_rw rw;
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/* The first and last cycles (1 for E1, etc.) at which the operand,
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or the low part for two-register operands, is read or
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written. */
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unsigned short low_first;
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unsigned short low_last;
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/* Likewise, for the high part. */
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unsigned short high_first;
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unsigned short high_last;
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} tic6x_operand_info;
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/* Ways of converting an operand or functional unit specifier to a
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field value. */
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typedef enum
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{
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/* Store an unsigned assembly-time constant (which must fit) in
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the field. */
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tic6x_coding_ucst,
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/* Store a signed constant (which must fit) in the field. This
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may be used both for assembly-time constants and for link-time
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constants. */
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tic6x_coding_scst,
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/* Subtract one from an unsigned assembly-time constant (which
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must be strictly positive before the subtraction) and store the
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value (which must fit) in the field. */
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tic6x_coding_ucst_minus_one,
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/* Negate a signed assembly-time constant, and store the result of
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negation (which must fit) in the field. Used only for
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pseudo-operations. */
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tic6x_coding_scst_negate,
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/* Store an unsigned link-time constant, implicitly DP-relative
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and counting in bytes, in the field. For expression operands,
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assembly-time constants are encoded as-is. For memory
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reference operands, the offset is encoded as-is if [] syntax is
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used and shifted if () is used. */
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tic6x_coding_ulcst_dpr_byte,
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/* Store an unsigned link-time constant, implicitly DP-relative
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and counting in half-words, in the field. For expression
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operands, assembly-time constants are encoded as-is. For
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memory reference operands, the offset is encoded as-is if []
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syntax is used and shifted if () is used. */
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tic6x_coding_ulcst_dpr_half,
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|
/* Store an unsigned link-time constant, implicitly DP-relative
|
|
and counting in words, in the field. For expression operands,
|
|
assembly-time constants are encoded as-is. For memory
|
|
reference operands, the offset is encoded as-is if [] syntax is
|
|
used and shifted if () is used. */
|
|
tic6x_coding_ulcst_dpr_word,
|
|
/* Store the low 16 bits of a link-time constant in the field;
|
|
considered unsigned for disassembly. */
|
|
tic6x_coding_lcst_low16,
|
|
/* Store the high 16 bits of a link-time constant in the field;
|
|
considered unsigned for disassembly. */
|
|
tic6x_coding_lcst_high16,
|
|
/* Store a signed PC-relative value (address of label minus
|
|
address of fetch packet containing the current instruction,
|
|
counted in words) in the field. */
|
|
tic6x_coding_pcrel,
|
|
/* Likewise, but counting in half-words if in a header-based fetch
|
|
packet. */
|
|
tic6x_coding_pcrel_half,
|
|
/* Store an unsigned PC-relative value used in compact insn */
|
|
tic6x_coding_pcrel_half_unsigned,
|
|
/* Encode the register number (even number for a register pair) in
|
|
the field. When applied to a memory reference, encode the base
|
|
register. */
|
|
tic6x_coding_reg,
|
|
/* Encode the register-pair's lsb (even register) for instructions
|
|
that use src1 as port for loading lsb of double-precision
|
|
operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp). */
|
|
tic6x_coding_regpair_lsb,
|
|
/* Encode the register-pair's msb (odd register), see above. */
|
|
tic6x_coding_regpair_msb,
|
|
/* Store 0 for register B14, 1 for register B15. When applied to
|
|
a memory reference, encode the base register. */
|
|
tic6x_coding_areg,
|
|
/* Compact instruction offset base register */
|
|
tic6x_coding_reg_ptr,
|
|
/* Store the low part of a control register address. */
|
|
tic6x_coding_crlo,
|
|
/* Store the high part of a control register address. */
|
|
tic6x_coding_crhi,
|
|
/* Encode the even register number for a register pair, shifted
|
|
right by one bit. */
|
|
tic6x_coding_reg_shift,
|
|
/* Store either the offset register or the 5-bit unsigned offset
|
|
for a memory reference. If an offset uses the unscaled ()
|
|
form, which is only permitted with constants, it is scaled
|
|
according to the access size of the operand before being
|
|
stored. */
|
|
tic6x_coding_mem_offset,
|
|
/* Store either the offset register or the 5-bit unsigned offset
|
|
for a memory reference, but with no scaling applied to the
|
|
offset (for nonaligned doubleword operations). */
|
|
tic6x_coding_mem_offset_noscale,
|
|
/* Store the addressing mode for a memory reference. */
|
|
tic6x_coding_mem_mode,
|
|
/* Store whether a memory reference is scaled. */
|
|
tic6x_coding_scaled,
|
|
/* Store the stage in an SPKERNEL instruction in the upper part of
|
|
the field. */
|
|
tic6x_coding_fstg,
|
|
/* Store the cycle in an SPKERNEL instruction in the lower part of
|
|
the field. */
|
|
tic6x_coding_fcyc,
|
|
/* Store the mask bits for functional units in the field in an
|
|
SPMASK or SPMASKR instruction. */
|
|
tic6x_coding_spmask,
|
|
/* Store the number of a register that is unused, or minimally
|
|
used, in this execute packet. The number must be the same for
|
|
all uses of this coding in a single instruction, but may be
|
|
different for different instructions in the execute packet.
|
|
This is for the "zero" pseudo-operation. This is not safe when
|
|
reads may occur from instructions in previous execute packets;
|
|
in such cases the programmer or compiler should use explicit
|
|
"sub" instructions for those cases of "zero" that cannot be
|
|
implemented as "mvk" for the processor specified. */
|
|
tic6x_coding_reg_unused,
|
|
/* Store 1 if the functional unit used is on side B, 0 for side
|
|
A. */
|
|
tic6x_coding_fu,
|
|
/* Store 1 if the data path used (source register for store,
|
|
destination for load) is on side B, 0 for side A. */
|
|
tic6x_coding_data_fu,
|
|
/* Store 1 if the cross path is being used, 0 otherwise. */
|
|
tic6x_coding_xpath,
|
|
/* L3i constant coding */
|
|
tic6x_coding_scst_l3i,
|
|
/* S3i constant coding */
|
|
tic6x_coding_cst_s3i,
|
|
/* mem offset minus 1 */
|
|
tic6x_coding_mem_offset_minus_one,
|
|
/* non aligned mem offset minus 1 */
|
|
tic6x_coding_mem_offset_minus_one_noscale,
|
|
tic6x_coding_rside
|
|
} tic6x_coding_method;
|
|
|
|
/* How to generate the value of a particular field. */
|
|
typedef struct
|
|
{
|
|
/* The name of the field. */
|
|
tic6x_insn_field_id field_id;
|
|
|
|
/* How it is encoded. */
|
|
tic6x_coding_method coding_method;
|
|
|
|
/* Source operand number, if any. */
|
|
unsigned int operand_num;
|
|
} tic6x_coding_field;
|
|
|
|
/* Types of instruction for pipeline purposes. The type determines
|
|
functional unit and cross path latency (when the same functional
|
|
unit can be used by other instructions, when the same cross path
|
|
can be used by other instructions). */
|
|
typedef enum
|
|
{
|
|
tic6x_pipeline_nop,
|
|
tic6x_pipeline_1cycle,
|
|
tic6x_pipeline_1616_m,
|
|
tic6x_pipeline_store,
|
|
tic6x_pipeline_mul_ext,
|
|
tic6x_pipeline_load,
|
|
tic6x_pipeline_branch,
|
|
tic6x_pipeline_2cycle_dp,
|
|
tic6x_pipeline_4cycle,
|
|
tic6x_pipeline_intdp,
|
|
tic6x_pipeline_dpcmp,
|
|
tic6x_pipeline_addsubdp,
|
|
tic6x_pipeline_mpyi,
|
|
tic6x_pipeline_mpyid,
|
|
tic6x_pipeline_mpydp,
|
|
tic6x_pipeline_mpyspdp,
|
|
tic6x_pipeline_mpysp2dp
|
|
} tic6x_pipeline_type;
|
|
|
|
/* Description of a control register. */
|
|
typedef struct
|
|
{
|
|
/* The name of the register. */
|
|
const char *name;
|
|
|
|
/* Which ISA variants include this control register. */
|
|
unsigned short isa_variants;
|
|
|
|
/* Whether it can be read, written or both (in supervisor mode).
|
|
Some registers use the same address, but different names, for
|
|
reading and writing. */
|
|
tic6x_rw rw;
|
|
|
|
/* crlo value for this register. */
|
|
unsigned int crlo;
|
|
|
|
/* Mask that, ANDed with the crhi value in the instruction, must be
|
|
0. 0 is always generated when generating code. */
|
|
unsigned int crhi_mask;
|
|
} tic6x_ctrl;
|
|
|
|
/* An index into the table of control registers. */
|
|
typedef enum
|
|
{
|
|
#define CTRL(name, isa, rw, crlo, crhi_mask) \
|
|
CONCAT2(tic6x_ctrl_,name),
|
|
#include "tic6x-control-registers.h"
|
|
#undef CTRL
|
|
tic6x_ctrl_max
|
|
} tic6x_ctrl_id;
|
|
|
|
/* The table itself. */
|
|
extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
|
|
|
|
/* An entry in the opcode table. */
|
|
typedef struct
|
|
{
|
|
/* The name of the instruction. */
|
|
const char *name;
|
|
|
|
/* Functional unit used by this instruction (basic information). */
|
|
tic6x_func_unit_base func_unit;
|
|
|
|
/* The format of this instruction. */
|
|
tic6x_insn_format_id format;
|
|
|
|
/* The pipeline type of this instruction. */
|
|
tic6x_pipeline_type type;
|
|
|
|
/* Which ISA variants include this instruction. */
|
|
unsigned short isa_variants;
|
|
|
|
/* Flags for this instruction. */
|
|
unsigned int flags;
|
|
|
|
/* Number of fixed fields, or fields with restricted value ranges,
|
|
for this instruction. */
|
|
unsigned int num_fixed_fields;
|
|
|
|
/* Values of fields fixed for this instruction. */
|
|
tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
|
|
|
|
/* The number of operands in the source form of this
|
|
instruction. */
|
|
unsigned int num_operands;
|
|
|
|
/* Information about individual operands. */
|
|
tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
|
|
|
|
/* The number of variable fields for this instruction with encoding
|
|
instructions explicitly given. */
|
|
unsigned int num_variable_fields;
|
|
|
|
/* How fields (other than ones with fixed value) are computed from
|
|
the source operands and functional unit specifiers. In addition
|
|
to fields specified here:
|
|
|
|
- creg, if present, is set from the predicate, along with z which
|
|
must be present if creg is present.
|
|
|
|
- p, if present (on all non-compact instructions), is set from
|
|
the parallel bars.
|
|
*/
|
|
tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
|
|
} tic6x_opcode;
|
|
|
|
/* An index into the table of opcodes. */
|
|
typedef enum
|
|
{
|
|
#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
|
|
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
|
|
#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
|
|
CONCAT4(tic6x_opcode_,name,_,e),
|
|
#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
|
|
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
|
|
#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
|
|
CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
|
|
#include "tic6x-opcode-table.h"
|
|
#undef INSN
|
|
#undef INSNE
|
|
#undef INSNU
|
|
#undef INSNUE
|
|
tic6x_opcode_max
|
|
} tic6x_opcode_id;
|
|
|
|
/* The table itself. */
|
|
extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
|
|
|
|
/* A linked list of opcodes. */
|
|
typedef struct tic6x_opcode_list_tag
|
|
{
|
|
tic6x_opcode_id id;
|
|
struct tic6x_opcode_list_tag *next;
|
|
} tic6x_opcode_list;
|
|
|
|
/* The information from a fetch packet header. */
|
|
typedef struct
|
|
{
|
|
/* The header itself. */
|
|
unsigned int header;
|
|
|
|
/* Whether each word uses compact instructions. */
|
|
bfd_boolean word_compact[7];
|
|
|
|
/* Whether loads are protected. */
|
|
bfd_boolean prot;
|
|
|
|
/* Whether instructions use the high register set. */
|
|
bfd_boolean rs;
|
|
|
|
/* Data size. */
|
|
unsigned int dsz;
|
|
|
|
/* Whether compact instructions in the S unit are decoded as
|
|
branches. */
|
|
bfd_boolean br;
|
|
|
|
/* Whether compact instructions saturate. */
|
|
bfd_boolean sat;
|
|
|
|
/* P-bits. */
|
|
bfd_boolean p_bits[14];
|
|
} tic6x_fetch_packet_header;
|
|
|
|
#endif /* OPCODE_TIC6X_H */
|