68a9101237
* or1k/Makefile.in: Add libor1k
* or1k/README: New file
* or1k/caches-asm.S: New file
* or1k/exceptions-asm.S: New file
* or1k/exceptions.c: New file
* or1k/impure.c: New file
* or1k/include/or1k-nop.h: New file
* or1k/include/or1k-support.h: New file
* or1k/interrupts-asm.S: New file
* or1k/interrupts.c: New file
* or1k/mmu-asm.S: New file
* or1k/or1k-internals.h: New file
* or1k/or1k_uart.c: New file
* or1k/or1k_uart.h: New file
* or1k/outbyte.S: New file
* or1k/sbrk.c: New file
* or1k/sync-asm.S: New file
* or1k/syscalls.c: New file
* or1k/timer.c: New file
* or1k/util.c: New file
68 lines
2.2 KiB
ArmAsm
68 lines
2.2 KiB
ArmAsm
/* mmu-asm.S -- MMU handling for OpenRISC 1000.
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*
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* Copyright (c) 2011, 2014 Authors
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*
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* Contributor Julius Baxter <juliusbaxter@gmail.com>
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* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* -------------------------------------------------------------------------- */
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/*!Function to control MMU
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*/
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/* -------------------------------------------------------------------------- */
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#include "include/or1k-asm.h"
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#include "include/or1k-sprs.h"
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/* MMU control functions always switch MMU control with a l.rfe to return
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from function */
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.section .text
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.global or1k_dmmu_enable
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or1k_dmmu_enable:
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l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r3,r3,OR1K_SPR_SYS_SR_DME_MASK
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l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
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l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
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OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
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.global or1k_dmmu_disable
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or1k_dmmu_disable:
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l.ori r3,r0,OR1K_SPR_SYS_SR_DME_MASK
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l.xori r4,r3,0xffff
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l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
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l.and r3,r4,r3
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l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
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l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
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OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
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.global or1k_immu_enable
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or1k_immu_enable:
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l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r3,r3,OR1K_SPR_SYS_SR_IME_MASK
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l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
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l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
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OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
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.global or1k_immu_disable
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or1k_immu_disable:
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l.ori r3,r0,OR1K_SPR_SYS_SR_IME_MASK
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l.xori r4,r3,0xffff
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l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
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l.and r3,r4,r3
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l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
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l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
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OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
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