09b64ed336
include/opcode/ * nios2.h (OP_MATCH_ERET): Correct eret encoding. gas/testsuite/ * gas/nios2/tret.d: Correct eret encoding.
523 lines
16 KiB
C
523 lines
16 KiB
C
/* Nios II opcode list for GAS, the GNU assembler.
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Copyright (C) 2012, 2013 Free Software Foundation, Inc.
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Contributed by Nigel Gray (ngray@altera.com).
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Contributed by Mentor Graphics, Inc.
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This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING3. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef _NIOS2_H_
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#define _NIOS2_H_
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#include "bfd.h"
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/****************************************************************************
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* This file contains structures, bit masks and shift counts used
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* by the GNU toolchain to define the Nios II instruction set and
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* access various opcode fields.
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****************************************************************************/
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/* Identify different overflow situations for error messages. */
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enum overflow_type
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{
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call_target_overflow = 0,
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branch_target_overflow,
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address_offset_overflow,
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signed_immed16_overflow,
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unsigned_immed16_overflow,
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unsigned_immed5_overflow,
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custom_opcode_overflow,
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no_overflow
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};
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/* This structure holds information for a particular instruction.
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The args field is a string describing the operands. The following
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letters can appear in the args:
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c - a 5-bit control register index
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d - a 5-bit destination register index
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s - a 5-bit left source register index
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t - a 5-bit right source register index
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i - a 16-bit signed immediate
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u - a 16-bit unsigned immediate
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o - a 16-bit signed program counter relative offset
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j - a 5-bit unsigned immediate
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b - a 5-bit break instruction constant
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l - a 8-bit custom instruction constant
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m - a 26-bit unsigned immediate
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Literal ',', '(', and ')' characters may also appear in the args as
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delimiters.
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The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
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of bits describing the instruction, notably any relevant hazard
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information.
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When assembling, the match field contains the opcode template, which
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is modified by the arguments to produce the actual opcode
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that is emitted. If pinfo is INSN_MACRO, then this is 0.
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If pinfo is INSN_MACRO, the mask field stores the macro identifier.
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Otherwise this is a bit mask for the relevant portions of the opcode
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when disassembling. If the actual opcode anded with the match field
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equals the opcode field, then we have found the correct instruction. */
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struct nios2_opcode
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{
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const char *name; /* The name of the instruction. */
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const char *args; /* A string describing the arguments for this
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instruction. */
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const char *args_test; /* Like args, but with an extra argument for
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the expected opcode. */
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unsigned long num_args; /* The number of arguments the instruction
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takes. */
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unsigned long match; /* The basic opcode for the instruction. */
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unsigned long mask; /* Mask for the opcode field of the
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instruction. */
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unsigned long pinfo; /* Is this a real instruction or instruction
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macro? */
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enum overflow_type overflow_msg; /* Used to generate informative
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message when fixup overflows. */
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};
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/* This value is used in the nios2_opcode.pinfo field to indicate that the
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instruction is a macro or pseudo-op. This requires special treatment by
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the assembler, and is used by the disassembler to determine whether to
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check for a nop. */
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#define NIOS2_INSN_MACRO 0x80000000
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#define NIOS2_INSN_MACRO_MOV 0x80000001
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#define NIOS2_INSN_MACRO_MOVI 0x80000002
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#define NIOS2_INSN_MACRO_MOVIA 0x80000004
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#define NIOS2_INSN_RELAXABLE 0x40000000
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#define NIOS2_INSN_UBRANCH 0x00000010
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#define NIOS2_INSN_CBRANCH 0x00000020
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#define NIOS2_INSN_CALL 0x00000040
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#define NIOS2_INSN_ADDI 0x00000080
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#define NIOS2_INSN_ANDI 0x00000100
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#define NIOS2_INSN_ORI 0x00000200
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#define NIOS2_INSN_XORI 0x00000400
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/* Associates a register name ($6) with a 5-bit index (eg 6). */
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struct nios2_reg
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{
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const char *name;
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const int index;
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};
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/* These are bit masks and shift counts for accessing the various
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fields of a Nios II instruction. */
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/* Macros for getting and setting an instruction field. */
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#define GET_INSN_FIELD(X, i) \
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(((i) & OP_MASK_##X) >> OP_SH_##X)
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#define SET_INSN_FIELD(X, i, j) \
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((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X)))
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/* Instruction field definitions. */
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#define IW_A_LSB 27
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#define IW_A_MSB 31
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#define IW_A_SZ 5
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#define IW_A_MASK 0x1f
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#define IW_B_LSB 22
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#define IW_B_MSB 26
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#define IW_B_SZ 5
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#define IW_B_MASK 0x1f
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#define IW_C_LSB 17
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#define IW_C_MSB 21
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#define IW_C_SZ 5
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#define IW_C_MASK 0x1f
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#define IW_IMM16_LSB 6
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#define IW_IMM16_MSB 21
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#define IW_IMM16_SZ 16
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#define IW_IMM16_MASK 0xffff
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#define IW_IMM26_LSB 6
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#define IW_IMM26_MSB 31
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#define IW_IMM26_SZ 26
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#define IW_IMM26_MASK 0x3ffffff
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#define IW_OP_LSB 0
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#define IW_OP_MSB 5
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#define IW_OP_SZ 6
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#define IW_OP_MASK 0x3f
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#define IW_OPX_LSB 11
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#define IW_OPX_MSB 16
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#define IW_OPX_SZ 6
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#define IW_OPX_MASK 0x3f
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#define IW_SHIFT_IMM5_LSB 6
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#define IW_SHIFT_IMM5_MSB 10
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#define IW_SHIFT_IMM5_SZ 5
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#define IW_SHIFT_IMM5_MASK 0x1f
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#define IW_CONTROL_REGNUM_LSB 6
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#define IW_CONTROL_REGNUM_MSB 9
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#define IW_CONTROL_REGNUM_SZ 4
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#define IW_CONTROL_REGNUM_MASK 0xf
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/* Operator mask and shift. */
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#define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB)
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#define OP_SH_OP IW_OP_LSB
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/* Masks and shifts for I-type instructions. */
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#define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB)
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#define OP_SH_IOP IW_OP_LSB
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#define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB)
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#define OP_SH_IMM16 IW_IMM16_LSB
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#define OP_MASK_IRD (IW_B_MASK << IW_B_LSB)
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#define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */
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#define OP_MASK_IRT (IW_B_MASK << IW_B_LSB)
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#define OP_SH_IRT IW_B_LSB
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#define OP_MASK_IRS (IW_A_MASK << IW_A_LSB)
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#define OP_SH_IRS IW_A_LSB
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/* Masks and shifts for R-type instructions. */
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#define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB)
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#define OP_SH_ROP IW_OP_LSB
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#define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB)
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#define OP_SH_ROPX IW_OPX_LSB
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#define OP_MASK_RRD (IW_C_MASK << IW_C_LSB)
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#define OP_SH_RRD IW_C_LSB
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#define OP_MASK_RRT (IW_B_MASK << IW_B_LSB)
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#define OP_SH_RRT IW_B_LSB
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#define OP_MASK_RRS (IW_A_MASK << IW_A_LSB)
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#define OP_SH_RRS IW_A_LSB
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/* Masks and shifts for J-type instructions. */
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#define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB)
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#define OP_SH_JOP IW_OP_LSB
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#define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB)
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#define OP_SH_IMM26 IW_IMM26_LSB
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/* Masks and shifts for CTL instructions. */
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#define OP_MASK_RCTL 0x000007c0
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#define OP_SH_RCTL 6
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/* Break instruction imm5 field. */
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#define OP_MASK_TRAP_IMM5 0x000007c0
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#define OP_SH_TRAP_IMM5 6
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/* Instruction imm5 field. */
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#define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB)
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#define OP_SH_IMM5 IW_SHIFT_IMM5_LSB
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/* Cache operation fields (type j,i(s)). */
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#define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB)
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#define OP_SH_CACHE_OPX IW_B_LSB
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#define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB)
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#define OP_SH_CACHE_RRS IW_A_LSB
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/* Custom instruction masks. */
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#define OP_MASK_CUSTOM_A 0x00010000
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#define OP_SH_CUSTOM_A 16
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#define OP_MASK_CUSTOM_B 0x00008000
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#define OP_SH_CUSTOM_B 15
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#define OP_MASK_CUSTOM_C 0x00004000
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#define OP_SH_CUSTOM_C 14
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#define OP_MASK_CUSTOM_N 0x00003fc0
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#define OP_SH_CUSTOM_N 6
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#define OP_MAX_CUSTOM_N 255
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/* OP instruction values. */
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#define OP_ADDI 4
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#define OP_ANDHI 44
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#define OP_ANDI 12
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#define OP_BEQ 38
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#define OP_BGE 14
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#define OP_BGEU 46
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#define OP_BLT 22
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#define OP_BLTU 54
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#define OP_BNE 30
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#define OP_BR 6
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#define OP_CALL 0
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#define OP_CMPEQI 32
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#define OP_CMPGEI 8
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#define OP_CMPGEUI 40
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#define OP_CMPLTI 16
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#define OP_CMPLTUI 48
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#define OP_CMPNEI 24
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#define OP_CUSTOM 50
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#define OP_FLUSHD 59
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#define OP_FLUSHDA 27
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#define OP_INITD 51
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#define OP_INITDA 19
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#define OP_JMPI 1
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#define OP_LDB 7
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#define OP_LDBIO 39
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#define OP_LDBU 3
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#define OP_LDBUIO 35
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#define OP_LDH 15
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#define OP_LDHIO 47
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#define OP_LDHU 11
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#define OP_LDHUIO 43
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#define OP_LDL 31
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#define OP_LDW 23
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#define OP_LDWIO 55
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#define OP_MULI 36
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#define OP_OPX 58
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#define OP_ORHI 52
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#define OP_ORI 20
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#define OP_RDPRS 56
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#define OP_STB 5
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#define OP_STBIO 37
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#define OP_STC 29
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#define OP_STH 13
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#define OP_STHIO 45
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#define OP_STW 21
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#define OP_STWIO 53
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#define OP_XORHI 60
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#define OP_XORI 28
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/* OPX instruction values. */
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#define OPX_ADD 49
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#define OPX_AND 14
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#define OPX_BREAK 52
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#define OPX_BRET 9
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#define OPX_CALLR 29
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#define OPX_CMPEQ 32
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#define OPX_CMPGE 8
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#define OPX_CMPGEU 40
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#define OPX_CMPLT 16
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#define OPX_CMPLTU 48
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#define OPX_CMPNE 24
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#define OPX_CRST 62
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#define OPX_DIV 37
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#define OPX_DIVU 36
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#define OPX_ERET 1
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#define OPX_FLUSHI 12
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#define OPX_FLUSHP 4
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#define OPX_HBREAK 53
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#define OPX_INITI 41
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#define OPX_INTR 61
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#define OPX_JMP 13
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#define OPX_MUL 39
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#define OPX_MULXSS 31
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#define OPX_MULXSU 23
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#define OPX_MULXUU 7
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#define OPX_NEXTPC 28
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#define OPX_NOR 6
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#define OPX_OR 22
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#define OPX_RDCTL 38
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#define OPX_RET 5
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#define OPX_ROL 3
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#define OPX_ROLI 2
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#define OPX_ROR 11
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#define OPX_SLL 19
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#define OPX_SLLI 18
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#define OPX_SRA 59
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#define OPX_SRAI 58
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#define OPX_SRL 27
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#define OPX_SRLI 26
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#define OPX_SUB 57
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#define OPX_SYNC 54
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#define OPX_TRAP 45
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#define OPX_WRCTL 46
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#define OPX_WRPRS 20
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#define OPX_XOR 30
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/* The following macros define the opcode matches for each
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instruction code & OP_MASK_INST == OP_MATCH_INST. */
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/* OP instruction matches. */
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#define OP_MATCH_ADDI OP_ADDI
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#define OP_MATCH_ANDHI OP_ANDHI
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#define OP_MATCH_ANDI OP_ANDI
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#define OP_MATCH_BEQ OP_BEQ
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#define OP_MATCH_BGE OP_BGE
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#define OP_MATCH_BGEU OP_BGEU
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#define OP_MATCH_BLT OP_BLT
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#define OP_MATCH_BLTU OP_BLTU
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#define OP_MATCH_BNE OP_BNE
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#define OP_MATCH_BR OP_BR
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#define OP_MATCH_FLUSHD OP_FLUSHD
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#define OP_MATCH_FLUSHDA OP_FLUSHDA
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#define OP_MATCH_INITD OP_INITD
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#define OP_MATCH_INITDA OP_INITDA
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#define OP_MATCH_CALL OP_CALL
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#define OP_MATCH_CMPEQI OP_CMPEQI
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#define OP_MATCH_CMPGEI OP_CMPGEI
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#define OP_MATCH_CMPGEUI OP_CMPGEUI
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#define OP_MATCH_CMPLTI OP_CMPLTI
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#define OP_MATCH_CMPLTUI OP_CMPLTUI
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#define OP_MATCH_CMPNEI OP_CMPNEI
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#define OP_MATCH_JMPI OP_JMPI
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#define OP_MATCH_LDB OP_LDB
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#define OP_MATCH_LDBIO OP_LDBIO
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#define OP_MATCH_LDBU OP_LDBU
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#define OP_MATCH_LDBUIO OP_LDBUIO
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#define OP_MATCH_LDH OP_LDH
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#define OP_MATCH_LDHIO OP_LDHIO
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#define OP_MATCH_LDHU OP_LDHU
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#define OP_MATCH_LDHUIO OP_LDHUIO
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#define OP_MATCH_LDL OP_LDL
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#define OP_MATCH_LDW OP_LDW
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#define OP_MATCH_LDWIO OP_LDWIO
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#define OP_MATCH_MULI OP_MULI
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#define OP_MATCH_OPX OP_OPX
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#define OP_MATCH_ORHI OP_ORHI
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#define OP_MATCH_ORI OP_ORI
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#define OP_MATCH_RDPRS OP_RDPRS
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#define OP_MATCH_STB OP_STB
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#define OP_MATCH_STBIO OP_STBIO
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#define OP_MATCH_STC OP_STC
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#define OP_MATCH_STH OP_STH
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#define OP_MATCH_STHIO OP_STHIO
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#define OP_MATCH_STW OP_STW
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#define OP_MATCH_STWIO OP_STWIO
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#define OP_MATCH_CUSTOM OP_CUSTOM
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#define OP_MATCH_XORHI OP_XORHI
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#define OP_MATCH_XORI OP_XORI
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#define OP_MATCH_OPX OP_OPX
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/* OPX instruction values. */
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#define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX)
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#define OP_MATCH_ADD OPX_MATCH (OPX_ADD)
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#define OP_MATCH_AND OPX_MATCH (OPX_AND)
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#define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK))
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#define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET))
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#define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR))
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#define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ)
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#define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE)
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#define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU)
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#define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT)
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#define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU)
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#define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE)
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#define OP_MATCH_DIV OPX_MATCH (OPX_DIV)
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#define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU)
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#define OP_MATCH_JMP OPX_MATCH (OPX_JMP)
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#define OP_MATCH_MUL OPX_MATCH (OPX_MUL)
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#define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS)
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#define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU)
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#define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU)
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#define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC)
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#define OP_MATCH_NOR OPX_MATCH (OPX_NOR)
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#define OP_MATCH_OR OPX_MATCH (OPX_OR)
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#define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL)
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#define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET))
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#define OP_MATCH_ROL OPX_MATCH (OPX_ROL)
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#define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI)
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#define OP_MATCH_ROR OPX_MATCH (OPX_ROR)
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#define OP_MATCH_SLL OPX_MATCH (OPX_SLL)
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#define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI)
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#define OP_MATCH_SRA OPX_MATCH (OPX_SRA)
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#define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI)
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#define OP_MATCH_SRL OPX_MATCH (OPX_SRL)
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#define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI)
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#define OP_MATCH_SUB OPX_MATCH (OPX_SUB)
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#define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC)
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#define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP))
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#define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET))
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#define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL)
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#define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS)
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#define OP_MATCH_XOR OPX_MATCH (OPX_XOR)
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#define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI)
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#define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP)
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#define OP_MATCH_INITI OPX_MATCH (OPX_INITI)
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/* Some unusual op masks. */
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#define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
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| OP_MASK_ROPX | OP_MASK_OP) \
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& 0xfffff03f)
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#define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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| OP_MASK_OP))
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#define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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| OP_MASK_OP))
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#define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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| OP_MASK_OP))
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#define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
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| OP_MASK_ROPX | OP_MASK_OP) \
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|
& 0xfffff83f)
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#define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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| OP_MASK_OP)) /*& 0xfffff83f */
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#define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
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| OP_MASK_OP))
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#define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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|
| OP_MASK_OP))
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#define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
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|
| OP_MASK_OP))
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|
|
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#define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
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#define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
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#define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
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#define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
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#define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
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|
| OP_MASK_OP)) /*& 0xfffff83f */
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|
|
|
#ifndef OP_MASK
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#define OP_MASK 0xffffffff
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|
#endif
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|
|
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/* These convenience macros to extract instruction fields are used by GDB. */
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|
#define GET_IW_A(Iw) \
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|
(((Iw) >> IW_A_LSB) & IW_A_MASK)
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|
#define GET_IW_B(Iw) \
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|
(((Iw) >> IW_B_LSB) & IW_B_MASK)
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|
#define GET_IW_C(Iw) \
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|
(((Iw) >> IW_C_LSB) & IW_C_MASK)
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|
#define GET_IW_CONTROL_REGNUM(Iw) \
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|
(((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK)
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|
#define GET_IW_IMM16(Iw) \
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|
(((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK)
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|
#define GET_IW_IMM26(Iw) \
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|
(((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK)
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|
#define GET_IW_OP(Iw) \
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|
(((Iw) >> IW_OP_LSB) & IW_OP_MASK)
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|
#define GET_IW_OPX(Iw) \
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|
(((Iw) >> IW_OPX_LSB) & IW_OPX_MASK)
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|
|
|
/* These are the data structures we use to hold the instruction information. */
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|
extern const struct nios2_opcode nios2_builtin_opcodes[];
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|
extern const int bfd_nios2_num_builtin_opcodes;
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|
extern struct nios2_opcode *nios2_opcodes;
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|
extern int bfd_nios2_num_opcodes;
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|
|
|
/* These are the data structures used to hold the register information. */
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|
extern const struct nios2_reg nios2_builtin_regs[];
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|
extern struct nios2_reg *nios2_regs;
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|
extern const int nios2_num_builtin_regs;
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|
extern int nios2_num_regs;
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|
|
|
/* Machine-independent macro for number of opcodes. */
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|
#define NUMOPCODES bfd_nios2_num_opcodes
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|
#define NUMREGISTERS nios2_num_regs;
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|
|
|
/* This is made extern so that the assembler can use it to find out
|
|
what instruction caused an error. */
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|
extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long);
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|
|
|
#endif /* _NIOS2_H */
|