ff7b7b8945
There was an issue revealed in gdb testing where C++ virtual tables were not getting properly initialized. This seems to be due to the c++ global constructors moving from ctors to init_array. This fix makes sure we call the proper method for initializing the constructors in all places.
678 lines
20 KiB
ArmAsm
678 lines
20 KiB
ArmAsm
/* crt0.S -- startup file for OpenRISC 1000.
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*
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* Copyright (c) 2011, 2014 Authors
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*
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* Contributor Julius Baxter <juliusbaxter@gmail.com>
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* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* -------------------------------------------------------------------------- */
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/* Coding convention:
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Assembly is hard to read per se, so please follow the following coding
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conventions to keep it consistent and ease reading:
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* internal jump labels start with L, no identation
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* assemble lines have one tab identation
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* attributes (.section, .global, ..) are indented with one tab
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* code is structured using tabs, i.e., use 'l.sw\t0(r1),r1' with a single
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tab. libgloss assumes 8 space tab width, so that might look unstructured
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with tab widths below 6. Nevertheless don't use spaces or two tabs.
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* no space after comma
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* use the defined macros if possible as they reduce errors
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* use OR1K_INST with OR1K_DELAYED(_NOP)
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* OR1K_DELAYED is multiline for better readability, the inner parts are
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indented with another tab.
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* COMMENT! Try to accompy every line with a meaningful comment. If possible
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use pseudo code to describe the code. Also mention intentions and not only
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the obvious things.. */
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/* -------------------------------------------------------------------------- */
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#include "newlib.h"
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#include "include/or1k-asm.h"
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#include "include/or1k-sprs.h"
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/* -------------------------------------------------------------------------- */
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// Stack definitions
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/* -------------------------------------------------------------------------- */
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// Stacks
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// Memory layout:
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// +--------------------+ <- board_mem_base+board_mem_size/exception_stack_top
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// | exception stack(s) |
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// +--------------------+ <- stack_top
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// | stack(s) |
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// +--------------------+ <- stack_bottom
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// | heap |
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// +--------------------+
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// | text, data, bss.. |
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// +--------------------+
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// Reserved stack size
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#define STACK_SIZE 8192
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// Reserved stack size for exceptions (can usually be smaller than normal stack)
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#define EXCEPTION_STACK_SIZE 8192
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// Size of space required to store state
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// This value must match that in the support library or1k_exception_handler
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// function
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#define EXCEPTION_STACK_FRAME 136
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#define REDZONE 128
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.extern _or1k_stack_top /* points to the next address after the stack */
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.extern _or1k_stack_bottom /* points to the last address in the stack */
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.extern _or1k_exception_stack_top
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.extern _or1k_exception_stack_bottom
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.extern _or1k_exception_level /* Nesting level of exceptions */
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.section .data
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.global _or1k_stack_size /* reserved stack size */
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.global _or1k_exception_stack_size
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.global _or1k_exception_level
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_or1k_stack_size: .word STACK_SIZE
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_or1k_exception_stack_size: .word EXCEPTION_STACK_SIZE
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#ifdef __OR1K_MULTICORE__
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.extern _or1k_stack_core
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.extern _or1k_exception_stack_core
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#endif
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#define SHADOW_REG(x) (OR1K_SPR_SYS_GPR_BASE + 32 + x)
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/* -------------------------------------------------------------------------- */
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/*!Macro to handle exceptions.
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Load NPC into r3, EPCR into r4
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*/
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/* -------------------------------------------------------------------------- */
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#ifdef HAVE_INITFINI_ARRAY
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#define _init __libc_init_array
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#define _fini __libc_fini_array
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#endif
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#define GPR_BUF_OFFSET(x) (x << 2)
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#ifndef __OR1K_MULTICORE__
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#define CALL_EXCEPTION_HANDLER(id) \
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/* Store current stack pointer to address 4 */ \
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l.sw 0x4(r0),r1; \
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/* Load address of exception nesting level */ \
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l.movhi r1,hi(_or1k_exception_level); \
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l.ori r1,r1,lo(_or1k_exception_level); \
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/* Load the current nesting level */ \
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l.lwz r1,0(r1); \
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/* Set flag if this is the outer (first) exception */ \
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l.sfeq r1,r0; \
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/* Branch to the code for nested exceptions */ \
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OR1K_DELAYED_NOP( \
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OR1K_INST(l.bnf .Lnested_##id) \
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); \
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/* Load top of the exception stack */ \
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l.movhi r1,hi(_or1k_exception_stack_top); \
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l.ori r1,r1,lo(_or1k_exception_stack_top); \
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OR1K_DELAYED( \
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/* Load value from array to stack pointer */ \
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OR1K_INST(l.lwz r1,0(r1)), \
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/* and jump over the nested code */ \
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OR1K_INST(l.j .Lnesting_done_##id) \
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); \
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.Lnested_##id: \
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/* Load back the stack pointer */ \
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l.lwz r1,0x4(r0); \
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/* Add redzone, nesting needs this */ \
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l.addi r1,r1,-REDZONE; \
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.Lnesting_done_##id: \
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/* Reserve red zone and context space */ \
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l.addi r1,r1,-EXCEPTION_STACK_FRAME; \
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/* Store GPR3 in context */ \
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l.sw GPR_BUF_OFFSET(3)(r1),r3; \
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/* Load back software's stack pointer */ \
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l.lwz r3,0x4(r0); \
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/* Store this in the context */ \
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l.sw GPR_BUF_OFFSET(1)(r1),r3; \
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/* Store GPR4 in the context */ \
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l.sw GPR_BUF_OFFSET(4)(r1),r4; \
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/* Load address of the exception level */ \
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l.movhi r3,hi(_or1k_exception_level); \
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l.ori r3,r3,lo(_or1k_exception_level); \
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/* Load current value */ \
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l.lwz r4,0(r3); \
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/* Increment level */ \
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l.addi r4,r4,1; \
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/* Store back */ \
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l.sw 0(r3),r4; \
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/* Copy the current program counter as first */ \
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/* argument for the exception handler. This */ \
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/* is then used to determine the exception. */ \
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l.mfspr r3,r0,OR1K_SPR_SYS_NPC_ADDR; \
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OR1K_DELAYED( \
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/* Copy program counter of exception as */ \
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/* second argument to the exception handler */ \
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OR1K_INST(l.mfspr r4,r0,OR1K_SPR_SYS_EPCR_BASE),\
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/* Jump to exception handler. This will rfe */ \
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OR1K_INST(l.j _or1k_exception_handler) \
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)
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#else
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#define CALL_EXCEPTION_HANDLER(id) \
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/* Store current stack pointer to shadow reg */ \
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l.mtspr r0,r1,SHADOW_REG(1); \
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/* Store current GPR3 for temporary use */ \
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l.mtspr r0,r3,SHADOW_REG(2); \
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/* Store current GPR2 for the level pointer */ \
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l.mtspr r0,r4,SHADOW_REG(3); \
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/* Load nesting level of exceptions */ \
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l.movhi r4,hi(_or1k_exception_level); \
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l.ori r4,r4,lo(_or1k_exception_level); \
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/* Load array pointer */ \
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l.lwz r4,0(r4); \
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/* Get core id */ \
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l.mfspr r3,r0,OR1K_SPR_SYS_COREID_ADDR; \
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/* Generate offset */ \
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l.slli r3,r3,2; \
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/* Generate core nesting level address */ \
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l.add r4,r4,r3; \
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/* Load nesting level */ \
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l.lwz r3,0(r4); \
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/* Increment nesting level */ \
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l.addi r3,r3,1; \
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/* Write back nesting level */ \
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l.sw 0(r4),r3; \
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/* Set flag if this is the outer (first) exception */ \
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l.sfeqi r3,1; \
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/* Branch to the code for nested exceptions */ \
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OR1K_DELAYED_NOP( \
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OR1K_INST(l.bnf .Lnested_##id) \
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); \
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/* Load pointer to exception stack array */ \
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l.movhi r1,hi(_or1k_exception_stack_core); \
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l.ori r1,r1,lo(_or1k_exception_stack_core); \
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l.lwz r1,0(r1); \
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/* Get core id */ \
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l.mfspr r3,r0,OR1K_SPR_SYS_COREID_ADDR; \
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/* Calculate offset in array */ \
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l.slli r3,r3,2; \
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l.add r1,r1,r3; \
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OR1K_DELAYED( \
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/* Load value from array to stack pointer */ \
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OR1K_INST(l.lwz r1,0(r1)), \
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/* and jump over nested exception pointer */ \
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OR1K_INST(l.j .Lnesting_done_##id) \
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); \
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.Lnested_##id: \
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/* The stack pointer is still active */ \
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/* Add redzone, nesting needs this */ \
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l.addi r1,r1,-REDZONE; \
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.Lnesting_done_##id: \
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/* Reserve context space */ \
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l.addi r1,r1,-EXCEPTION_STACK_FRAME; \
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/* Load back software's stack pointer */ \
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l.mfspr r3,r0,SHADOW_REG(1); \
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/* Store this in the context */ \
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l.sw GPR_BUF_OFFSET(1)(r1),r3; \
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/* Load back GPR3 */ \
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l.mfspr r3,r0,SHADOW_REG(2); \
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/* Store this in the context */ \
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l.sw GPR_BUF_OFFSET(3)(r1),r3; \
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/* Load back GPR4 */ \
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l.mfspr r4,r0,SHADOW_REG(3); \
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/* Store GPR4 in the context */ \
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l.sw GPR_BUF_OFFSET(4)(r1),r4; \
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/* Copy the current program counter as first */ \
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/* argument for the exception handler. This */ \
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/* is then used to determine the exception. */ \
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l.mfspr r3,r0,OR1K_SPR_SYS_NPC_ADDR; \
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OR1K_DELAYED( \
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/* Copy program counter of exception as */ \
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/* second argument to the exception handler */ \
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OR1K_INST(l.mfspr r4,r0,OR1K_SPR_SYS_EPCR_BASE),\
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/* Jump to exception handler. This will rfe */ \
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OR1K_INST(l.j _or1k_exception_handler) \
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)
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#endif
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/* -------------------------------------------------------------------------- */
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/*!Exception vectors */
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/* -------------------------------------------------------------------------- */
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.section .vectors,"ax"
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/* 0x100: RESET exception */
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.org 0x100
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_or1k_reset:
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l.movhi r0,0
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#ifdef __OR1K_MULTICORE__
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// This is a hack that relies on the fact, that all cores start at the
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// same time and they are similarily fast
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l.sw 0x4(r0),r0
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// Similarly, we use address 8 to signal how many cores have exit'ed
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l.sw 0x8(r0),r0
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#endif
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l.movhi r1,0
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l.movhi r2,0
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l.movhi r3,0
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l.movhi r4,0
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l.movhi r5,0
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l.movhi r6,0
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l.movhi r7,0
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l.movhi r8,0
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l.movhi r9,0
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l.movhi r10,0
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l.movhi r11,0
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l.movhi r12,0
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l.movhi r13,0
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l.movhi r14,0
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l.movhi r15,0
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l.movhi r16,0
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l.movhi r17,0
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l.movhi r18,0
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l.movhi r19,0
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l.movhi r20,0
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l.movhi r21,0
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l.movhi r22,0
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l.movhi r23,0
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l.movhi r24,0
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l.movhi r25,0
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l.movhi r26,0
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l.movhi r27,0
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l.movhi r28,0
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l.movhi r29,0
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l.movhi r30,0
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l.movhi r31,0
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/* Clear status register, set supervisor mode */
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l.ori r1,r0,OR1K_SPR_SYS_SR_SM_MASK
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l.mtspr r0,r1,OR1K_SPR_SYS_SR_ADDR
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/* Clear timer mode register*/
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l.mtspr r0,r0,OR1K_SPR_TICK_TTMR_ADDR
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/* Jump to program initialisation code */
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LOAD_SYMBOL_2_GPR(r4, _or1k_start)
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r4))
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.org 0x200
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CALL_EXCEPTION_HANDLER(2)
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/* 0x300: Data Page Fault exception */
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.org 0x300
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CALL_EXCEPTION_HANDLER(3)
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/* 0x400: Insn Page Fault exception */
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.org 0x400
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CALL_EXCEPTION_HANDLER(4)
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/* 0x500: Timer exception */
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.org 0x500
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CALL_EXCEPTION_HANDLER(5)
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/* 0x600: Aligment exception */
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.org 0x600
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CALL_EXCEPTION_HANDLER(6)
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/* 0x700: Illegal insn exception */
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.org 0x700
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CALL_EXCEPTION_HANDLER(7)
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/* 0x800: External interrupt exception */
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.org 0x800
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CALL_EXCEPTION_HANDLER(8)
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/* 0x900: DTLB miss exception */
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.org 0x900
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CALL_EXCEPTION_HANDLER(9)
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/* 0xa00: ITLB miss exception */
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.org 0xa00
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CALL_EXCEPTION_HANDLER(10)
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/* 0xb00: Range exception */
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.org 0xb00
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CALL_EXCEPTION_HANDLER(11)
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/* 0xc00: Syscall exception */
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.org 0xc00
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CALL_EXCEPTION_HANDLER(12)
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/* 0xd00: Floating point exception */
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.org 0xd00
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CALL_EXCEPTION_HANDLER(13)
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/* 0xe00: Trap exception */
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.org 0xe00
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CALL_EXCEPTION_HANDLER(14)
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/* 0xf00: Reserved exceptions */
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.org 0xf00
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CALL_EXCEPTION_HANDLER(15)
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.org 0x1000
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CALL_EXCEPTION_HANDLER(16)
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.org 0x1100
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CALL_EXCEPTION_HANDLER(17)
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.org 0x1200
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CALL_EXCEPTION_HANDLER(18)
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.org 0x1300
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CALL_EXCEPTION_HANDLER(19)
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.org 0x1400
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CALL_EXCEPTION_HANDLER(20)
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.org 0x1500
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CALL_EXCEPTION_HANDLER(21)
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.org 0x1600
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CALL_EXCEPTION_HANDLER(22)
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.org 0x1700
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CALL_EXCEPTION_HANDLER(23)
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.org 0x1800
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CALL_EXCEPTION_HANDLER(24)
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.org 0x1900
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CALL_EXCEPTION_HANDLER(25)
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.org 0x1a00
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CALL_EXCEPTION_HANDLER(26)
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.org 0x1b00
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CALL_EXCEPTION_HANDLER(27)
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.org 0x1c00
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CALL_EXCEPTION_HANDLER(28)
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.org 0x1d00
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CALL_EXCEPTION_HANDLER(29)
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.org 0x1e00
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CALL_EXCEPTION_HANDLER(30)
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.org 0x1f00
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CALL_EXCEPTION_HANDLER(31)
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/* Pad to the end */
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.org 0x1ffc
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l.nop
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/* -------------------------------------------------------------------------- */
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/*!Main entry point
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This is the initialization code of the library. It performs these steps:
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* Call early board initialization:
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Before anything happened, the board support may do some very early
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initialization. This is at maximum some very basic stuff that would
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otherwise prevent the following code from functioning. Other initialization
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of peripherals etc. is done later (before calling main).
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See the description below and README.board for details.
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* Initialize the stacks:
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Two stacks are configured: The system stack is used by the software and
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the exception stack is used when an exception occurs. We added this as
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this should be flexible with respect to the usage of virtual memory.
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* Activate the caches:
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If available the caches are initiliazed and activated.
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* Clear BSS:
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The BSS are essentially the uninitialized C variables. They are set to 0
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by default. This is performed by this function.
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* Initialize the impure data structure:
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Similarly, we need two library contexts, one for the normal software and
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one that is used during exceptions. The impure data structure holds
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the context information of the library. The called C function will setup
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both data structures. There is furthermore a pointer to the currently
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active impure data structure, which is initially set to the normal one.
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* Initialize or1k support library reentrant data structures
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* Initialize constructors:
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Call the static and global constructors
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* Set up destructors to call from exit
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The library will call the function set via atexit() during exit(). We set
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it to call the _fini function which performs destruction.
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* Call board initialization:
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The board initialization can perform board specific initializations such as
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configuring peripherals etc.
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* Jump to main
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Call main with argc = 0 and *argv[] = 0
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* Call exit after main returns
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Now we call exit()
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* Loop forever
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We are dead.
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*/
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/* -------------------------------------------------------------------------- */
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.section .text
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/* Following externs from board-specific object passed at link time */
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.extern _or1k_board_mem_base
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.extern _or1k_board_mem_size
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.extern _or1k_board_uart_base
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/* The early board initialization may for example read the memory size and
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set the mem_base and mem_size or do some preliminary board
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initialization. As we do not have a stack at this time, the function may
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not use the stack (and therefore be a or call a C function. But it can
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safely use all registers.
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We define a default implementation, which allows board files in C. As
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described above, this can only be used in assembly (board_*.S) as at
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the early stage not stack is available. A board that needs early
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initialization can overwrite the function with .global _board_init_early.
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Recommendation: Only use when you really need it! */
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.weak _or1k_board_init_early
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_or1k_board_init_early:
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* The board initialization is then called after the C library and UART
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are initialized. It can then be used to configure UART or other
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devices before the actual main function is called. */
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.extern _or1k_board_init
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.global _or1k_start
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.type _or1k_start,@function
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_or1k_start:
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/* It is good to initialize and enable the caches before we do anything,
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otherwise the cores will continuously access the bus during the wait
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time for the boot barrier (0x4).
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Fortunately or1k_cache_init does not need a stack */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_cache_init))
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#ifdef __OR1K_MULTICORE__
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// All but core 0 have to wait
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l.mfspr r1, r0, OR1K_SPR_SYS_COREID_ADDR
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l.sfeq r1, r0
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OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lcore0))
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.Lspin:
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/* r1 will be used by the other cores to check for the boot variable
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Check if r1 is still zero, core 0 will set it to 1 once it booted
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As the cache is already turned on, this will not create traffic on
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the bus, but the change is snooped by cache coherency then */
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l.lwz r1,0x4(r0)
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l.sfeq r1, r0
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OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lspin))
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/* Initialize core i stack */
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// _or1k_stack_core is the array of stack pointers
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LOAD_SYMBOL_2_GPR(r2,_or1k_stack_core)
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// Load the base address
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l.lwz r2,0(r2)
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// Generate offset in array
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l.mfspr r1,r0,OR1K_SPR_SYS_COREID_ADDR
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l.slli r1,r1,2
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// Add to array base
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l.add r2,r2,r1
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// Load pointer to the stack top and set frame pointer
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l.lwz r1,0(r2)
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l.or r2,r1,r1
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// The slave cores are done, jump to main part
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OR1K_DELAYED_NOP(OR1K_INST(l.j .Linit_done));
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/* Only core 0 executes the initialization code */
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.Lcore0:
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#endif
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/* Call early board initialization */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_board_init_early))
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/* Clear BSS */
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.Lclear_bss:
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LOAD_SYMBOL_2_GPR(r3,__bss_start)
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LOAD_SYMBOL_2_GPR(r4,end)
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.Lclear_bss_loop:
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l.sw (0)(r3),r0
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l.sfltu r3,r4
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OR1K_DELAYED(
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OR1K_INST(l.addi r3,r3,4),
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OR1K_INST(l.bf .Lclear_bss_loop)
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)
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/* Initialise stack and frame pointer (set to same value) */
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LOAD_SYMBOL_2_GPR(r1,_or1k_board_mem_base)
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l.lwz r1,0(r1)
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LOAD_SYMBOL_2_GPR(r2,_or1k_board_mem_size)
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l.lwz r2,0(r2)
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l.add r1,r1,r2
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/* Store exception stack top address */
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LOAD_SYMBOL_2_GPR(r3,_or1k_exception_stack_top)
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l.sw 0(r3),r1
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/* Store exception stack bottom address */
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// calculate bottom address
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// r3 = *exception stack size
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LOAD_SYMBOL_2_GPR(r3,_or1k_exception_stack_size)
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// r3 = exception stack size
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l.lwz r3,0(r3)
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#ifdef __OR1K_MULTICORE__
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l.mfspr r4,r0,OR1K_SPR_SYS_NUMCORES_ADDR
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l.mul r3,r4,r3
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#endif
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// r4 = exception stack top - exception stack size = exception stack bottom
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l.sub r4,r1,r3
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// r5 = *exception stack bottom
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LOAD_SYMBOL_2_GPR(r5,_or1k_exception_stack_bottom)
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// store
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l.sw 0(r5),r4
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// Move stack pointer accordingly
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l.or r1,r0,r4
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l.or r2,r1,r1
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/* Store stack top address */
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LOAD_SYMBOL_2_GPR(r3,_or1k_stack_top)
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l.sw 0(r3),r1
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/* Store stack bottom address */
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// calculate bottom address
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// r3 = stack size
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LOAD_SYMBOL_2_GPR(r3,_or1k_stack_size)
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l.lwz r3,0(r3)
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#ifdef __OR1K_MULTICORE__
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l.mfspr r4, r0, OR1K_SPR_SYS_NUMCORES_ADDR
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l.mul r3, r4, r3
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#endif
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// r4 = stack top - stack size = stack bottom
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// -> stack bottom
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l.sub r4,r1,r3
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// r5 = *exception stack bottom
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LOAD_SYMBOL_2_GPR(r5,_or1k_stack_bottom)
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// store to variable
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l.sw 0(r5),r4
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/* Reinitialize the or1k support library */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_init))
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/* Reinitialize the reentrancy structure */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_libc_impure_init))
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/* Call global and static constructors */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _init))
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/* Set up destructors to be called from exit if main ever returns */
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l.movhi r3,hi(_fini)
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OR1K_DELAYED(
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OR1K_INST(l.ori r3,r3,lo(_fini)),
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OR1K_INST(l.jal atexit)
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)
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/* Check if UART is to be initialised */
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LOAD_SYMBOL_2_GPR(r4,_or1k_board_uart_base)
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l.lwz r4,0(r4)
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/* Is base set? If not, no UART */
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l.sfne r4,r0
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l.bnf .Lskip_uart
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l.or r3,r0,r0
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_uart_init))
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.Lskip_uart:
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/* Board initialization */
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OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_board_init))
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#ifdef __OR1K_MULTICORE__
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// Start other cores
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l.ori r3, r0, 1
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l.sw 0x4(r0), r3
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#endif
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.Linit_done:
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/* Jump to main program entry point (argc = argv = envp = 0) */
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l.or r3,r0,r0
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l.or r4,r0,r0
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OR1K_DELAYED(
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OR1K_INST(l.or r5,r0,r0),
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OR1K_INST(l.jal main)
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)
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#ifdef __OR1K_MULTICORE__
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.incrementexit:
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/* Atomically increment number of finished cores */
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l.lwa r3,0x8(r0)
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l.addi r3,r3,1
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l.swa 0x8(r0),r3
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf .incrementexit));
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/* Compare to number of cores in this cluster */
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l.mfspr r4,r0, OR1K_SPR_SYS_NUMCORES_ADDR
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/* Compare to number of finished tasks */
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l.sfeq r3,r4
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/* Last core needs to desctruct library etc. */
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OR1K_DELAYED_NOP(OR1K_INST(l.bf .exitcorelast));
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OR1K_DELAYED(
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OR1K_INST(l.addi r3,r11,0),
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OR1K_INST(l.jal _exit)
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)
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.exitcorelast:
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#endif
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/* If program exits, call exit routine */
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OR1K_DELAYED(
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OR1K_INST(l.addi r3,r11,0),
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OR1K_INST(l.jal exit)
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)
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/* Loop forever */
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.Lloop_forever:
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OR1K_DELAYED_NOP(OR1K_INST(l.j .Lloop_forever))
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.size _or1k_start,.-_or1k_start
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