166 lines
5.1 KiB
C
166 lines
5.1 KiB
C
/* or1k_uart.c -- UART implementation for OpenRISC 1000.
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*
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*Copyright (c) 2014 Authors
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*
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* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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* Contributor Olof Kindgren <olof.kindgren@gmail.com>
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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#include "include/or1k-support.h"
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#include "or1k_uart.h"
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#include <stdint.h>
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// Register interface
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#define RB _or1k_board_uart_base + 0 // Receiver Buffer (R)
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#define THR _or1k_board_uart_base + 0 // Transmitter Holding Register (W)
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#define IER _or1k_board_uart_base + 1 // Interrupt Enable Register (RW)
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#define IIR _or1k_board_uart_base + 2 // Interrupt Identification Register (R)
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#define FCR _or1k_board_uart_base + 2 // FIFO Control Register (W)
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#define LCR _or1k_board_uart_base + 3 // Line Control Register (RW)
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#define MCR _or1k_board_uart_base + 4 // Modem Control Register (W)
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#define LSR _or1k_board_uart_base + 5 // Line Status Register (R)
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#define MSR _or1k_board_uart_base + 6 // Modem Status Register (R)
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// Divisor Register (Accessed when DLAB bit in LCR is set)
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#define DLB1 _or1k_board_uart_base + 0 // Divisor Latch LSB (RW)
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#define DLB2 _or1k_board_uart_base + 1 // Divisor Latch MSB (RW)
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// Interrupt Enable Register bits
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#define IER_RDAI 0 // Receiver Data Available Interrupt
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#define IER_TEI 1 // Transmitter Holding Register Empty Interrupt
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#define IER_RLSI 2 // Receiver Line Status Interrupt
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#define IER_MSI 3 // Modem Status Interrupt
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// Interrupt Identification Register Values
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#define IIR_RLS 0xC6 // Receiver Line Status
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#define IIR_RDA 0xC4 // Receiver Data Available
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#define IIR_TO 0xCC // Timeout
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#define IIR_THRE 0xC2 // Transmitter Holding Register Empty
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#define IIT_MS 0xC0 // Modem Status
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// FIFO Control Register bits
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#define FCR_CLRRECV 0x1 // Clear receiver FIFO
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#define FCR_CLRTMIT 0x2 // Clear transmitter FIFO
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// FIFO Control Register bit 7-6 values
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#define FCR_TRIG_1 0x0 // Trigger level 1 byte
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#define FCR_TRIG_4 0x40 // Trigger level 4 bytes
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#define FCR_TRIG_8 0x80 // Trigger level 8 bytes
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#define FCR_TRIG_14 0xC0 // Trigger level 14 bytes
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// Line Control Reigster values and bits
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#define LCR_BPC_5 0x0 // 5 bits per character
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#define LCR_BPC_6 0x1 // 6 bits per character
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#define LCR_BPC_7 0x2 // 7 bits per character
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#define LCR_BPC_8 0x3 // 8 bits per character
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#define LCR_SB_1 0x0 // 1 stop bit
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#define LCR_SB_2 0x4 // 1.5 stop bits (LCR_BPC_5) or 2 stop bits (else)
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#define LCR_PE 0x8 // Parity Enabled
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#define LCR_EPS 0x10 // Even Parity Select
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#define LCR_SP 0x20 // Stick Parity
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#define LCR_BC 0x40 // Break Control
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#define LCR_DLA 0x80 // Divisor Latch Access
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// Line Status Register
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#define LSR_DR 0x0 // Data Ready
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#define LSR_OE 0x2 // Overrun Error
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#define LSR_PE 0x4 // Parity Error
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#define LSR_FE 0x8 // Framing Error
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#define LSR_BI 0x10 // Break Interrupt
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#define LSR_TFE 0x20 // Transmitter FIFO Empty
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#define LSR_TEI 0x40 // Transmitter Empty Indicator
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/**
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* The registered callback function
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*/
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void (*_or1k_uart_read_cb)(char c);
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/**
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* This is the interrupt handler that is registered for the callback
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* function.
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*/
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void _or1k_uart_interrupt_handler(uint32_t data)
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{
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uint8_t iir = REG8(IIR);
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// Check if this is a read fifo interrupt, bit 0 indicates pending
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// interrupt and the other bits are IIR_RDA
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if (!(iir & 0x1) || ((iir & 0xfe) != IIR_RDA)) {
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return;
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}
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// Read character and call callback function
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_or1k_uart_read_cb(REG8(RB));
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}
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int _or1k_uart_init(void)
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{
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uint16_t divisor;
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// Is uart present?
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if (!_or1k_board_uart_base) {
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return -1;
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}
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// Reset the callback function
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_or1k_uart_read_cb = 0;
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// Calculate and set divisor
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divisor = _or1k_board_clk_freq / (_or1k_board_uart_baud * 16);
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REG8(LCR) = LCR_DLA;
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REG8(DLB1) = divisor & 0xff;
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REG8(DLB2) = divisor >> 8;
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// Set line control register:
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// - 8 bits per character
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// - 1 stop bit
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// - No parity
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// - Break disabled
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// - Disallow access to divisor latch
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REG8(LCR) = LCR_BPC_8;
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// Reset FIFOs and set trigger level to 14 bytes
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REG8(FCR) = FCR_CLRRECV | FCR_CLRTMIT | FCR_TRIG_14;
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// Disable all interrupts
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REG8(IER) = 0;
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return 0;
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}
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void _or1k_uart_write(char c)
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{
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// Wait until FIFO is empty
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while (!(REG8(LSR) & LSR_TFE)) {}
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// Write character to device
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REG8(THR) = c;
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}
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void or1k_uart_set_read_cb(void (*cb)(char c))
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{
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// Set callback function
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_or1k_uart_read_cb = cb;
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// Enable interrupt
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REG8(IER) = 1 << IER_RDAI;
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// Add the interrupt handler that calls the callback function
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or1k_interrupt_handler_add(_or1k_board_uart_IRQ,
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_or1k_uart_interrupt_handler, 0);
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// Enable UART interrupt
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or1k_interrupt_enable(_or1k_board_uart_IRQ);
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}
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