f34428eb35
* cpu_features.c: New file. * cpu_features.h: New file. * crt1.c: Include "cpu_features.h". (__mingw_CRTStartup): Call cpu_features_init(). * Makefile.in (MING_OBJS): Add cpu_features.c. (SRCDIST_FILES): Add cpu_features.c, cpu_features.h. * include/fenv,h ( fenv_t;): Append __mxcsr field. (__MXCSR_EXCEPT_FLAG_SHIFT): New define. (__MXCSR_EXCEPT_MASK_SHIFT): New define. (__MXCSR_ROUND_FLAG_SHIFT): New define. * mingwex/feclearexcept.c: Include "cpu_features.h". Handle SSE environment. * mingwex/fegetenv.c: Likewise. * mingwex/feholdexcept.c: Likewise. * mingwex/fesetenv.c: Likewise. * mingwex/fesetexceptflag.c: Likewise. * mingwex/fesetround.c: Likewise. * mingwex/fetestexcept.c: Likewise. * mingwex/feupdateenv.c: Likewise. * mingwex/fegetround.c: Add comment.
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
#include <fenv.h>
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#include <float.h>
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#include "cpu_features.h"
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/* 7.6.4.3
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The fesetenv function establishes the floating-point environment
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represented by the object pointed to by envp. The argument envp
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points to an object set by a call to fegetenv or feholdexcept, or
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equal the macro FE_DFL_ENV or an implementation-defined environment
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macro. Note that fesetenv merely installs the state of the exception
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flags represented through its argument, and does not raise these
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exceptions.
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*/
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extern void (*_imp___fpreset)( void ) ;
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int fesetenv (const fenv_t * envp)
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{
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/* Default mxcsr status is to mask all exceptions. All other bits
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are zero. */
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unsigned int _csr = FE_ALL_EXCEPT << __MXCSR_EXCEPT_MASK_SHIFT /*= 0x1f80 */;
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if (envp == FE_PC64_ENV)
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/*
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* fninit initializes the control register to 0x37f,
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* the status register to zero and the tag word to 0FFFFh.
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* The other registers are unaffected.
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*/
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__asm__ ("fninit");
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else if (envp == FE_PC53_ENV)
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/*
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* MS _fpreset() does same *except* it sets control word
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* to 0x27f (53-bit precison).
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* We force calling _fpreset in msvcrt.dll
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*/
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(*_imp___fpreset)();
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else if (envp == FE_DFL_ENV)
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/* Use the choice made at app startup */
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_fpreset();
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else
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{
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__asm__ ("fldenv %0;" : : "m" (*envp));
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/* Setting the reserved high order bits of MXCSR causes a segfault */
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_csr = envp ->__mxcsr & 0xffff;
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}
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/* Set MXCSR */
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if (__HAS_SSE)
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__asm__ volatile ("ldmxcsr %0" : : "m" (_csr));
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return 0;
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}
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