601 lines
28 KiB
ArmAsm
601 lines
28 KiB
ArmAsm
/**
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* fido-crt0.S -- Simple startup code
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*
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* Copyright (c) 1995, 1996, 1998 Cygnus Support
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*
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* Copyright 2006 Innovasic Semiconductor, All Rights Reserved.
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* Part of the fido Realtime Support Library
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*
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* Description:
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* This routine performs initializations assuming a Fido
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* development board. In order, the following functions are performed:
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*
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* -- memory offset register initialization
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* -- chip select register initialization for external memory
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* -- SDRAM ctrl register initialization for external memory
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* -- in line test of external SRAM
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* -- sets user SP for MasterContext0 (main)
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* -- copies the bss section to RAM
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* -- transfers control to MasterContext0 (main)
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*
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*/
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#include "asm.h"
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#include "fido.h"
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.title "fido-crt0.S for Fido"
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/*----------------------------------------------------------------------------*/
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//--------- 66 MHz values --------
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// set up CS0 for flash
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#define CS0_CTRL_VAL 0x0000024A
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#define CS0_TIMING_VAL 0x01000000
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// set up CS1 for SDRAM
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#define CS1_CTRL_VAL 0x0200030A /* selects SDRAM ctrl instead of CS1 */
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#define CS1_TIMING_VAL 0x00000000 /* N/A for SDRAM operation */
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#define SDRAM_TIMING_0_VAL 0x00022522 /* TRP=0x2, TRCD=0x2, TRF=0x5, TWR=0x5 TCL=0x5 */
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#define SDRAM_TIMING_1_VAL 0x00120407 /* INI_PREC=0x1, INI_REFT=0x2, REF_INTV=0x407 */
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#define SDRAM_CONFIG_0_VAL 0x00002113 /* MA2T=0, DDW=x16device=0x2, dsz=64MBit, mbw=16bit, bnksz=8Mbyte */
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#define SDRAM_CONFIG_1_VAL 0x00000000 /* IPREC=0, IREF=0, ISMR=0, PWDN=0, SREF=0 */
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#define SDRAM_EXT_BANK_1_VAL 0x00001020 /* SDRAM memory bank 0 at addr 0x0200_0000 */
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// set up CS2 for SRAM
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#define CS2_CTRL_VAL 0x03000267
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#define CS2_TIMING_VAL 0x08400000
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/*----------------------------------------------------------------------------*/
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#define EXT_SRAM_END_ADDR 0x30FFFFC /* 1 MB of ext. SRAM (2-512Kx8 chips) */
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#define PERP_PWRUP_MASK 0x0000 /* turn on all peripherals */
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/*
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* Define an empty environment.
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*/
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.data 2
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.align 2
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SYM (environ):
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.long 0
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.align 2
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.text 2
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/*
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* These symbols are defined in C code, so they need to always be
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* named with SYM because of the difference between object file formats.
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*/
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/* These are defined in C code. */
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/* .extern SYM (main) */
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.extern SYM (exit)
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.extern SYM (hardware_init_hook)
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.extern SYM (software_init_hook)
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.extern SYM (atexit)
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.extern SYM (__do_global_dtors)
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/*
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* These values are set in the linker script, so they must be
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* explicitly named here without SYM.
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*/
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#ifdef FIDO_rom
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.extern __stack
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#endif
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.extern __bss_start
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.extern _end
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/*
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* set things up so application will run. This *must* be called _start.
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*/
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.global SYM (_start)
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SYM (_start):
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#ifdef FIDO_rom
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/* save initial value of base offset register */
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movec mbb,d7
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/* Initialize memory offset register to offset value in FIDOmemmap.h */
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movel #FIDO_MEM_OFFSET,d0 /* Load memory offset into REG d0 */
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movec d0,mbb
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movel #0x011, FIDO_DBG_CTRL /* set the debug control reg */
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/* At POR the PerpPowerCtrlReg is set to 0x3F0F, all peripherals off
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See PerpPowerCtrlReg definition, this example turns ON everything */
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movel #PERP_PWRUP_MASK,FIDO_CLOCK_MASK_REGISTER
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/* Set up chip selects for ROM, SRAM, and SDRAM (all external mem.) */
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movel #CS0_CTRL_VAL, FIDO_BIU_CS0_CONTROL /* flash memory CS0 */
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movel #CS0_TIMING_VAL, FIDO_BIU_CS0_TIMING
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movel #CS2_CTRL_VAL, FIDO_BIU_CS2_CONTROL /* SRAM memory CS2 */
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movel #CS2_TIMING_VAL, FIDO_BIU_CS2_TIMING
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/* if this is not POR then say so */
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movel FIDO_POR_REG,d6
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/* test external SRAM -- */
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/* a0 == working pointer */
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/* a1 == pointer to base of memory */
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/* a2 == pointer to end of memory */
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/* d0,d1,d2,d3 working registers */
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moveal #0x3000000,a1
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moveal #0x30FFFFC,a2
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movel a1,a0
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/* walking ones */
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movel #1,d0
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.LWalkOnes:
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movel d0, (a0) /* write value out */
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cmpl (a0), d0 /* read it back */
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bne .LFailOnes
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lsl.l #1, d0 /* move to next value */
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bne .LWalkOnes /* when it goes to zero you're done */
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bra .LValTest
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.LFailOnes:
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movel #0x01, d0
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bra .LMemTestEnd
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.LValTest:
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/* ffff's */
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/* 5555's */
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/* aaaa's */
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/* 0000's */
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movel a1,a0
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movel #0xFFFFFFFF,d0
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.LValLoop:
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movel d0,(a0) /* write value out */
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cmpl (a0)+, d0 /* compare and move to next */
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bne .LFailVal
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cmpl a0,a2 /* at end of memory? */
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bge .LValLoop
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movel d0,d0 /* done writing zeros? */
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beq .LAddrTest
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movel a1,a0 /* go back to start with next value */
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subl #0x55555555,d0 /* get next value (f->a->5->0) */
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bra .LValLoop
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.LFailVal:
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movel #0x02, d0
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bra .LMemTestEnd
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.LAddrTest:
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/* unique values */
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movel a1,a0
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.LWriteLoop:
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movel a0, (a0)+ /* write value out and move one */
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cmpl a0,a2 /* look for end of memory */
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bge .LWriteLoop
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movel a1,a0
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.LReadLoop:
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cmpl (a0), a0 /* compare value and move on */
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bne .LFailAddr
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addql #4,a0
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cmpl a0,a2 /* look for end of memory */
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bge .LReadLoop
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clrl d0 /* everything passed */
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bra .LMemTestEnd
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.LFailAddr:
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movel #0x03, d0
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.LMemTestEnd:
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movel d0,d4 /* mem test result in d4 0 == pass */
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#endif /* ROM */
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/* See if user supplied their own stack (__stack != 0). If not, then
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* default to using the value of %sp as set by the ROM monitor */
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movel IMM(__stack), a0
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cmpl IMM(0), a0
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jbeq .Lloc1
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movel a0, sp
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.Lloc1:
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/* set up initial stack frame */
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link a6, IMM(-8)
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#ifdef FIDO_rom
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/*
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* Now set up the SDRAM (waited to let the controller spin up)
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*/
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/* always initialize SDRAM regs, they're cleared by any reset */
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/* SDRAM enbl bit set in CS1 re-directs to SDRAM controller regs */
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movel #CS1_CTRL_VAL, FIDO_BIU_CS1_CONTROL /* SDRAM memory CS1 */
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movel #SDRAM_TIMING_0_VAL, FIDO_SDRAM_TIMING_0 /* SDRAM TIMING REG0 */
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movel #SDRAM_TIMING_1_VAL, FIDO_SDRAM_TIMING_1 /* SDRAM TIMING REG1 */
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movel #SDRAM_CONFIG_0_VAL, FIDO_SDRAM_CONFIG_0 /* SDRAM CONFIG REG */
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movel #0x0000001c, FIDO_SDRAM_CONFIG_1 /* SDRAM CONFIG REG */
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.LsdConfigLoop:
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movel FIDO_SDRAM_CONFIG_1,d0
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cmpl #0x00000000,d0
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bne .LsdConfigLoop
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movel #SDRAM_EXT_BANK_1_VAL, FIDO_SDRAM_EXT_BANK_1 /* BANK 1 REG */
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/*
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* copy data from ROM to RAM
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*/
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moval IMM(__start_romdata),a0 /* begin data in ROM */
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moval IMM(_data), a1 /* begin data in RAM */
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moval IMM(_edata),a2 /* end of data in RAM */
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/* while(a1 < a2) *a1++ = *a0++; */
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.LdataCopyLoop:
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movel (a0)+,(a1)+
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cmpal a1,a2
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bgt .LdataCopyLoop
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#endif /* ROM */
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#ifdef FIDO_ram
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/* For ROM configs, the linker script ensures that
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_vector_table is placed at the proper place. For RAM
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configs, we have to adjust it ourselves. */
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movel IMM (SYM (_vector_table)), FIDO_CTX0_VBR
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#endif
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#ifndef FIDO_redboot
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/* Setup interrupt vectors for secondary contexts. */
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movel IMM (SYM (_vector_table1)), FIDO_CTX1_VBR
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movel IMM (SYM (_vector_table2)), FIDO_CTX2_VBR
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movel IMM (SYM (_vector_table3)), FIDO_CTX3_VBR
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movel IMM (SYM (_vector_table4)), FIDO_CTX4_VBR
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#endif
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/*
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* zero out the bss section.
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*/
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movel IMM(__bss_start), d1
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movel IMM(_end), d0
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cmpl d0, d1
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jbeq .Lloc3
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movl d1, a0
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subl d1, d0
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subql IMM(1), d0
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2:
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clrb (a0)+
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#ifndef __mcf5200__
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dbra d0, 2b
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clrw d0
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subql IMM(1), d0
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jbcc 2b
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#else
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subql IMM(1), d0
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jbpl 2b
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#endif
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.Lloc3:
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#ifdef ADD_DTORS
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/* put __do_global_dtors in the atexit list so the destructors get run */
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movel IMM (SYM(__do_global_dtors)),(sp)
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jsr SYM (atexit)
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#endif
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movel IMM (_fini),(sp)
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jsr SYM (atexit)
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jsr _init
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/*
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* call the main routine from the application to get it going.
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* main (argc, argv, environ)
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* we pass argv as a pointer to NULL.
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*/
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pea 0
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pea SYM (environ)
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pea sp@(4)
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pea 0
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jsr SYM (main) /* call to main */
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movel d0, sp@-
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/*
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* drop down into exit in case the user doesn't. This should drop
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* control back to the ROM monitor, if there is one. This calls the
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* exit() from the C library so the C++ tables get cleaned up right.
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*/
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jsr SYM (exit)
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#ifndef FIDO_redboot
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/* Define the interrupt vector table. The linker script
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ensures that the table is placed at address zero. */
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.section .vector_table,"a"
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.global SYM (_vector_table)
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SYM (_vector_table):
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dc.l __stack /* 000 Initial Stack */
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dc.l _start /* 001 Context 0 Start */
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dc.l _BusErrorHandler /* 002 Bus Error */
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dc.l _AddressErrorHandler /* 003 Address Error */
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dc.l _IllegalInstructionHandler /* 004 Illegal Instruction */
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dc.l _DivideByZeroHandler /* 005 Divide by Zero */
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dc.l _ChkHandler /* 006 CHK, CHK2 Instructions */
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dc.l _TrapccHandler /* 007 TRAPcc, TRAPV Instructions */
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dc.l _PrivilegeViolationHandler /* 008 Privilege Violation */
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dc.l _TraceHandler /* 009 Trace */
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dc.l _ALineHandler /* 010 A-Line Unimplemented Instr */
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dc.l _FLineHandler /* 011 F-Line Unimplemented Instr */
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dc.l _HwBreakpointHandler /* 012 Hardware Breakpoint */
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dc.l _Reserved0Handler /* 013 Reserved */
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dc.l _FormatErrorHandler /* 014 Format Error */
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dc.l _UnitializedIntHandler /* 015 Unitialized Interrupt */
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dc.l _SoftwareIntHandler /* 016 Software Interrupt */
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dc.l _Unassigned0Handler /* 017 Unassigned */
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dc.l _Unassigned1Handler /* 018 Unassigned */
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dc.l _Unassigned2Handler /* 019 Unassigned */
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dc.l _Unassigned3Handler /* 020 Unassigned */
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dc.l _Unassigned4Handler /* 021 Unassigned */
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dc.l _Unassigned5Handler /* 022 Unassigned */
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dc.l _Unassigned6Handler /* 023 Unassigned */
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dc.l _Int0Handler /* 024 Interrupt 0 */
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dc.l _Int1Handler /* 025 Interrupt 1 */
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dc.l _Int2Handler /* 026 Interrupt 2 */
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dc.l _Int3Handler /* 027 Interrupt 3 */
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dc.l _Int4Handler /* 028 Interrupt 4 */
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dc.l _Int5Handler /* 029 Interrupt 5 */
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dc.l _Int6Handler /* 030 Interrupt 6 */
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dc.l _Int7Handler /* 031 Interrupt 7 */
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dc.l _Trap00Handler /* 032 Trap #00 Instruction */
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dc.l _Trap01Handler /* 033 Trap #01 Instruction */
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dc.l _Trap02Handler /* 034 Trap #02 Instruction */
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dc.l _Trap03Handler /* 035 Trap #03 Instruction */
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dc.l _Trap04Handler /* 036 Trap #04 Instruction */
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dc.l _Trap05Handler /* 037 Trap #05 Instruction */
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dc.l _Trap06Handler /* 038 Trap #06 Instruction */
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dc.l _Trap07Handler /* 039 Trap #07 Instruction */
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dc.l _Trap08Handler /* 040 Trap #08 Instruction */
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dc.l _Trap09Handler /* 041 Trap #09 Instruction */
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dc.l _Trap10Handler /* 042 Trap #10 Instruction */
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dc.l _Trap11Handler /* 043 Trap #11 Instruction */
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dc.l _Trap12Handler /* 044 Trap #12 Instruction */
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dc.l _Trap13Handler /* 045 Trap #13 Instruction */
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dc.l _Trap14Handler /* 046 Trap #14 Instruction */
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dc.l _Trap15Handler /* 047 Trap #15 Instruction */
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dc.l _Reserved048Handler /* 048 Reserved */
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dc.l _Reserved049Handler /* 049 Reserved */
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dc.l _Reserved050Handler /* 050 Reserved */
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dc.l _Reserved051Handler /* 051 Reserved */
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dc.l _Reserved052Handler /* 052 Reserved */
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dc.l _Reserved053Handler /* 053 Reserved */
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dc.l _Reserved054Handler /* 054 Reserved */
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dc.l _Reserved055Handler /* 055 Reserved */
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dc.l _Reserved056Handler /* 056 Reserved */
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dc.l _Reserved057Handler /* 057 Reserved */
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dc.l _Reserved058Handler /* 058 Reserved */
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dc.l _Reserved059Handler /* 059 Reserved */
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dc.l _Reserved060Handler /* 060 Reserved */
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dc.l _Reserved061Handler /* 061 Reserved */
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dc.l _Reserved062Handler /* 062 Reserved */
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dc.l _Reserved063Handler /* 063 Reserved */
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dc.l _ContextOvertimeHandler /* 064 Context Overtime */
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dc.l _MpuErrorHandler /* 065 MPU Error */
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dc.l _SystemTimer0Handler /* 066 System Timer 0 */
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dc.l _SystemTimer1Handler /* 067 System Timer 1 */
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dc.l _SystemTimer2Handler /* 068 System Timer 2 */
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dc.l _SystemTimer3Handler /* 069 System Timer 3 */
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dc.l _SystemTimer4Handler /* 070 System Timer 4 */
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dc.l _WatchdogTimerHandler /* 071 Watchdog Timer */
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dc.l _TimerCounter0Handler /* 072 Timer Counter 1 */
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dc.l _TimerCounter1Handler /* 073 Timer Counter 2 */
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dc.l _DMA0Handler /* 074 DMA Channel 0 */
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dc.l _DMA1Handler /* 075 DMA Channel 1 */
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dc.l _AtoDConversionHandler /* 076 A/D Conversion Complete */
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dc.l _Pdma0Handler /* 077 PDMA Ch 0 Interrupt */
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dc.l _Pdma1Handler /* 078 PDMA Ch 1 Interrupt */
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dc.l _Pdma2Handler /* 079 PDMA Ch 2 Interrupt */
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dc.l _Pdma3Handler /* 080 PDMA Ch 3 Interrupt */
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dc.l _Reserved081Handler /* 081 Reserved */
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dc.l _Reserved082Handler /* 082 Reserved */
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dc.l _Reserved083Handler /* 083 Reserved */
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dc.l _Reserved084Handler /* 084 Reserved */
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dc.l _Reserved085Handler /* 085 Reserved */
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dc.l _Reserved086Handler /* 086 Reserved */
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dc.l _Reserved087Handler /* 087 Reserved */
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dc.l _Reserved088Handler /* 088 Reserved */
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dc.l _Reserved089Handler /* 089 Reserved */
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dc.l _Reserved090Handler /* 090 Reserved */
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dc.l _Reserved091Handler /* 091 Reserved */
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dc.l _Reserved092Handler /* 092 Reserved */
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dc.l _Reserved093Handler /* 093 Reserved */
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dc.l _Reserved094Handler /* 094 Reserved */
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dc.l _Reserved095Handler /* 095 Reserved */
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dc.l _Trapx00Handler /* 096 Trapx 00 Instruction */
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dc.l _Trapx01Handler /* 097 Trapx 01 Instruction */
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dc.l _Trapx02Handler /* 098 Trapx 02 Instruction */
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dc.l _Trapx03Handler /* 099 Trapx 03 Instruction */
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dc.l _Trapx04Handler /* 100 Trapx 04 Instruction */
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dc.l _Trapx05Handler /* 101 Trapx 05 Instruction */
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dc.l _Trapx06Handler /* 102 Trapx 06 Instruction */
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dc.l _Trapx07Handler /* 103 Trapx 07 Instruction */
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dc.l _Trapx08Handler /* 104 Trapx 08 Instruction */
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dc.l _Trapx09Handler /* 105 Trapx 09 Instruction */
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dc.l _Trapx10Handler /* 106 Trapx 10 Instruction */
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dc.l _Trapx11Handler /* 107 Trapx 11 Instruction */
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dc.l _Trapx12Handler /* 108 Trapx 12 Instruction */
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dc.l _Trapx13Handler /* 109 Trapx 13 Instruction */
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dc.l _Trapx14Handler /* 110 Trapx 14 Instruction */
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dc.l _Trapx15Handler /* 111 Trapx 15 Instruction */
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dc.l _DummyHandler /* 112 */
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dc.l _DummyHandler /* 113 */
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dc.l _DummyHandler /* 114 */
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dc.l _DummyHandler /* 115 */
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dc.l _DummyHandler /* 116 */
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dc.l _DummyHandler /* 117 */
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dc.l _DummyHandler /* 118 */
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dc.l _DummyHandler /* 119 */
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dc.l _DummyHandler /* 120 */
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dc.l _DummyHandler /* 121 */
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dc.l _DummyHandler /* 122 */
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dc.l _DummyHandler /* 123 */
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dc.l _DummyHandler /* 124 */
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dc.l _DummyHandler /* 125 */
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dc.l _DummyHandler /* 126 */
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dc.l _DummyHandler /* 127 */
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dc.l _DummyHandler /* 128 */
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dc.l _DummyHandler /* 129 */
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dc.l _DummyHandler /* 130 */
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dc.l _DummyHandler /* 131 */
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dc.l _DummyHandler /* 132 */
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dc.l _DummyHandler /* 133 */
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dc.l _DummyHandler /* 134 */
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dc.l _DummyHandler /* 135 */
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dc.l _DummyHandler /* 136 */
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dc.l _DummyHandler /* 137 */
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dc.l _DummyHandler /* 138 */
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dc.l _DummyHandler /* 139 */
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dc.l _DummyHandler /* 140 */
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dc.l _DummyHandler /* 141 */
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dc.l _DummyHandler /* 142 */
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dc.l _DummyHandler /* 143 */
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dc.l _DummyHandler /* 144 */
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dc.l _DummyHandler /* 145 */
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dc.l _DummyHandler /* 146 */
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dc.l _DummyHandler /* 147 */
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dc.l _DummyHandler /* 148 */
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dc.l _DummyHandler /* 149 */
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dc.l _DummyHandler /* 150 */
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dc.l _DummyHandler /* 151 */
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dc.l _DummyHandler /* 152 */
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dc.l _DummyHandler /* 153 */
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dc.l _DummyHandler /* 154 */
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dc.l _DummyHandler /* 155 */
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dc.l _DummyHandler /* 156 */
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dc.l _DummyHandler /* 157 */
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dc.l _DummyHandler /* 158 */
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dc.l _DummyHandler /* 159 */
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dc.l _DummyHandler /* 160 */
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dc.l _DummyHandler /* 161 */
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dc.l _DummyHandler /* 162 */
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dc.l _DummyHandler /* 163 */
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dc.l _DummyHandler /* 164 */
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dc.l _DummyHandler /* 165 */
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dc.l _DummyHandler /* 166 */
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dc.l _DummyHandler /* 167 */
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dc.l _DummyHandler /* 168 */
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dc.l _DummyHandler /* 169 */
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dc.l _DummyHandler /* 170 */
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dc.l _DummyHandler /* 171 */
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dc.l _DummyHandler /* 172 */
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dc.l _DummyHandler /* 173 */
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dc.l _DummyHandler /* 174 */
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dc.l _DummyHandler /* 175 */
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dc.l _DummyHandler /* 176 */
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dc.l _DummyHandler /* 177 */
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dc.l _DummyHandler /* 178 */
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dc.l _DummyHandler /* 179 */
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dc.l _DummyHandler /* 180 */
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dc.l _DummyHandler /* 181 */
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dc.l _DummyHandler /* 182 */
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dc.l _DummyHandler /* 183 */
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dc.l _DummyHandler /* 184 */
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dc.l _DummyHandler /* 185 */
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dc.l _DummyHandler /* 186 */
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dc.l _DummyHandler /* 187 */
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dc.l _DummyHandler /* 188 */
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dc.l _DummyHandler /* 189 */
|
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dc.l _DummyHandler /* 190 */
|
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dc.l _DummyHandler /* 191 */
|
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dc.l _DummyHandler /* 192 */
|
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dc.l _DummyHandler /* 193 */
|
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dc.l _DummyHandler /* 194 */
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dc.l _DummyHandler /* 195 */
|
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dc.l _DummyHandler /* 196 */
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dc.l _DummyHandler /* 197 */
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dc.l _DummyHandler /* 198 */
|
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dc.l _DummyHandler /* 199 */
|
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dc.l _DummyHandler /* 200 */
|
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dc.l _DummyHandler /* 201 */
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dc.l _DummyHandler /* 202 */
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dc.l _DummyHandler /* 203 */
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dc.l _DummyHandler /* 204 */
|
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dc.l _DummyHandler /* 205 */
|
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dc.l _DummyHandler /* 206 */
|
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dc.l _DummyHandler /* 207 */
|
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dc.l _DummyHandler /* 208 */
|
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dc.l _DummyHandler /* 209 */
|
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dc.l _DummyHandler /* 210 */
|
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dc.l _DummyHandler /* 211 */
|
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dc.l _DummyHandler /* 212 */
|
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dc.l _DummyHandler /* 213 */
|
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dc.l _DummyHandler /* 214 */
|
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dc.l _DummyHandler /* 215 */
|
|
dc.l _DummyHandler /* 216 */
|
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dc.l _DummyHandler /* 217 */
|
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dc.l _DummyHandler /* 218 */
|
|
dc.l _DummyHandler /* 219 */
|
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dc.l _DummyHandler /* 220 */
|
|
dc.l _DummyHandler /* 221 */
|
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dc.l _DummyHandler /* 222 */
|
|
dc.l _DummyHandler /* 223 */
|
|
dc.l _DummyHandler /* 224 */
|
|
dc.l _DummyHandler /* 225 */
|
|
dc.l _DummyHandler /* 226 */
|
|
dc.l _DummyHandler /* 227 */
|
|
dc.l _DummyHandler /* 228 */
|
|
dc.l _DummyHandler /* 229 */
|
|
dc.l _DummyHandler /* 230 */
|
|
dc.l _DummyHandler /* 231 */
|
|
dc.l _DummyHandler /* 232 */
|
|
dc.l _DummyHandler /* 233 */
|
|
dc.l _DummyHandler /* 234 */
|
|
dc.l _DummyHandler /* 235 */
|
|
dc.l _DummyHandler /* 236 */
|
|
dc.l _DummyHandler /* 237 */
|
|
dc.l _DummyHandler /* 238 */
|
|
dc.l _DummyHandler /* 239 */
|
|
dc.l _DummyHandler /* 240 */
|
|
dc.l _DummyHandler /* 241 */
|
|
dc.l _DummyHandler /* 242 */
|
|
dc.l _DummyHandler /* 243 */
|
|
dc.l _DummyHandler /* 244 */
|
|
dc.l _DummyHandler /* 245 */
|
|
dc.l _DummyHandler /* 246 */
|
|
dc.l _DummyHandler /* 247 */
|
|
dc.l _DummyHandler /* 248 */
|
|
dc.l _DummyHandler /* 249 */
|
|
dc.l _DummyHandler /* 250 */
|
|
dc.l _DummyHandler /* 251 */
|
|
dc.l _DummyHandler /* 252 */
|
|
dc.l _DummyHandler /* 253 */
|
|
dc.l _DummyHandler /* 254 */
|
|
dc.l _DummyHandler /* 255 */
|
|
|
|
/*
|
|
* Define weak symbols for four alternate interrupt vectors.
|
|
* These will be used as the interrupt vectors for the four
|
|
* secondary contexts.
|
|
*/
|
|
.section .data
|
|
|
|
.global SYM (_vector_table1)
|
|
.weak SYM (_vector_table1)
|
|
.set SYM (_vector_table1), SYM (_vector_table)
|
|
|
|
.global SYM (_vector_table2)
|
|
.weak SYM (_vector_table2)
|
|
.set SYM (_vector_table2), SYM (_vector_table)
|
|
|
|
.global SYM (_vector_table3)
|
|
.weak SYM (_vector_table3)
|
|
.set SYM (_vector_table3), SYM (_vector_table)
|
|
|
|
.global SYM (_vector_table4)
|
|
.weak SYM (_vector_table4)
|
|
.set SYM (_vector_table4), SYM (_vector_table)
|
|
|
|
#endif
|