68a9101237
* or1k/Makefile.in: Add libor1k
* or1k/README: New file
* or1k/caches-asm.S: New file
* or1k/exceptions-asm.S: New file
* or1k/exceptions.c: New file
* or1k/impure.c: New file
* or1k/include/or1k-nop.h: New file
* or1k/include/or1k-support.h: New file
* or1k/interrupts-asm.S: New file
* or1k/interrupts.c: New file
* or1k/mmu-asm.S: New file
* or1k/or1k-internals.h: New file
* or1k/or1k_uart.c: New file
* or1k/or1k_uart.h: New file
* or1k/outbyte.S: New file
* or1k/sbrk.c: New file
* or1k/sync-asm.S: New file
* or1k/syscalls.c: New file
* or1k/timer.c: New file
* or1k/util.c: New file
136 lines
2.9 KiB
ArmAsm
136 lines
2.9 KiB
ArmAsm
#include "include/or1k-asm.h"
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#include "include/or1k-sprs.h"
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.section .text
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.global or1k_has_multicore_support
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.type or1k_has_multicore_support,@function
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or1k_has_multicore_support:
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#ifdef __OR1K_MULTICORE__
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// Return 1
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OR1K_DELAYED(
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OR1K_INST(l.ori r11,r0,1),
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OR1K_INST(l.jr r9)
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)
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#else
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// Return 0
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OR1K_DELAYED(
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OR1K_INST(l.or r11,r0,r0),
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OR1K_INST(l.jr r9)
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)
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#endif
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.global or1k_coreid
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.type or1k_coreid,@function
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or1k_coreid:
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#ifdef __OR1K_MULTICORE__
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// Return SPR with core identifier
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OR1K_DELAYED(
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OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_COREID_ADDR),
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OR1K_INST(l.jr r9)
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)
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#else
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// Return 0
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OR1K_DELAYED(
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OR1K_INST(l.or r11,r0,r0),
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OR1K_INST(l.jr r9)
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)
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#endif
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.global or1k_numcores
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.type or1k_numcores,@function
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or1k_numcores:
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#ifdef __OR1K_MULTICORE__
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// Return SPR with number of cores
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OR1K_DELAYED(
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OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_NUMCORES_ADDR),
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OR1K_INST(l.jr r9)
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)
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#else
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// Return 1
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OR1K_DELAYED(
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OR1K_INST(l.ori r11,r0,1),
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OR1K_INST(l.jr r9)
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)
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#endif
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.global or1k_sync_ll
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.type or1k_sync_ll,@function
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or1k_sync_ll:
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#ifdef __OR1K_MULTICORE__
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// Load word atomic
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OR1K_DELAYED(
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OR1K_INST(l.lwa r11, 0(r3)),
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OR1K_INST(l.jr r9)
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)
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#else
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// Simply load word, TODO: throw exception? which?
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OR1K_DELAYED(
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OR1K_INST(l.lwz r11, 0(r3)),
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OR1K_INST(l.jr r9)
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)
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#endif
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.global or1k_sync_sc
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.type or1k_sync_sc,@function
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or1k_sync_sc:
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#ifdef __OR1K_MULTICORE__
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// swa sets the flag if it was succesfull
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// Store the value to address and set flag
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l.swa 0(r3),r4
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OR1K_DELAYED(
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// Set return to success speculatively (may go to delay slot)
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OR1K_INST(l.ori r11,r0,1),
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// If the swa was successfull, jump to end
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OR1K_INST(l.bf .or1k_sync_sc_done)
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)
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// If the swa was not successfull, set
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l.or r11,r0,r0
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.or1k_sync_sc_done:
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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#else
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// Simply store word, TODO: throw exception? which?
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OR1K_DELAYED(
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OR1K_INST(l.sw 0(r3),r4),
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OR1K_INST(l.jr r9)
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)
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#endif
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.global or1k_sync_cas
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.type or1k_sync_sc,@function
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or1k_sync_cas:
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#ifdef __OR1K_MULTICORE__
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/* Load linked address value to return register */
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l.lwa r11,0(r3)
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/* Compare value to parameter */
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l.sfeq r11,r4
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/* If not equal: abort and return the read value */
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done))
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/* If compare was successfull: try writing */
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l.swa 0(r3),r5
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/* If writing was not successful: restart */
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf or1k_sync_cas))
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.or1k_sync_cas_done:
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/* Return value is the original read value */
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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#else
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// Non-atomic CAS, TODO: throw exception? which?
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l.lwz r11,0(r3)
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l.sfeq r11,r4
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OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done))
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l.sw 0(r3),r5
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.or1k_sync_cas_done:
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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#endif
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.global or1k_sync_tsl
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.type or1k_sync_tsl,@function
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or1k_sync_tsl:
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l.or r4,r0,r0
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OR1K_DELAYED(
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OR1K_INST(l.addi r5,r0,1),
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OR1K_INST(l.j or1k_sync_cas)
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)
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