6e9c1e8dd5
* mep/default.ld: New. * mep/gmap_default.ld: Change default endian to little. * mep/sim-crt0.S: Maintain 8-byte stack alignment. * mep/sim-crtn.S: Likewise.
500 lines
10 KiB
ArmAsm
500 lines
10 KiB
ArmAsm
# Copyright (c) 2003 Red Hat, Inc. All rights reserved.
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#
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# This copyrighted material is made available to anyone wishing to use, modify,
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# copy, or redistribute it subject to the terms and conditions of the BSD
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# License. This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY expressed or implied, including the implied
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# warranties of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. A copy of
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# this license is available at http://www.opensource.org/licenses. Any Red Hat
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# trademarks that are incorporated in the source code or documentation are not
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# subject to the BSD License and may only be used or replicated with the express
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# permission of Red Hat, Inc.
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#
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# Toshiba Media Processor startup file (crt0.S)
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#
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# Designed for user programs running in the 0-2Mb startup section.
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# Designed for the simulator by default.
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#
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# Exception/Interrupt Handler Locations
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# CFG.EVM CFG.EVA CFG.IVA Exception INTn
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## 0 - - 0x0000_0000 0x0000_0030 rom
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## 1 0 0 0x0020_0000 0x0020_0030 local RAM / local RAM
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## 1 1 0 0x0080_0000 0x0020_0000 ext RAM / local RAM
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## 1 0 1 0x0020_0000 0x0080_0000 local RAM / ext RAM
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## 1 1 1 0x0080_0000 0x0080_0030 ext RAM / ext RAM
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#
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# Exceptions
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# Reset 0x0000_0000
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# NMI 0x0000_0000+4
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# RI (Base Address) +0x08
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# ZDIV (Base Address) +0x0C
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# BRK (Base Address) +0x10
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# SWI (Base Address) +0x14
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# DSP (Base Address) +0x1C
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# COP (Base Address) +0x20
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.set _local_ram_base, 0x00200000
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.set _ext_ram_base, 0x00800000
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.set _int_base_offset, 0x30
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#include "syscall.h"
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.macro if_bitfield_zero reg, start, length, label
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ldc $0, \reg
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srl $0, \start
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and3 $0, $0, (1 << \length) - 1
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beqz $0,\label
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.endm
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.macro if_bitfield_notN reg, start, length, N, label
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ldc $0, \reg
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srl $0, \start
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and3 $0, $0, (1 << \length) - 1
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bnei $0,\N, \label
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.endm
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.macro if_bitfield_eqN reg, start, length, N, label
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ldc $0, \reg
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srl $0, \start
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and3 $0, $0, (1 << \length) - 1
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beqi $0,\N, \label
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.endm
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.macro if_bitfield_ltN reg, start, length, N, label
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ldc $0, \reg
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srl $0, \start
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and3 $0, $0, (1 << \length) - 1
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blti $0,\N, \label
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.endm
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.section .hwinit, "ax"
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# CCFG.ICSZ
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if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_enable_icache
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__enable_icache:
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# set ICE(cfg[1])
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ldc $1,$cfg
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or3 $1,$1,2
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stc $1,$cfg
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nop
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nop
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nop
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nop
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nop
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.Lend_enable_icache:
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ret
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__enable_dcache:
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# CCFG.DCSZ
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if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_enable_dcache
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# set DCE(cfg[0])
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ldc $1,$cfg
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or3 $1,$1,1
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stc $1,$cfg
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nop
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nop
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nop
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nop
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nop
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ret
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.Lend_enable_dcache:
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.text
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#ifdef NOVEC
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.global _reset
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_reset:
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#endif
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.global _start
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_start:
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mov $fp, 0 # for unwinding
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# $sp set
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movh $sp, %uhi(__stack_table)
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or3 $sp, $sp, %lo(__stack_table)
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# initialize sp, gp, tp
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# get CPU ID
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ldc $0, $id
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srl $0, 16
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# load ID-specific stack pointer
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sl2ad3 $0, $0, $sp # $0 = ($0 << 2) + $sp
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lw $sp,($0) # $sp = *($0)
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mov $0,0xfff8
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and $sp, $0
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#ifndef NOVEC
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# copy exception vector table
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# RCFG.IRSZ
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if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_ev_imem
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# handle imem
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movh $11,%uhi(_local_ram_base)
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or3 $11,$11,%lo(_local_ram_base)
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# clear CFG.EVA ([23])
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ldc $0,$cfg
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movh $1, %uhi(0xff7fffff)
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or3 $1, $1, %lo(0xff7fffff)
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and $0,$1
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stc $0,$cfg
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bra .Ldo_repeat_ev
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.Lend_ev_imem:
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#ifdef UseSDRAM
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movh $11,%uhi(_ext_ram_base)
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or3 $11,$11,%lo(_ext_ram_base)
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# set CFG.EVA ([23])
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ldc $0,$cfg
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movh $1,%uhi(1<<23)
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or3 $1,$1,%lo(1<<23)
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or $0,$1
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stc $0,$cfg
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#else
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# handle ROM
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bra .Lend_ev
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#endif
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.Ldo_repeat_ev:
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# set CFG.EVM ([4])
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ldc $0,$cfg
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or3 $0,$0,(1<<4)
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stc $0,$cfg
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# copy _exception_table to $11
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movh $12,%uhi(_exception_table)
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or3 $12,$12,%lo(_exception_table)
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mov $13,8
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repeat $13,.Lrepeat_ev
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lw $1,0($12)
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add $12,4
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.Lrepeat_ev:
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sw $1,0($11)
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add $11,4
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.Lend_ev:
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# copy interrupt vector table
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# RCFG.IRSZ
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if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_iv_imem
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# handle imem
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movh $11,%uhi(_local_ram_base)
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or3 $11,$11,%lo(_int_base_offset)
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# clear CFG.IVA ([22])
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ldc $0,$cfg
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movh $1,%uhi(0xffbfffff) # ~(1<<22)
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or3 $1,$1,%lo(0xffbfffff)
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and $0,$1
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stc $0,$cfg
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bra .Ldo_repeat_iv
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.Lend_iv_imem:
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#ifdef UseSDRAM
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movh $11,%uhi(_ext_ram_base)
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or3 $11,$11,%lo(_int_base_offset)
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# set CFG. IVA ([22])
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ldc $0,$cfg
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movh $1,%uhi(1<<22)
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or3 $1,$1,%lo(1<<22)
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or $0,$1
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stc $0,$cfg
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#else
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# handle ROM
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bra .Lend_iv
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#endif
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.Ldo_repeat_iv:
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# set CFG.IVM ([3])
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ldc $0,$cfg
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or3 $0,$0,(1<<3)
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stc $0,$cfg
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# copy _interrupt_table to $11
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movh $12,%uhi(_interrupt_table)
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or3 $12,$12,%lo(_interrupt_table)
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mov $13,32
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add $13,-1
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and3 $13,$13,127
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repeat $13,.Lrepeat_iv
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lw $1,0($12)
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add $12,4
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.Lrepeat_iv:
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sw $1,0($11)
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add $11,4
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.Lend_iv:
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# initialize instruction cache
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# Icache Size CCFG.ICSZ ([22..16]) KByte
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if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_ic
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mov $3,$0 # cache size in KB
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# ID.ID
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if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_ic
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# Line Size CCFG.ICSZ ([26..24]) Byte
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if_bitfield_ltN reg=$ccfg, start=24, length=3, N=2, label=.Lend_ic
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bgei $0,5,.Lend_ic
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add3 $1,$0,3 # bit width of line size
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mov $0,$3
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# clear tag
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mov $2,10
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sub $2,$1
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sll $0,$2 # *KByte/(line size)
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add $0,-1
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mov $2,1
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sll $2,$1 # line size
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bra .Ldo_repeat_icache
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.Lend_mepc3_ic:
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# ICache: $0 KByte
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mov $0,$3
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# clear tag
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sll $0,(10-5) # *KByte/(32byte=linesize)
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add $0,-1
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mov $2,32
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.Ldo_repeat_icache:
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mov $1,0
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bra 0f
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# Align this code on an 8 byte boundary in order to keep the repeat
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# loop entirely within the instruction fetch buffer.
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.p2align 3
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0:
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movh $3,%hi(0x00310000) # for tag
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repeat $0,.Lrepeat_icache
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add $0,-1
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.Lrepeat_icache:
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sw $1,0($3)
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add3 $3,$3,$2
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.Lenable_icache:
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movh $1,%hi(__enable_icache)
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add3 $1,$1,%lo(__enable_icache)
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jsr $1
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.Lend_ic:
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# initialize data cache
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# Dcache Size CCFG.DCSZ ([6..0]) KByte
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if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_dc
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mov $3,$0 # cache size in KB
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# ID.ID
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if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_dc
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# Line Size CCFG.DCSZ ([10..8]) Byte
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if_bitfield_ltN reg=$ccfg, start=8, length=3, N=2, label=.Lend_dc
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bgei $0,5,.Lend_dc
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add3 $1,$0,3 # bit width of line size
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mov $0,$3
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# clear tag
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mov $2,10
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sub $2,$1
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sll $0,$2 # *KByte/(line size)
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add $0,-1
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mov $2,1
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sll $2,$1 # line size
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bra .Ldo_repeat_dcache
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.Lend_mepc3_dc:
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# DCache: $0 KByte
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mov $0,$3
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# clear tag
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sll $0,(10-5) # *KByte/(32byte=linesize)
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add $0,-1
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mov $2,32
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.Ldo_repeat_dcache:
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mov $1,0
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movh $3,%hi(0x00330000) # for tag
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repeat $0,.Lrepeat_dcache
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add $0,-1
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.Lrepeat_dcache:
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sw $1,0($3)
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add3 $3,$3,$2
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.Lenable_dcache:
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movh $1,%hi(__enable_dcache)
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add3 $1,$1,%lo(__enable_dcache)
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jsr $1
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.Lend_dc:
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# NOVEC
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#endif
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mov $0, 0
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movh $gp, %uhi(__sdabase)
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or3 $gp, $gp, %lo(__sdabase)
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movh $tp, %uhi(__tpbase)
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or3 $tp, $tp, %lo(__tpbase)
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# zero out BSS
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movh $1, %uhi(__bss_start)
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or3 $1, $1, %lo(__bss_start)
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mov $2, 0
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movh $3, %uhi(_end)
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or3 $3, $3, %lo(_end)
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sub $3, $1
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bsr memset
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movh $1, %uhi(__sbss_start)
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or3 $1, $1, %lo(__sbss_start)
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mov $2, 0
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movh $3, %uhi(__sbss_end)
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or3 $3, $3, %lo(__sbss_end)
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sub $3, $1
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bsr memset
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movh $1, %uhi(__farbss_start)
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or3 $1, $1, %lo(__farbss_start)
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mov $2, 0
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movh $3, %uhi(__farbss_end)
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or3 $3, $3, %lo(__farbss_end)
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sub $3, $1
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bsr memset
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# enable interrupts
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ei
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# construct global class variables
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bsr __invoke_init_section
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# invoke main
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mov $1, 0 # argc, argv, envp
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mov $2, 0
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mov $3, 0
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bsr main
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mov $1, $0
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bsr exit
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.global _exit
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_exit:
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# Prevent _exit recursion
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movh $3, %uhi(_exit_in_progress)
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or3 $3, $3, %lo(_exit_in_progress)
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lw $5, ($3)
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bnez $5, _skip_fini
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mov $5, 1
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sw $5, ($3)
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# We don't need to preserve $5 because we're going to exit anyway.
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mov $5,$1
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# destruct global class variables
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bsr __invoke_fini_section
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mov $1,$5
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_skip_fini:
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#ifdef NOSIM
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_exit_loop:
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bra _exit_loop
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#else
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.2byte 0x7800 | ((SYS_exit & 0xe) << 7) | ((SYS_exit & 1) << 4)
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ret
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#endif
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.data
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_exit_in_progress: .word 0
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# For these two, the epilogue is in crtn.S
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.section .init
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__invoke_init_section:
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add $sp, -8
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ldc $0, $lp
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sw $0, ($sp)
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.section .fini
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__invoke_fini_section:
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add $sp, -8
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ldc $0, $lp
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sw $0, ($sp)
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#ifndef NOVEC
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.section .vec, "ax"
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.core
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.org 0x0, 0
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.global _exception_table
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.type _exception_table,@function
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_exception_table:
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.p2align 2
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.org 0x0000, 0
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.global _reset
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_reset:
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jmp _handler_RESET
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.org 0x0004, 0
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jmp _handler_NMI
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.org 0x0008, 0
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jmp _handler_RI
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.org 0x000c, 0
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jmp _handler_ZDIV
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.org 0x0010, 0
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jmp _handler_BRK
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.org 0x0014, 0
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jmp _handler_SWI
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.org 0x0018, 0
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jmp _handler_DEBUG
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.org 0x001c, 0
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jmp _handler_DSP
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.org 0x0020, 0
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jmp _handler_COP
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.org 0x30, 0
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.global _interrupt_table
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.type _interrupt_table,@function
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_interrupt_table:
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.org 0x0030
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jmp _handler_INT0
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.org 0x0034
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jmp _handler_INT1
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.org 0x0038
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jmp _handler_INT2
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.org 0x003c
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jmp _handler_INT3
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.org 0x0040
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jmp _handler_INT4
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.org 0x0044
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jmp _handler_INT5
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.org 0x0048
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jmp _handler_INT6
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.org 0x004c
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jmp _handler_INT7
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.org 0x0050
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jmp _handler_INT8
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.org 0x0054
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jmp _handler_INT9
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.org 0x0058
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jmp _handler_INT10
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.org 0x005c
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jmp _handler_INT11
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.org 0x0060
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jmp _handler_INT12
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.org 0x0064
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jmp _handler_INT13
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.org 0x0068
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jmp _handler_INT14
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.org 0x006c
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jmp _handler_INT15
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.org 0x0070
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jmp _handler_INT16
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.org 0x0074
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jmp _handler_INT17
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.org 0x0078
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jmp _handler_INT18
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.org 0x007c
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jmp _handler_INT19
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.org 0x0080
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jmp _handler_INT20
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.org 0x0084
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jmp _handler_INT21
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.org 0x0088
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jmp _handler_INT22
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.org 0x008c
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jmp _handler_INT23
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.org 0x0090
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jmp _handler_INT24
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.org 0x0094
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jmp _handler_INT25
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.org 0x0098
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jmp _handler_INT26
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.org 0x009c
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jmp _handler_INT27
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.org 0x00a0
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jmp _handler_INT28
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.org 0x00a4
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jmp _handler_INT29
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.org 0x00a8
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jmp _handler_INT30
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.org 0x00ac
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jmp _handler_INT31
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# NOVEC
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#endif
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